CN106094377A - A kind of array base palte and display panels - Google Patents
A kind of array base palte and display panels Download PDFInfo
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- CN106094377A CN106094377A CN201610592025.4A CN201610592025A CN106094377A CN 106094377 A CN106094377 A CN 106094377A CN 201610592025 A CN201610592025 A CN 201610592025A CN 106094377 A CN106094377 A CN 106094377A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Power Engineering (AREA)
Abstract
The present invention provides a kind of array base palte and display panels, and described array base palte includes: main pixel portion, has the first film transistor and the first pixel electrode；Sub-pixel portion, there is the second thin film transistor (TFT) and the second pixel electrode, described second thin film transistor (TFT) has second grid, second source electrode, second drain electrode, described second grid is connected with described scan line, described second source electrode is connected with described data wire, described second drain electrode is connected with described second pixel electrode, described sub-pixel portion also includes sharing electric capacity, described electric capacity of sharing is to be formed with corresponding scan line by described second pixel electrode, described electric capacity of sharing is for being adjusted the brightness in described sub-pixel portion, so that the brightness in described main pixel portion is different from the brightness of described sub-pixel.Due to the fact that and need not arrange extra thin film transistor (TFT) and share electric capacity, thus improve the penetrance of panel.
Description
[technical field]
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and display panels.
[background technology]
Currently in order to increase visual angle, generally pixel electrode is made the structure of " rice " font, comprises the vertical trunk of strip
With the horizontal trunk of strip, this vertical trunk and horizontal trunk be referred to as stem portion (main-pixel), wherein vertically trunk and
Horizontal trunk center intersects vertically, and so-called center intersects vertically, and i.e. refers to that vertical trunk and horizontal trunk are mutually perpendicular to, and this is vertical
Whole pixel electrode area is divided into 4 regions (sub-pixel), these 4 pixel electrode area by trunk and horizontal trunk
It is referred to as branch；Each pixel electrode area by with vertical trunk or horizontal trunk in ± 45 °, the strip of ± 135 ° of angles divides
Prop up (slit) tiling composition, namely each strip branch is in the same plane with vertical trunk and horizontal trunk, is thusly-formed
Descend and the pixel electrode structure of left and right " rice " font of specular respectively.The pixel electrode structure of this " rice " font, due to
Strip branch in branch is identical with the angle of horizontal trunk and vertical trunk, can there is certain visual color or visual color
Partially, the penetrance causing panel declines.
Being divided into two independent pixel electrodes to improve visual color or visual color assistant general's sub-pixel, each electrode uses
" rice " font structure designs, and as described in Figure 1, Fig. 1 only provides the structural representation of a pixel, and described pixel includes: main pixel
Portion 101 and sub-pixel portion 102；Wherein, described main pixel portion 101 has the first film transistor T1, and described sub-pixel portion 102 has
The second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, described 3rd thin film transistor (TFT) T3 is had to connect and share electric capacity 14.
The first grid of described the first film transistor T1 and the second grid of described second thin film transistor (TFT) T2 connect phase
Same scan line 11；First source electrode of described the first film transistor T1 and second source electrode of described second thin film transistor (TFT) T2 are even
Connect identical data wire 12, the grid connexon scan line 11 ' of described 3rd thin film transistor (TFT) T3, described the first film transistor
First drain electrode of T1 connects second drain electrode of the first pixel electrode and described second thin film transistor (TFT) T2 by passing through by through hole
Bore a hole the second pixel electrode；When described the first film transistor T1 and described second thin film transistor (TFT) T2 closes, described 3rd thin
Film transistor T3 turns on, and at this moment a part of electric charge on the second pixel electrode has been transferred to share by the 3rd thin film transistor (TFT) T3
On electric capacity 14, so that the voltage at the second liquid crystal capacitance two ends corresponding to the second pixel electrode is less than the first liquid crystal capacitance two ends
Voltage, thus reduce big visual angle colour cast problem.But a part can be taken hold owing to sharing electric capacity and the 3rd thin film transistor (TFT)
Mouth rate, therefore reduces the penetrance of panel.
[summary of the invention]
It is an object of the present invention to provide a kind of array base palte and display panels, to solve existing array base
The penetrance of plate is than relatively low technical problem.
For solving above-mentioned technical problem, the present invention constructs a kind of array base palte, comprising:
Data wire, scan line and the multiple pixels being staggered to form by described data wire and described scan line；Described pixel
Including:
Main pixel portion, has the first film transistor and the first pixel electrode；Described the first film transistor has first
Grid, the first source electrode, the first drain electrode, described first grid is connected with described scan line, described first source electrode and described data wire
Connecting, described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion, has the second thin film transistor (TFT) and the second pixel electrode, and described second thin film transistor (TFT) has second
Grid, the second source electrode, the second drain electrode, described second grid is connected with described scan line, described second source electrode and described data wire
Connect, described second drain electrode is connected with described second pixel electrode, described sub-pixel portion also includes sharing electric capacity, described in share electricity
Appearance is to be formed with corresponding scan line by described second pixel electrode, described in share electric capacity for described sub-pixel portion
Brightness is adjusted, so that the brightness in described main pixel portion is different from the brightness of described sub-pixel.
In the array base palte of the present invention, described in share electric capacity particular by by first projection with the second projection section weight
Folded formation, wherein said first is projected as the projection on the underlay substrate of described array base palte of described two pixel electrodes, institute
State second and be projected as the projection on the underlay substrate of described array base palte of scan line corresponding to described pixel.
In the array base palte of the present invention, described in share electric capacity for when described scan line is scanned, adjust described
The pixel voltage in sub-pixel portion, is adjusted with the brightness to described sub-pixel portion.
In the array base palte of the present invention, when the voltage of described data wire input positive polarity, described main pixel portion bright
Degree is more than the brightness in described sub-pixel portion.
In the array base palte of the present invention, when the voltage of described data wire input negative polarity, described sub-pixel portion bright
Degree is more than the brightness in described main pixel portion.
In the array base palte of the present invention, described array base palte also includes public electrode；Described first pixel electrode and institute
State and between public electrode, form the first storage electric capacity, between described second pixel electrode and described public electrode, form the second storage
Electric capacity.
The present invention also provides for a kind of display panels, and it includes
Color membrane substrates；
Liquid crystal layer；
Array base palte, is oppositely arranged with described color membrane substrates, and described array base palte includes:
Data wire, scan line and the multiple pixels being staggered to form by described data wire and described scan line；Described pixel
Including:
Main pixel portion, has the first film transistor and the first pixel electrode；Described the first film transistor has first
Grid, the first source electrode, the first drain electrode, described first grid is connected with described scan line, described first source electrode and described data wire
Connecting, described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion, has the second thin film transistor (TFT) and the second pixel electrode, and described second thin film transistor (TFT) has second
Grid, the second source electrode, the second drain electrode, described second grid is connected with described scan line, described second source electrode and described data wire
Connect, described second drain electrode is connected with described second pixel electrode, described sub-pixel portion also includes sharing electric capacity, described in share electricity
Appearance is to be formed with corresponding scan line by described second pixel electrode, described in share electric capacity for described sub-pixel portion
Brightness is adjusted, so that the brightness in described main pixel portion is different from the brightness of described sub-pixel.
In the display panels of the present invention, described in share electric capacity particular by by first projection with the second Projection Division
Point overlapping to form, wherein said first is projected as the throwing on the underlay substrate of described array base palte of described two pixel electrodes
Shadow, described second is projected as the projection on the underlay substrate of described array base palte of scan line corresponding to described pixel.
In the display panels of the present invention, described in share electric capacity for when described scan line is scanned, adjust
The pixel voltage in described sub-pixel portion, is adjusted with the brightness to described sub-pixel portion.
In the display panels of the present invention, when the voltage of described data wire input positive polarity, described main pixel portion
Brightness more than the brightness in described sub-pixel portion.
The array base palte of the present invention and display panels, by by shape between pixel electrode and the scan line in sub-pixel portion
Become to share electric capacity, adjust the brightness in sub-pixel portion by sharing electric capacity, so that the brightness in main pixel portion and the brightness in sub-pixel portion
Difference, owing to need not arrange extra thin film transistor (TFT) and share electric capacity, thus improves the penetrance of panel.
[accompanying drawing explanation]
Fig. 1 is the perspective structure schematic diagram of array base palte in prior art；
Fig. 2 is the perspective structure schematic diagram of array base palte of the present invention；
Fig. 3 is the equivalent circuit diagram of array base palte of the present invention.
[detailed description of the invention]
The explanation of following embodiment is particular implementation that is graphic with reference to add, that implement in order to illustrate the present invention may be used to
Example.The direction term that the present invention is previously mentioned, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side "
Deng, it is only the direction with reference to annexed drawings.Therefore, the direction term of use is to illustrate and understand the present invention, and is not used to
Limit the present invention.In the drawings, the unit that structure is similar is to represent with identical label.
Refer to the perspective structure schematic diagram of Fig. 2, Fig. 2 array base palte of the present invention.
Technical scheme eliminates the 3rd thin film transistor (TFT) T3 in Fig. 1 to share electric capacity 14；
As in figure 2 it is shown, described array base palte includes data wire 12, scan line 11 and by described data wire and described scanning
Multiple pixels that line is staggered to form；Described array base palte also includes common wire 13；
Described pixel includes: main pixel portion 201 and sub-pixel portion 202；
In conjunction with Fig. 3, described main pixel portion 201, there is the first film transistor T1 and the first pixel electrode, described first thin
Film transistor T1 has first grid, the first source electrode, the first drain electrode, and described first grid is connected with described scan line 11, described
First source electrode is connected with described data wire 12, and described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion 202, has the second thin film transistor (TFT) T2 and the second pixel electrode, described second thin film transistor (TFT) T2 tool
Having second grid, the second source electrode, the second drain electrode, described second grid is connected with described scan line 11, described second source electrode and institute
Stating data wire 12 to connect, described second drain electrode is connected with described second pixel electrode, and described sub-pixel portion also includes sharing electric capacity,
Described electric capacity of sharing is to be formed with corresponding scan line by described second pixel electrode, described in share electric capacity for described
The brightness in sub-pixel portion is adjusted, and the brightness making described main pixel portion is different from the brightness of described sub-pixel.Described main pixel
Portion 201 and described sub-pixel portion 202 all include multiple display farmland.The scan line of the most above-mentioned correspondence is to the input scanning of this pixel
The scan line of signal.
Share electric capacity owing to being generated by scan line and pixel electrode, therefore need not to be separately provided and extra share electricity
Hold, it is not required that arrange and control this thin film transistor (TFT) sharing electric capacity, therefore improve penetrance.
Preferably, share electric capacity described in overlap to form, wherein particular by by the first projection and second projection section
Described first is projected as the projection on the underlay substrate of described array base palte of described two pixel electrodes, and described second is projected as institute
State the projection on the underlay substrate of described array base palte of scan line corresponding to pixel.Such as, the pixel in the sub-pixel portion of pixel
Electrode and for this pixel input scanning signal scan line 11 between lap as shown in the dotted line frame 203 in Fig. 2,
Namely electric capacity is shared in formation in described overlapping region 203.
Share electric capacity owing to being formed by the way of overlapping between two conductive layers, simplify making technology, reduce life
Produce cost.
Preferably, described in share electric capacity for when described scan line is scanned, adjust the pixel in described sub-pixel portion
Voltage, is adjusted with the brightness to described sub-pixel portion.
Due to share electric capacity have scanning signal input time, be charged to pixel electrode side；When corresponding the sweeping of this pixel
Retouch line scanning signal input complete time, share electric capacity electric discharge so that sub-pixel portion current potential send change.
Preferably, described array base palte also includes public electrode；Between described first pixel electrode and described public electrode
Form the first storage electric capacity, between described second pixel electrode and described public electrode, form the second storage electric capacity.Specifically
Lap between described first pixel electrode and described public electrode forms the first storage electric capacity, in described second pixel
Lap between electrode and described public electrode forms the second storage electric capacity.
Connect particularly in connection with Fig. 3, the first film transistor T1 and the first pixel electrode, the first pixel electrode and color film base
The public electrode U1 of the first liquid crystal capacitance Clc1, the first pixel electrode and array base palte side is formed between the public electrode U0 of plate side
Between formed first storage electric capacity Cst1.
Second thin film transistor (TFT) T2 and the second pixel electrode connect, the second pixel electrode and the public electrode of color membrane substrates side
Form the second liquid crystal capacitance Clc2 between U0, form second between the public electrode U1 of the second pixel electrode and array base palte side and deposit
Storage electric capacity Cst2, is formed between the second pixel electrode with scan line 11 and shares electric capacity Cst3.
Preferably, when described data wire 12 inputs the voltage of positive polarity, the brightness in described main pixel portion 201 is more than described
The brightness in sub-pixel portion 202.Owing to sharing electric capacity, a part of electric charge in sub-pixel portion is discharged, therefore in input positive polarity
During data signal, the brightness in main pixel portion 201 is more than the brightness in described sub-pixel portion 202.
Preferably, when described data wire 12 inputs the voltage of negative polarity, the brightness in described sub-pixel portion 202 is more than described
The brightness in main pixel portion 201.Owing to sharing electric capacity, a part of electric charge in sub-pixel portion 202 is discharged, therefore at input negative pole
Property data signal time, the brightness in main pixel portion 201 is less than the brightness in described sub-pixel portion 202.
Specifically, the voltage difference between main pixel portion 201 and sub-pixel portion 202 is Δ V, and wherein Δ V is concrete such as formula 1 institute
Show:
Wherein Vgh and Vgl represents that (namely scan line has height to the voltage when grid of thin film transistor (TFT) opens and closes respectively
The scanning signal input of level and voltage when not having the scanning signal input of high level), Cst2 represents the of sub-pixel portion 202
Two storage electric capacity, Cst3 represents the electric capacity of sharing in sub-pixel portion, and Clc2 represents the liquid crystal capacitance in sub-pixel portion.
The characteristic depending mainly on the size of thin film transistor (TFT) of Vgh and Vgl, owing to being limited by technique, therefore adjusts
Scope is less.Therefore can be regulated the size of Δ V by the ratio adjusting Cst3 and Cst2, Δ V is always negative, namely according to
The capacitance sharing electric capacity and the second storage electric capacity arranges the luminance difference in main pixel portion and sub-pixel portion.Number in input positive polarity
During the number of it is believed that, the brightness in sub-pixel portion 202 is less than the brightness in main pixel portion 201, when inputting the data signal of negative polarity, sub-picture
The brightness in element portion 202 is more than the brightness in main pixel portion 201, the main picture in sub-pixel portion and half owing to there being half on array base palte
Element portion, therefore can make to have clock to have the pixel of half the brightest in a frame picture, and the pixel of half is partially dark, and overall brightness is not sent out
Changing.Compared with brightness with the existing sub-pixel portion dark brightness in main pixel portion all the time, penetrance slightly promotes.
The array base palte of the present invention is by sharing formed between the pixel electrode in sub-pixel portion and scan line with electric capacity, logical
Cross the brightness sharing electric capacity adjustment sub-pixel portion, so that the brightness in main pixel portion is different from the brightness in sub-pixel portion, owing to being not required to
Extra thin film transistor (TFT) it is set and shares electric capacity, thus improve the penetrance of panel.
The present invention also provides for a kind of display panels, described display panels include liquid crystal layer, color membrane substrates and
Array base palte, wherein color membrane substrates is oppositely arranged with array base palte, and liquid crystal layer is positioned at described array base palte and described color membrane substrates
Between, described array base palte can be any one array base palte above-mentioned, the specifically technical scheme of the array base palte of the present invention
Eliminate the 3rd thin film transistor (TFT) T3 in Fig. 1 to share electric capacity 14；
As in figure 2 it is shown, described array base palte includes data wire 12, scan line 11 and by described data wire and described scanning
Multiple pixels that line is staggered to form；Described array base palte also includes common wire 13；
Described pixel includes: main pixel portion 201 and sub-pixel portion 202；
In conjunction with Fig. 3, described main pixel portion 201, there is the first film transistor T1 and the first pixel electrode, described first thin
Film transistor T1 has first grid, the first source electrode, the first drain electrode, and described first grid is connected with described scan line 11, described
First source electrode is connected with described data wire 12, and described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion 202, has the second thin film transistor (TFT) T2 and the second pixel electrode, described second thin film transistor (TFT) T2 tool
Having second grid, the second source electrode, the second drain electrode, described second grid is connected with described scan line 11, described second source electrode and institute
Stating data wire 12 to connect, described second drain electrode is connected with described second pixel electrode, and described sub-pixel portion also includes sharing electric capacity,
Described electric capacity of sharing is to be formed with corresponding scan line by described second pixel electrode, described in share electric capacity for described
The brightness in sub-pixel portion is adjusted, and the brightness making described main pixel portion is different from the brightness of described sub-pixel.Described main pixel
Portion 201 and described sub-pixel portion 202 all include multiple display farmland.
Share electric capacity owing to being generated by scan line and pixel electrode, therefore need not to be separately provided and extra share electricity
Hold, it is not required that arrange and control this thin film transistor (TFT) sharing electric capacity, therefore improve penetrance.
Preferably, share electric capacity described in overlap to form, wherein particular by by the first projection and second projection section
Described first is projected as the projection on the underlay substrate of described array base palte of described two pixel electrodes, and described second is projected as institute
State the projection on the underlay substrate of described array base palte of scan line corresponding to pixel.Such as, the pixel in the sub-pixel portion of pixel
Electrode and for this pixel input scanning signal scan line 11 between lap as shown in the dotted line frame 203 in Fig. 2,
Namely electric capacity is shared in formation in described overlapping region 203.
Share electric capacity owing to being formed by the way of overlapping between two conductive layers, simplify making technology, reduce life
Produce cost.
Preferably, described in share electric capacity for when described scan line is scanned, adjust the pixel in described sub-pixel portion
Voltage, is adjusted with the brightness to described sub-pixel portion.
Due to share electric capacity have scanning signal input time, be charged to pixel electrode side；When corresponding the sweeping of this pixel
Retouch line scanning signal input complete time, share electric capacity electric discharge so that sub-pixel portion current potential send change.
Preferably, described array base palte also includes public electrode；Between described first pixel electrode and described public electrode
Form the first storage electric capacity, between described second pixel electrode and described public electrode, form the second storage electric capacity.Specifically
Lap between described first pixel electrode and described public electrode forms the first storage electric capacity, in described second pixel
Lap between electrode and described public electrode forms the second storage electric capacity.
Connect particularly in connection with Fig. 3, the first film transistor T1 and the first pixel electrode, the first pixel electrode and color film base
The public electrode U1 of the first liquid crystal capacitance Clc1, the first pixel electrode and array base palte side is formed between the public electrode U0 of plate side
Between formed first storage electric capacity Cst1.
Second thin film transistor (TFT) T2 and the second pixel electrode connect, the second pixel electrode and the public electrode of color membrane substrates side
Form the second liquid crystal capacitance Clc2 between U0, form second between the public electrode U1 of the second pixel electrode and array base palte side and deposit
Storage electric capacity Cst2, is formed between the second pixel electrode with scan line 11 and shares electric capacity Cst3.
Preferably, when described data wire 12 inputs the voltage of positive polarity, the brightness in described main pixel portion 201 is more than described
The brightness in sub-pixel portion 202.Owing to sharing electric capacity, a part of electric charge in sub-pixel portion 202 is discharged, therefore at input positive pole
Property data signal time, the brightness in main pixel portion 201 is more than the brightness in described sub-pixel portion 202.
Preferably, when described data wire 12 inputs the voltage of negative polarity, the brightness in described sub-pixel portion 202 is more than described
The brightness in main pixel portion 201.Owing to sharing electric capacity, a part of electric charge in sub-pixel portion 202 is discharged, therefore at input negative pole
Property data signal time, the brightness in main pixel portion 201 is less than the brightness in described sub-pixel portion 202.
Specifically, the voltage difference between main pixel portion 201 and sub-pixel portion 202 is Δ V, and wherein Δ V is concrete such as formula 1 institute
Show:
Wherein Vgh and Vgl represents that (namely scan line has height to the voltage when grid of thin film transistor (TFT) opens and closes respectively
The scanning signal input of level and voltage when not having the scanning signal input of high level), Cst2 represents the of sub-pixel portion 202
Two storage electric capacity, Cst3 represents the electric capacity of sharing in sub-pixel portion, and Clc2 represents the liquid crystal capacitance in sub-pixel portion.
The characteristic depending mainly on the size of thin film transistor (TFT) of Vgh and Vgl, owing to being limited by technique, therefore adjusts
Scope is less.Therefore can be regulated the size of Δ V by the ratio adjusting Cst3 and Cst2, Δ V is always negative, namely according to
The capacitance sharing electric capacity and the second storage electric capacity arranges the luminance difference in main pixel portion and sub-pixel portion.Number in input positive polarity
During the number of it is believed that, the brightness in sub-pixel portion 202 is less than the brightness in main pixel portion 201, when inputting the data signal of negative polarity, sub-picture
The brightness in element portion 202 is more than the brightness in main pixel portion 201, the main picture in sub-pixel portion and half owing to there being half on array base palte
Element portion, therefore can make to have clock to have the pixel of half the brightest in a frame picture, and the pixel of half is partially dark, and overall brightness is not sent out
Changing.Compared with brightness with the existing sub-pixel portion dark brightness in main pixel portion all the time, penetrance slightly promotes.
The display panels of the present invention, by sharing formed between the pixel electrode in sub-pixel portion and scan line with electricity
Hold, adjust the brightness in sub-pixel portion by sharing electric capacity, so that the brightness in main pixel portion is different from the brightness in sub-pixel portion, due to
Need not arrange extra thin film transistor (TFT) and share electric capacity, thus improve the penetrance of panel.
In sum, although the present invention is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit
The present invention processed, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, all can make various change and profit
Decorations, therefore protection scope of the present invention defines in the range of standard with claim.
Claims (10)
1. an array base palte, it is characterised in that: include data wire, scan line and handed over by described data wire and described scan line
The wrong multiple pixels formed；Described pixel includes:
Main pixel portion, has the first film transistor and the first pixel electrode；Described the first film transistor have first grid,
First source electrode, the first drain electrode, described first grid is connected with described scan line, and described first source electrode is connected with described data wire,
Described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion, has the second thin film transistor (TFT) and the second pixel electrode, described second thin film transistor (TFT) have second grid,
Second source electrode, the second drain electrode, described second grid is connected with described scan line, and described second source electrode is connected with described data wire,
Described second drain electrode is connected with described second pixel electrode, and described sub-pixel portion also includes sharing electric capacity, described in share electric capacity and be
Formed with corresponding scan line by described second pixel electrode, described in share electric capacity for the brightness to described sub-pixel portion
It is adjusted, so that the brightness in described main pixel portion is different from the brightness of described sub-pixel.
Array base palte the most according to claim 1, it is characterised in that
Described electric capacity of sharing is particular by overlap to form the first projection and the second projection section, and wherein said first projects
For the projection on the underlay substrate of described array base palte of described two pixel electrodes, described second to be projected as described pixel corresponding
Scan line projection on the underlay substrate of described array base palte.
Array base palte the most according to claim 1, it is characterised in that
Described electric capacity of sharing, for when described scan line is scanned, adjusts the pixel voltage in described sub-pixel portion, with to institute
The brightness stating sub-pixel portion is adjusted.
Array base palte the most according to claim 1, it is characterised in that
When the voltage of described data wire input positive polarity, the brightness in described main pixel portion is more than the brightness in described sub-pixel portion.
Array base palte the most according to claim 1, it is characterised in that
When the voltage of described data wire input negative polarity, the brightness in described sub-pixel portion is more than the brightness in described main pixel portion.
Array base palte the most according to claim 1, it is characterised in that
Described array base palte also includes public electrode；The first storage is formed between described first pixel electrode and described public electrode
Electric capacity, forms the second storage electric capacity between described second pixel electrode and described public electrode.
7. a display panels, it is characterised in that: include
Color membrane substrates；
Liquid crystal layer；
Array base palte, is oppositely arranged with described color membrane substrates, and described array base palte includes:
Data wire, scan line and the multiple pixels being staggered to form by described data wire and described scan line；Described pixel includes:
Main pixel portion, has the first film transistor and the first pixel electrode；Described the first film transistor have first grid,
First source electrode, the first drain electrode, described first grid is connected with described scan line, and described first source electrode is connected with described data wire,
Described first drain electrode is connected with described first pixel electrode；
Sub-pixel portion, has the second thin film transistor (TFT) and the second pixel electrode, described second thin film transistor (TFT) have second grid,
Second source electrode, the second drain electrode, described second grid is connected with described scan line, and described second source electrode is connected with described data wire,
Described second drain electrode is connected with described second pixel electrode, and described sub-pixel portion also includes sharing electric capacity, described in share electric capacity and be
Formed with corresponding scan line by described second pixel electrode, described in share electric capacity for the brightness to described sub-pixel portion
It is adjusted, so that the brightness in described main pixel portion is different from the brightness of described sub-pixel.
Display panels the most according to claim 7, it is characterised in that
Described electric capacity of sharing is particular by overlap to form the first projection and the second projection section, and wherein said first projects
For the projection on the underlay substrate of described array base palte of described two pixel electrodes, described second to be projected as described pixel corresponding
Scan line projection on the underlay substrate of described array base palte.
Display panels the most according to claim 7, it is characterised in that
Described electric capacity of sharing, for when described scan line is scanned, adjusts the pixel voltage in described sub-pixel portion, with to institute
The brightness stating sub-pixel portion is adjusted.
Display panels the most according to claim 7, it is characterised in that
When the voltage of described data wire input positive polarity, the brightness in described main pixel portion is more than the brightness in described sub-pixel portion.
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