CN106057821B - Array substrate, manufacturing method of array base plate and display device - Google Patents
Array substrate, manufacturing method of array base plate and display device Download PDFInfo
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- CN106057821B CN106057821B CN201610586457.4A CN201610586457A CN106057821B CN 106057821 B CN106057821 B CN 106057821B CN 201610586457 A CN201610586457 A CN 201610586457A CN 106057821 B CN106057821 B CN 106057821B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The invention discloses a kind of array substrate, manufacturing method of array base plate and display devices, belong to field of display technology.The array substrate includes: underlay substrate；First electrode, the first insulating layer and second electrode are disposed on the underlay substrate；It is provided on the underlay substrate of the second electrode and is provided with storage capacitance, the storage capacitance includes: the first transparency electrode being sequentially overlapped, second insulating layer and second transparency electrode, wherein, the first transparency electrode is electrically connected with the first electrode, the second transparency electrode is electrically connected with the second electrode, therefore the first transparency electrode and second transparency electrode are capable of forming transparent storage capacitance, the storage capacitance will not light transmission to pixel or light emitting region cause to block, it therefore can influence to avoid storage capacitance to pixel openings area, increase pixel aperture ratio.The present invention is for showing image.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of array substrate, manufacturing method of array base plate and display dress
It sets.
Background technique
Organic Light Emitting Diode (English: Organic Light-Emitting Diode；Referred to as: OLED) in display device
Each dot structure may include thin film transistor (TFT) (English: Thin Film Transistor；Referred to as: TFT), OLED shines
Unit and storage capacitance, wherein for TFT for driving OLED light emitting unit, storage capacitance is used to maintain the grid voltage of the TFT.
In the related technology, storage capacitance is generally collectively formed with TFT, i.e., storage capacitance a pole plate can be with TFT's
Grid is formed in same layer, the source-drain electrode and drain electrode of another pole plate and TFT are formed in same layer, and two of the storage capacitance
The material of pole plate is identical as the electrode material that TFT is used.Due to the presence of TFT leakage current, voltage meeting that storage capacitance is stored
It is gradually reduced, the grid potential of TFT is caused to change, and then influence the electric current for flowing through OLED light emitting unit and the luminous list of the OLED
The light emission luminance of member, therefore usually increase capacitor by increasing the area of two pole plates of storage capacitance, to increase voltage signal
Duration.
But since two pole plates of storage capacitance are all to increase two pole plates of storage capacitance made of opaque material
Area, aperture opening ratio (ratio of each pixel effective light transmission/light emitting region and entire area) can be reduced, influence display effect
Fruit.
Summary of the invention
In order to solve the problems, such as that storage capacitance can impact the aperture opening ratio of display device in the related technology, the present invention is mentioned
A kind of array substrate, manufacturing method of array base plate and display device are supplied.The technical solution is as follows:
In a first aspect, providing a kind of array substrate, the array substrate includes: underlay substrate；
First electrode, the first insulating layer and second electrode are disposed on the underlay substrate；
It is provided on the underlay substrate of the second electrode and is provided with storage capacitance, the storage capacitance includes: successively folded
First transparency electrode, second insulating layer and the second transparency electrode added, wherein the first transparency electrode and the first electrode
Electrical connection, the second transparency electrode are electrically connected with the second electrode.
Optionally, luminescence unit is provided on the underlay substrate；
The luminescence unit includes: lower electrode, pixel defining layer, luminescent layer and the top electrode being sequentially overlapped；
The second transparency electrode and the lower electrode are same electrode.
Optionally, orthographic projection of the pixel defining layer on the underlay substrate is with the first transparency electrode described
Orthographic projection overlapping on underlay substrate, and it is Chong Die with orthographic projection of the second transparency electrode on the underlay substrate.
Optionally, the region that the luminescence unit is provided on the underlay substrate is light emitting region, the underlay substrate
Further include: transmission region, orthographic projection of the pixel defining layer on the underlay substrate and the transmission region be not be overlapped；
Orthographic projection of the first transparency electrode on the underlay substrate is Chong Die with the transmission region；
Orthographic projection of the second transparency electrode on the underlay substrate is Chong Die with the transmission region.
Optionally, thin film transistor (TFT) is provided on the underlay substrate；
Grid in the first electrode and the thin film transistor (TFT) is formed in a patterning processes；
It is provided on the underlay substrate of the first electrode and the grid and is provided with first insulating layer；
Source-drain electrode in the second electrode and the thin film transistor (TFT) is formed in a patterning processes.
Optionally, it is provided with and is provided with multiple storage electricity being sequentially overlapped on the underlay substrate of the second electrode
Hold.
Second aspect provides a kind of manufacturing method of array base plate, which comprises
First electrode, the first insulating layer and second electrode are sequentially formed on underlay substrate；
Storage capacitance is formed on the underlay substrate for being formed with the second electrode, the storage capacitance includes: successively folded
First transparency electrode, second insulating layer and the second transparency electrode added, wherein the first transparency electrode and the first electrode
Electrical connection, the second transparency electrode are electrically connected with the second electrode.
It is optionally, described to form storage capacitance on the underlay substrate for being formed with the second electrode, comprising:
Third insulating layer is formed on the underlay substrate for being formed with the second electrode；
The first via hole is formed on the third insulating layer, the second electrode and first insulating layer；
First transparency electrode is formed on the underlay substrate for being formed with first via hole, the first transparency electrode passes through
First via hole is electrically connected with the first electrode；
Second insulating layer is formed on the underlay substrate for being formed with the first transparency electrode；
The second via hole is formed on the second insulating layer, the first transparency electrode and the third insulating layer；
Second transparency electrode is formed on the underlay substrate for being formed with second via hole, the second transparency electrode passes through
Second via hole is electrically connected with the second electrode.
Optionally, after first electrode, the first insulating layer and second electrode are sequentially formed on underlay substrate, the method
Further include:
Form luminescence unit on the underlay substrate, the luminescence unit includes: that the lower electrode being sequentially overlapped, pixel are fixed
Adopted layer, luminescent layer and top electrode；
The second transparency electrode and the lower electrode are same electrode.
Optionally, orthographic projection of the pixel defining layer on the underlay substrate is with the first transparency electrode described
Orthographic projection overlapping on underlay substrate, and it is Chong Die with orthographic projection of the second transparency electrode on the underlay substrate.
Optionally, the region that the luminescence unit is formed on the underlay substrate is light emitting region, the underlay substrate
Further include: transmission region, orthographic projection of the pixel defining layer on the underlay substrate and the transmission region be not be overlapped；
Orthographic projection of the first transparency electrode on the underlay substrate is Chong Die with the transmission region；
Orthographic projection of the second transparency electrode on the underlay substrate is Chong Die with the transmission region.
Optionally, thin film transistor (TFT) is formed on the underlay substrate；
It is described that first electrode, the first insulating layer and second electrode are sequentially formed on underlay substrate, comprising:
It is formed in the first electrode and the thin film transistor (TFT) on the underlay substrate by a patterning processes
Grid；
The first insulation is formed on the underlay substrate for the grid being formed in the first electrode and the thin film transistor (TFT)
Layer；
Formed on the underlay substrate for being formed with first insulating layer by a patterning processes second electrode and
Source-drain electrode in the thin film transistor (TFT).
It is optionally, described to form storage capacitance on the underlay substrate for being formed with the second electrode, comprising:
Multiple storage capacitances being sequentially overlapped are formed on the underlay substrate for being formed with the second electrode.
The third aspect, provides a kind of display device, and the display device includes array substrate as described in relation to the first aspect.
Technical solution provided by the invention has the benefit that
The present invention provides a kind of array substrate, manufacturing method of array base plate and display device, which includes: lining
Substrate；First electrode, the first insulating layer and second electrode are disposed on the underlay substrate；It is provided with the second electrode
Storage capacitance is provided on underlay substrate, which includes: the first transparency electrode being sequentially overlapped, second insulating layer and
Two transparent electrodes, wherein the first transparency electrode is electrically connected with the first electrode, the second transparency electrode and second electrode electricity
Connection, therefore the first transparency electrode and second transparency electrode are capable of forming transparent storage capacitance, which will not be right
The light transmission of pixel or light emitting region cause to block, thus can influence to avoid storage capacitance to pixel openings area, increase
Pixel aperture ratio.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 3 is a kind of top view of array substrate provided in an embodiment of the present invention；
Fig. 4-1 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 4-2 is the top view of array substrate shown in Fig. 4-1；
Fig. 4-3 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 4-4 is the top view of array substrate shown in Fig. 4-3；
Fig. 5 is a kind of structural schematic diagram of storage capacitance provided in an embodiment of the present invention；
Fig. 6 is a kind of flow chart of array substrate manufacturing method provided in an embodiment of the present invention；
Fig. 7 is the flow chart of another array substrate manufacturing method provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention, as shown in Figure 1, the array substrate
Include:
Underlay substrate 10 is disposed with first electrode 11, the first insulating layer 12 and second electrode 13 on the underlay substrate.
Be provided on the underlay substrate 10 of the second electrode 13 and be provided with storage capacitance 20, the storage capacitance 20 include: according to
First transparency electrode 21, second insulating layer 22 and the second transparency electrode 23 of secondary superposition, wherein the first transparency electrode 21 with should
First electrode 11 is electrically connected, which is electrically connected with the second electrode 13.
In conclusion the embodiment of the invention provides a kind of array substrate, the storage capacitance in the array substrate include according to
First transparency electrode, second insulating layer and the second transparency electrode of secondary superposition, wherein the first transparency electrode and the first electrode
Electrical connection, which is electrically connected with the second electrode, therefore the first transparency electrode and second transparency electrode can
Form transparent storage capacitance, the storage capacitance will not transmission region to pixel or light emitting region cause to block, therefore can
Influence to avoid storage capacitance to pixel openings area, increases pixel aperture ratio.
Fig. 2 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention, as shown in Fig. 2, the substrate base
Luminescence unit 30 is provided on plate 10, which includes: the lower electrode 23 being sequentially overlapped, pixel defining layer 31, luminescent layer
32 and top electrode 33, from figure 2 it can be seen that the second transparency electrode and the lower electrode are same electrode, it that is to say, formed
When storage capacitance, a pole plate of the lower electrode in the luminescence unit as the storage capacitance can use, to reduce this
The manufacturing process of storage capacitance, and can be to avoid the thickness for increasing display device.Alternatively, the second transparency electrode and the lower electricity
Pole may be independent two electrodes, and it is not limited in the embodiment of the present invention.In addition, in practical applications, this is second thoroughly
The electrode of prescribed electrode 23 and the second electrode 13 or same electrical properties.Wherein, which is the luminescence unit
Anode, this powers on the cathode of the extremely luminescence unit.
Fig. 3 is a kind of top view of array substrate provided in an embodiment of the present invention, as can be seen that should from Fig. 2 and Fig. 3
Pixel defining layer 31 on the underlay substrate orthographic projection and orthographic projection weight of the first transparency electrode 21 on the underlay substrate
It is folded and Chong Die with the orthographic projection of the second transparency electrode 23 on the underlay substrate.Wherein, overlapping may include it is completely overlapped or
Person partly overlaps.Preferably, as shown in figure 3, the orthographic projection of the pixel defining layer 31 on the underlay substrate can be located at this
One transparent electrode 21 in the orthographic projection on the underlay substrate, and be located at the second transparency electrode 23 on the underlay substrate just
In projection.Due to the pixel defining layer 31 region Chong Die with the lower electrode 23 be the light emitting region of each pixel (also referred to as
Open region), it follows that in embodiments of the present invention, in each pixel two pole plates of storage capacitance 20 with the pixel
Be open area overlapping, not only significantly increases the polar plate area of storage capacitance, and will not impact to the aperture opening ratio of pixel, thus
Effectively improve the display effect of display device.
Fig. 4-1 and Fig. 4-3 is the structural schematic diagram of other two kinds of array substrates provided in an embodiment of the present invention, and Fig. 4-2 is
The top view of array substrate shown in Fig. 4-1, Fig. 4-4 is the top view of array substrate shown in Fig. 4-3, such as Fig. 4-1 to Fig. 4-4
Shown, the region that luminescence unit 30 is formed on the underlay substrate 10 is light emitting region 30a, the underlay substrate 10 further include: thoroughly
Light region 30b, orthographic projection of the pixel defining layer 31 on underlay substrate 10 is not weighed with transmission region 30b in the luminescence unit 30
It is folded.Orthographic projection and the transparent area of the luminescent layer 32 on underlay substrate 10 with reference to Fig. 4-1 and Fig. 4-2, in the luminescence unit 30
Domain 30b is not overlapped, alternatively, the luminescent layer 32 in the luminescence unit 30 is on underlay substrate 10 as shown in Fig. 4-3 and Fig. 4-4
Orthographic projection can also be Chong Die with transmission region 30b, and it is not limited in the embodiment of the present invention.
In embodiments of the present invention, in a first aspect, for shown in Fig. 4-1 and Fig. 4-3 include transmission region array base
Plate, when top electrode 33 is transparent electrode in the luminescence unit 30, when the reflectivity of lower electrode 23 is higher, what which issued
Light can be appeared from top electrode 33, which is top light emitting-type, then refer to Fig. 4-1 and Fig. 4-2, the electricity of the storage at this time
Holding 20 can be formed in the transmission region 30b on underlay substrate 10, i.e., first transparency electrode exists in the storage capacitance 20 at this time
Orthographic projection on the underlay substrate 10 can be Chong Die with transmission region 30b, and the second transparency electrode in the storage capacitance 20
Orthographic projection on the underlay substrate 10 is also Chong Die with transmission region 30b, it is preferred that the first transparent electricity in the storage capacitance
The orthographic projection of pole and second transparency electrode on underlay substrate can be respectively positioned in the transmission region.Due to the two of the storage capacitance
A pole plate is transparent material, will not cause to block to transmission region 30b, therefore the opening of the transmission region can be improved
Rate.
Second aspect, the top electrode for array substrate shown in Fig. 2, Fig. 4-1 and Fig. 4-3, in the luminescence unit 30
33 reflectivity are higher, and when lower 23 light transmission of electrode, the light that luminescent layer 32 issues can be appeared from lower electrode 23, the luminescence unit 30
For bottom light emitting-type, the storage capacitance 20 be can be set in the light emitting region of underlay substrate at this time, due to depositing in each pixel
Two pole plates that storage holds 20 are transparent material, therefore the light that storage capacitance will not issue the luminescence unit 30 causes to hide
Gear, therefore the aperture opening ratio in pixel light emission region can be improved.
The third aspect, the lower electrode for array substrate shown in Fig. 2, Fig. 4-1 and Fig. 4-3, in the luminescence unit 30
23 be transparent electrode, and top electrode 33 is semi-transflective reflective electrode or lower electrode 23 is semi-transflective reflective electrode, and top electrode 33 is
When transparent electrode, transparence display is may be implemented in the display device which forms, and the storage capacitance 20 can be set at this time
It in the light emitting region of underlay substrate, also can be set in the transmission region of the underlay substrate, due to depositing in each pixel
Two pole plates that storage holds 20 are transparent material, thus will not light emitting region to underlay substrate or transmission region cause
It influences, therefore the aperture opening ratio of pixel light emission region or transmission region can be improved.
Optionally, as shown in Figures 2 and 3, it is provided with thin film transistor (TFT) 40 on the underlay substrate 10,11 He of first electrode
Grid 41 in the thin film transistor (TFT) 40 is formed in a patterning processes, and the material of the first electrode 11 and the grid 41
Matter is identical.It can also be seen that the grid 41 is electrically connected with controlling grid scan line 01 from Fig. 3.The first transparency electrode 21 passes through the
One via hole 21a is connect with the first electrode 11.
With reference to Fig. 2, it is provided on the underlay substrate 10 of the first electrode 11 and the grid 41 and is provided with first insulating layer
12, since first insulating layer 12 is set between grid 41 and active layer 43, which also has grid exhausted
The effect of edge layer.
Referring to figs. 2 and 3, the source-drain electrode 42 in the second electrode 13 and the thin film transistor (TFT) 40 is in a patterning processes
Middle formation, and the second electrode 13 is identical as the material of the source-drain electrode 42.From Fig. 3 it can also be seen that the source-drain electrode 42 with
Data line 02 is electrically connected.The second transparency electrode 23 is connect by the second via hole 23a with the second electrode 13.And the first electrode
11 and orthographic projection of the second electrode 13 on underlay substrate and the orthographic projection of the pixel defining layer 31 on the underlay substrate not
Overlapping, therefore can influence to avoid the first electrode made of transparent materials and second electrode to pixel openings area.
Further, since the first transparency electrode 21 and second transparency electrode 23 can respectively by via hole and first electrode and
Second electrode electrical connection, therefore when forming the storage capacitance on underlay substrate, it can only in the open region of each pixel and tie up
Determine area (i.e. the area bonding) and form the first transparency electrode and second transparency electrode, without being formed for two transparent electrodes
Long range cabling not only increases so as to the parasitic capacitance influence caused by data signal transmission for avoiding cabling from generating
The polar plate area of storage capacitance also ensures the display effect of display device.
It should be noted that in practical applications, in the second insulating layer 22 formed in the storage capacitance 20, can make
The second insulating layer 22 thinner thickness, and the second insulating layer is formed using the material of higher dielectric coefficient, for example, can be with
Use silica SiO2 (dielectric coefficient 3.9), silicon nitride Si3N4 (dielectric coefficient 7), aluminium oxide Al 2O3 (dielectric coefficient
For 9), yttria Y2O3 (dielectric coefficient 15), lanthana La2O3 (dielectric coefficient 30), tantalum pentoxide Ta2O5
(dielectric coefficient 26), titanium dioxide TiO2 (dielectric coefficient 80), hafnium oxide HfO2 (dielectric coefficient 25) or zirconium dioxide
The materials such as ZrO2 (dielectric coefficient 25) form the second insulating layer, to further increase the capacitor of the storage capacitance.
It should also be noted that, source-drain electrode described in the embodiment of the present invention is finger source electrode or drain electrode, in Fig. 3 with data line 02
Electrical connection is source electrode in thin film transistor (TFT), and being electrically connected with public electrode wire 03 is drain electrode in thin film transistor (TFT).
Further, in embodiments of the present invention, be provided on the underlay substrate 10 of the second electrode can be set it is more
A storage capacitance 20 being sequentially overlapped.As shown in figure 5, wherein each storage capacitance by two pole plates and two pole plates it
Between insulating layer composition, and a pole plate in two pole plates is electrically connected with first electrode, another pole plate and second electrode
Electrical connection, can form storage capacitance.In addition, the storage capacitance in multiple storage capacitance being sequentially overlapped, positioned at the top
The second transparency electrode of (storage capacitance i.e. farthest apart from underlay substrate) and the lower electrode of luminescence unit are same electrode.
In conclusion the embodiment of the invention provides a kind of array substrate, the storage capacitance in the array substrate include according to
First transparency electrode, second insulating layer and the second transparency electrode of secondary superposition, wherein the first transparency electrode and the first electrode
Electrical connection, which is electrically connected with the second electrode, therefore the first transparency electrode and second transparency electrode can
Form transparent storage capacitance, the storage capacitance will not transmission region to pixel or light emitting region cause to block, therefore can
Influence to avoid storage capacitance to pixel openings area, and two pole plates of the storage capacitance can be with pixel openings area weight
It is folded, therefore effectively increase the polar plate area of storage capacitance and the aperture opening ratio of pixel.
Fig. 6 is a kind of flow chart of manufacturing method of array base plate provided in an embodiment of the present invention, and with reference to Fig. 6, this method can
To include:
Step 501 sequentially forms first electrode, the first insulating layer and second electrode on underlay substrate.
Step 502 forms storage capacitance on the underlay substrate for be formed with the second electrode, the storage capacitance include: according to
First transparency electrode, second insulating layer and the second transparency electrode of secondary superposition, wherein the first transparency electrode and the first electrode
Electrical connection, the second transparency electrode are electrically connected with the second electrode.
In conclusion the storage electricity the embodiment of the invention provides a kind of manufacturing method of array base plate, in the array substrate
Appearance is formed using transparent electrode, thus will not transmission region to pixel or light emitting region cause to block, therefore can be to avoid
Influence of the storage capacitance to pixel openings area, increases pixel aperture ratio.
Fig. 7 is the flow chart of another manufacturing method of array base plate provided in an embodiment of the present invention, with reference to Fig. 7, this method
May include:
Step 601 is formed in the first electrode and the thin film transistor (TFT) on the underlay substrate by a patterning processes
Grid.
As shown in Fig. 2, forming first electrode 11 and grid 41 on underlay substrate 10 by a patterning processes, reach
Reduce the effect of array substrate manufacturing process.
Step 602 forms first on the underlay substrate for the grid being formed in the first electrode and the thin film transistor (TFT)
Insulating layer.
With reference to Fig. 2, since first insulating layer 12 is formed between grid 41 and source-drain electrode 42, also there is gate insulation
The effect of layer.
Step 603 forms second electricity by a patterning processes on the underlay substrate for being formed with first insulating layer
Source-drain electrode in pole and the thin film transistor (TFT).
As shown in Fig. 2, forming second electrode 12 and source-drain electrode 42 on underlay substrate 10 by a patterning processes, reach
Reduce the effect of array substrate manufacturing process.
Step 604 forms third insulating layer on the underlay substrate for be formed with the second electrode.
It is exemplary, as shown in Fig. 2, third insulating layer 14 can be formed on the underlay substrate for being formed with second electrode 13.
It should be noted that in practical applications, with reference to Fig. 2 and Fig. 3, since the first transparency electrode 21 is on the underlay substrate
Orthographic projection and the orthographic projection of the second electrode 13 on underlay substrate be not be overlapped, accordingly it is also possible to directly in the second electrode 13
Upper formation first transparency electrode 21, that is, not necessarily form third insulating layer 14.
Step 605 forms the first via hole on the third insulating layer, the second electrode and first insulating layer.
Step 606 forms first transparency electrode on the underlay substrate for being formed with first via hole, the first transparency electrode
It is electrically connected by first via hole with the first electrode.
Referring to figs. 2 and 3, which is electrically connected by the first via hole 21a with first electrode 11.
Step 607 forms second insulating layer on the underlay substrate for be formed with the first transparency electrode.
Step 608 forms the second via hole on the second insulating layer, the first transparency electrode and the third insulating layer.
Step 609 forms luminescence unit on the underlay substrate for being formed with second via hole, the luminescence unit include: according to
Lower electrode, pixel defining layer, luminescent layer and the top electrode of secondary superposition.
As shown in Fig. 2, the second transparency electrode and the lower electrode are same electrode 23.Referring to figs. 2 and 3, this second thoroughly
Prescribed electrode (descending electrode) 23 is electrically connected by the second via hole 23a with second electrode 13.
Optionally, as shown in Figures 2 and 3, orthographic projection of the pixel defining layer 31 on the underlay substrate 10 and this first
Orthographic projection overlapping of the transparent electrode 21 on the underlay substrate 10, and with the second transparency electrode 23 on the underlay substrate 10
Orthographic projection overlapping.
Optionally, as shown in Fig. 4-1 to Fig. 4-4, the region of the luminescence unit 30 is formed on the underlay substrate 10 as hair
Light region 30a, the underlay substrate 10 further include: transmission region 30b；
Orthographic projection of the first transparency electrode on the underlay substrate 10 is Chong Die with transmission region 30b；This is second transparent
Orthographic projection of the electrode on the underlay substrate 10 is Chong Die with transmission region 30b.
Optionally, storage capacitance is formed on the underlay substrate for be formed with the second electrode, comprising:
Multiple storage capacitances being sequentially overlapped are formed on the underlay substrate for be formed with the second electrode.
It should be noted that a patterning processes described in above-described embodiment may include photoresist coating, exposure, show
The techniques such as shadow, etching, photoresist lift off.
It should be noted manufacturing method of array base plate provided in an embodiment of the present invention, can be used for manufacturing such as Fig. 1 extremely
Array substrate shown in Fig. 5 is any.
In conclusion the storage electricity the embodiment of the invention provides a kind of manufacturing method of array base plate, in the array substrate
Hold includes the first transparency electrode, second insulating layer and the second transparency electrode that are sequentially overlapped, wherein the first transparency electrode with should
First electrode electrical connection, which is electrically connected with the second electrode, therefore the first transparency electrode and second transparent
Electrode is capable of forming transparent storage capacitance, the storage capacitance will not transmission region to pixel or light emitting region cause to hide
Gear, thus can influence to avoid storage capacitance to pixel openings area, and two pole plates of the storage capacitance can be with pixel
Be open area overlapping, therefore effectively increases the polar plate area of storage capacitance and the aperture opening ratio of pixel.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Underlay substrate；
First electrode, the first insulating layer and second electrode are disposed on the underlay substrate；
It is provided on the underlay substrate of the second electrode and is provided with multiple storage capacitances being sequentially overlapped, each storage electricity
Appearance includes: the first transparency electrode, second insulating layer and second transparency electrode being sequentially overlapped, wherein the first transparency electrode
It is electrically connected with the first electrode, the second transparency electrode is electrically connected with the second electrode；
Luminescence unit is provided on the underlay substrate；
The luminescence unit includes: lower electrode, pixel defining layer, luminescent layer and the top electrode being sequentially overlapped；
Second transparency electrode and the lower electricity in the multiple storage capacitance being sequentially overlapped, positioned at the storage capacitance of the top
Extremely same electrode；
The region that the luminescence unit is provided on the underlay substrate is light emitting region, the underlay substrate further include: light transmission
Region, orthographic projection of the pixel defining layer on the underlay substrate and the transmission region be not be overlapped；
Orthographic projection of the first transparency electrode on the underlay substrate, respectively with the transmission region and the light emitting region
Overlapping；
Orthographic projection of the second transparency electrode on the underlay substrate, respectively with the transmission region and the light emitting region
Overlapping；
Also, the first transparency electrode and the second transparency electrode, open region and binding positioned at the array substrate
Area.
2. array substrate according to claim 1, which is characterized in that
The pixel defining layer on the underlay substrate orthographic projection and the first transparency electrode on the underlay substrate
Orthographic projection overlapping, and it is Chong Die with orthographic projection of the second transparency electrode on the underlay substrate.
3. array substrate according to claim 1 or 2, which is characterized in that be provided with film crystal on the underlay substrate
Pipe；
Grid in the first electrode and the thin film transistor (TFT) is formed in a patterning processes；
It is provided on the underlay substrate of the first electrode and the grid and is provided with first insulating layer；
Source-drain electrode in the second electrode and the thin film transistor (TFT) is formed in a patterning processes.
4. a kind of manufacturing method of array base plate, which is characterized in that the described method includes:
First electrode, the first insulating layer and second electrode are sequentially formed on underlay substrate；
Multiple storage capacitances being sequentially overlapped, each storage electricity are formed on the underlay substrate for being formed with the second electrode
Appearance includes: the first transparency electrode, second insulating layer and second transparency electrode being sequentially overlapped, wherein the first transparency electrode
It is electrically connected with the first electrode, the second transparency electrode is electrically connected with the second electrode；
After sequentially forming first electrode, the first insulating layer and second electrode on underlay substrate, the method also includes:
Luminescence unit is formed on the underlay substrate, the luminescence unit includes: lower electrode, the pixel definition being sequentially overlapped
Layer, luminescent layer and top electrode；
Second transparency electrode and the lower electricity in the multiple storage capacitance being sequentially overlapped, positioned at the storage capacitance of the top
Extremely same electrode；
The region that the luminescence unit is formed on the underlay substrate is light emitting region, the underlay substrate further include: light transmission
Region, orthographic projection of the pixel defining layer on the underlay substrate and the transmission region be not be overlapped；
Orthographic projection of the first transparency electrode on the underlay substrate, respectively with the transmission region and the light emitting region
Overlapping；
Orthographic projection of the second transparency electrode on the underlay substrate, respectively with the transmission region and the light emitting region
Overlapping；
Also, the first transparency electrode and the second transparency electrode, open region and binding positioned at the array substrate
Area.
5. according to the method described in claim 4, it is characterized in that, described on the underlay substrate for being formed with the second electrode
Form storage capacitance, comprising:
Third insulating layer is formed on the underlay substrate for being formed with the second electrode；
The first via hole is formed on the third insulating layer, the second electrode and first insulating layer；
First transparency electrode is formed on the underlay substrate for being formed with first via hole, the first transparency electrode passes through described
First via hole is electrically connected with the first electrode；
Second insulating layer is formed on the underlay substrate for being formed with the first transparency electrode；
The second via hole is formed on the second insulating layer, the first transparency electrode and the third insulating layer；
Second transparency electrode is formed on the underlay substrate for being formed with second via hole, the second transparency electrode passes through described
Second via hole is electrically connected with the second electrode.
6. according to the method described in claim 4, it is characterized in that,
The pixel defining layer on the underlay substrate orthographic projection and the first transparency electrode on the underlay substrate
Orthographic projection overlapping, and it is Chong Die with orthographic projection of the second transparency electrode on the underlay substrate.
7. according to any method of claim 4 to 6, which is characterized in that be formed with film crystal on the underlay substrate
Pipe；
It is described that first electrode, the first insulating layer and second electrode are sequentially formed on underlay substrate, comprising:
The grid in the first electrode and the thin film transistor (TFT) is formed on the underlay substrate by a patterning processes；
First insulation is formed on the underlay substrate for the grid being formed in the first electrode and the thin film transistor (TFT)
Layer；
The second electrode and described is formed on the underlay substrate for being formed with first insulating layer by a patterning processes
Source-drain electrode in thin film transistor (TFT).
8. a kind of display device, which is characterized in that the display device includes any array substrate of claims 1 to 3.
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| CN107195662A (en) * | 2017-06-08 | 2017-09-22 | 京东方科技集团股份有限公司 | Display panel and preparation method thereof, display device and display methods |
| CN108428730B (en) * | 2018-05-16 | 2021-01-26 | 京东方科技集团股份有限公司 | OLED display substrate, manufacturing method thereof and display device |
| CN108764081B (en) * | 2018-05-17 | 2021-03-16 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| US11195863B2 (en) * | 2018-09-21 | 2021-12-07 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel having a storage capacitor, manufacturing method the same thereof and display module having the same |
| CN109659342B (en) * | 2018-12-13 | 2021-01-15 | 武汉华星光电半导体显示技术有限公司 | Flexible and foldable OLED display device |
| CN110767107B (en) | 2018-12-28 | 2023-03-24 | 昆山国显光电有限公司 | Display device, display panel thereof and OLED array substrate |
| CN109742113B (en) | 2019-01-08 | 2020-12-25 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and related device |
| CN110728919B (en) * | 2019-10-25 | 2022-04-08 | 京东方科技集团股份有限公司 | Transparent display panel, manufacturing method thereof and display device |
| CN110867474B (en) * | 2019-11-26 | 2022-01-25 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel |
| CN110943116A (en) * | 2019-12-19 | 2020-03-31 | 武汉天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
| CN112259595B (en) * | 2020-10-30 | 2022-10-11 | 武汉天马微电子有限公司 | Array substrate and display panel |
| WO2023283768A1 (en) * | 2021-07-12 | 2023-01-19 | 京东方科技集团股份有限公司 | Display substrate and preparation method therefor, and display device |
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