CN106028049A - Two-dimensional DCT image processor - Google Patents

Abstract

The invention belongs to the ethical field of an integrated circuit, and specifically relates to a two-dimensional DCT image processor. The image processor provided by the invention comprises a data selection module, a state control module, a one-dimensional DCT module and a shifting register array. The data input end of the data selection module is connected with the output end of the shifting register array. The control signal input end of the data selection module is connected with the output end of the state control module. The output end of the data selection module is connected with the data input end of the one-dimensional DCT module. The output end of the state control module is connected with the control signal input end of the shifting register array and the control signal input end of the data selection module. The data input end of the one-dimensional DCT module is connected with the output end of the data selection module. The control signal input end of the one-dimensional DCT module is connected with external control signals. The output end of the one-dimensional DCT module is connected with the data input end of the shifting register array and is the data output end of the whole image processor. The image processor has the advantages that the working modes of the two-dimensional DCT image processor can be adjusted according to the precision demands of different occasions; and therefore, the image processor has lower energy consumption.

Description

A kind of two-dimensional dct image processor

Technical field

The invention belongs to technical field of integrated circuits, particularly to the low energy consumption two-dimensional dct image processor of a kind of variable precision.

Background technology

Discrete cosine transform (DCT) is in the very popular a kind of technology of digital processing field, possesses good orthogonal property, Stalling characteristic, decorrelation characteristic and energy compaction property, be the core algorithm of compression of images.Image information becomes through two-dimensional dct After changing, the energy of the overwhelming majority concentrates on DC component and minority low frequency component, decreases spatial redundancy. JPEG (JointPhotographic Experts Group, JPEG), MPEG (MovingPicture Expert Group, Motion Picture Experts Group), H.263 etc. standard all have employed the DCT technology major programme as compressed encoding.

Two-dimensional dct circuit can use separation method of row and column to be decomposed into the combination of two one-dimensional DCT circuit, goes calculating respectively And column count, so the core of two-dimensional dct image processor is its one-dimensional DCT circuit in inside.In traditional images processor One-dimensional DCT circuit is made up of 22 multipliers and 30 adders, due to for multiplier relatively adder area and power consumption all than Bigger so that area and the power consumption of the conventional two-dimensional DCT image processor that number of multipliers is on the high side are the biggest.

In different occasions, the requirement to picture quality is the most different, needs image processor can regulate picture matter dynamically Amount is to adapt to different required precisions.Traditional two-dimensional dct image processor can only provide the image procossing of a kind of precision, uses The image procossing scheme of low precision is unsatisfactory for system requirements, uses high-precision image procossing scheme can cause the waste of energy.

For traditional images processor, the improvements of the present invention are that, decrease the usage quantity of multiplier, from And decreasing area and the power consumption of image processor, the design of adjustable accuracy simultaneously makes this two-dimensional dct image processor to fit Answer different scene demands, have lower energy consumption.

Summary of the invention

To be solved by this invention, it is simply that the problem existed for above-mentioned conventional two-dimensional DCT image processor, propose a kind of variable The low energy consumption two-dimensional dct image processor of precision.

For achieving the above object, the present invention adopts the following technical scheme that

The low energy consumption two-dimensional dct image processor of a kind of variable precision, have employed collapsible framework, and one has four kinds of mode of operations, Being respectively pattern 4, pattern 3, pattern 2 and pattern 1, precision and energy consumption are gradually lowered to pattern 1 from pattern 4；At this image Reason device includes data selecting module, status control module, one-dimensional DCT module, and shift register array, the most one-dimensional DCT Module includes the fixing bit wide multiplier of variable precision, adder, subtractor, threshold value judgment module and pipeline register；Institute The data input pin stating data selecting module connects the outfan of outer input data and shift register array, control signal input Connecing the outfan of status control module, the output of data selecting module terminates the data input pin of one-dimensional DCT module；Described state The control signal input termination external control signal of control module, the control signal input of its output termination shift register array Control signal input with data selecting module；The data input pin of described one-dimensional DCT module connects the output of data selecting module End, control signal input termination external control signal, the data input of the output termination shift register array of one-dimensional DCT module End, and be also the data output end of whole image processor；

Described status control module is made up of a finite state machine, and state is respectively original state, row calculating state and column count State, and carry out state switching according to external control signal and internal data change；The control signal that this module is exported determines The source that enters data to of one-dimensional DCT module and the moving direction of shift register array；

Described data selecting module determines to be input to the data of one-dimensional DCT module according to control signal, during row calculating state, controls Signal behavior outer input data enters one-dimensional DCT module, and during column count state, control signal selects shift register array defeated The data going out end enter one-dimensional DCT module；

Described one-dimensional DCT module comprises the fixing bit wide multiplier of variable precision, adder, subtractor, threshold value judgment module and Pipeline register, reduces the complexity of hardware by the approximation multiplexing of multiplier results, and fixed bit width multiplier is individual the most at last Number is reduced to 8；In the design, the fixing bit wide multiplier of variable precision has two kinds of computation schemas, respectively high precision computation mould Formula and low accuracy computation pattern, this image processor uses high precision computation pattern, pattern 2 and mould when pattern 4 and pattern 3 Low accuracy computation pattern is used during formula 1；Outer input data inputs into threshold value judgment module after first order addition and subtraction, Described threshold value judgment module only just can send into stream more than threshold value according to current operation mode decision threshold size, the data of input Pipeline register, is input into fixing bit wide multiplier at next clock and continues to calculate；The result of fixing bit wide multiplier through one is Obtaining final result of calculation after row addition and subtraction, different working modes calculative DCT coefficient number also differs, The coefficient number that the mode of operation that precision is high calculates is the most, and the adder of consuming is the most, and the mode of operation that precision is low calculates Coefficient number fewer, the adder of consuming is the most relatively fewer；

Described shift register array is made up of 64 12 bit registers, and every 8 is a row, constitutes 8 and takes advantage of the matrix array of 8； Opening, according to current operation mode, the depositor needing to use and carry out shifting function, the precision of mode of operation is the highest, one-dimensional DCT The DCT coefficient that module calculates is the most, and the depositor needing displacement is the most；During row calculating state, shift register array Storing the results of intermediate calculations of one-dimensional DCT module output line by line, the data that signal controls in shift register array move down directly Shift register array all it is stored in all of intermediate object program；During column count state, shift register array is by after transposition Between result of calculation export one-dimensional DCT module by column, signal controls the data in shift register array and is moved to the left until all Intermediate object program all out of shift register array；

Beneficial effects of the present invention is, is reduced hardware complexity and the power consumption of image processor by the approximation multiplexing of multiplier results； Can be according to the mode of operation of the accuracy requirement regulation two-dimensional dct image processor of different occasions so that it is have lower energy consumption；

Accompanying drawing explanation

Fig. 1 is the two-dimensional dct image processor structural representation proposed in the present invention；

Fig. 2 is the state transfer schematic diagram of status control module；

Fig. 3 is data selecting module structural representation；

Fig. 4 is one-dimensional DCT modular structure schematic diagram；

Fig. 5 is shift register array structural representation；

Fig. 6 is conventional shift register logical circuit diagram；

Fig. 7 is pattern shift register concerned logical circuitry.

Detailed description of the invention

Below in conjunction with the accompanying drawings the present invention is described in detail

The present invention provides the low energy consumption two-dimensional dct image processor of a kind of variable precision, and the approximation first passing through multiplier results is multiple With reducing its hardware complexity and power consumption；Then by the control of operational precision and operation times is regulated its precision and energy consumption, Make it switch suitable mode of operation in the face of different application scenarios, reach to reduce the purpose of energy consumption.

As it is shown in figure 1, this two-dimensional dct image processor is by data selecting module, status control module, one-dimensional DCT module With these four module compositions of shift register array, 64 view data of each calculation process.First mode control signal is by this figure As processor is configured to the mode of operation specified, then external control signal by the finite state machine in status control module by initially State is switched to row calculating state, and exports corresponding control signal.Data selecting module starts each clock and receives 88 Outer input data, be to input into one-dimensional DCT module after 12 bit data by these Data expansion, so continue 8 clocks Until 64 view data all input into data selecting module.One-dimensional DCT module each clock cycle calculates 8 12 bitmaps Picture data, and obtain the results of intermediate calculations of 8 12, these results are inputted and stores into shift register array.Move The intermediate object program that one-dimensional DCT module arithmetic obtains is moved down according to control signal and stores, directly by bit register array line by line To storing 8 whole row result of calculations.Now status control module according to the change of internal control data by state by going calculating State switches to column count state, and exports corresponding control signal.Shift register array starts each clock cycle by 8 Intermediate object program after transposition inputs into data selecting module, so continues 8 clock cycle until all of results of intermediate calculations all Being input to data selecting module, the intermediate object program after transposition is entered directly into one-dimensional according to control signal by data selecting module DCT module calculates.One-dimensional DCT module each clock cycle calculates the result that the row of 8 12 calculates, and obtains 8 The column count result of individual 12, as finally exporting data, obtains the view data after whole 64 compressions after 8 clock cycle.

Fig. 2 is the state transfer schematic diagram of status control module, is made up of three states altogether, is original state respectively, row meter Calculation state and column count state.Start is system commencing signal, and start is that 1 interval scale system can start to calculate, this Time state machine jumped to row calculating state by original state.Enable_row [7] is the row of shift register array the 8th row depositor Displacement storage enables signal, and it is that whole results that 1 epoch table row calculates have been stored in register array, it is not necessary to appoint again What displacement storage operation, state can be calculated state transition to column count state by row.Enable_column [7] is shift register battle array Arrange the 7th row row displacement storage enable signal, it be 0 epoch table row calculate whole intermediate object programs have moved out depositor battle array Row, now 64 view data are the most all disposed, and state to original state, is started next group by column count state transition The process of view data.

The structural representation of data processing module is as it is shown on figure 3, be mainly made up of multiplexer, and input is respectively outside defeated The view data entered and the results of intermediate calculations of one-dimensional DCT module, wherein outer input data is 8 bit image data, need into Row sign bit extends, and inputs again and calculate into one-dimensional DCT module after becoming 12 bit data.Data select signal is from state Control module, when row calculating state, multiplexer selects the view data of outside input, when column count state, multichannel Multiplexer selects the results of intermediate calculations of one-dimensional DCT module.

Two-dimensional dct transform is defined as follows:

$C(u,v)=\mathrm{\α}\left(u\right)\mathrm{\α}\left(v\right)\underset{x=0}{\overset{7}{\Σ}}\underset{y=0}{\overset{7}{\Σ}}f(x,y)cos\[\frac{\mathrm{\π}(2x+1)u}{16}\]cos\[\frac{\mathrm{\π}(2x+1)v}{16}\]$

Wherein (x, y) is the view data before compressing to f, and (u, is v) DCT coefficient after compressing to C, and α (u) is the function about u, expression formula As follows:

$\mathrm{\α}\left(u\right)=\left\{\begin{array}{ccc}\frac{\sqrt{2}}{4}& for& u=0\\ \frac{1}{2}& for& u\≠0\end{array}\right.$

Two-dimensional dct transform has stalling characteristic, can be decomposed into the combination of two continuous one-dimensional dct transforms, one-dimensional dct transform It is defined as follows:

$C\left(u\right)=\mathrm{\α}\left(u\right)\underset{x=0}{\overset{7}{\Σ}}f\left(x\right)cos\[\frac{\mathrm{\π}(2x+1)u}{16}\]$

Traditional one-dimensional DCT can be to be expressed as the form of matrix calculus:

$\left[\begin{array}{c}{W}_0\\ W_2\\ W_4\\ W_6\end{array}\right]=\left[\begin{array}{cccc}d& d& d& d\\ b& f& -f& -b\\ d& -d& -d& d\\ f& -b& b& -f\end{array}\right]\left[\begin{array}{c}{x}_0+x_7\\ x_1+x_6\\ x_2+x_5\\ x_3+x_4\end{array}\right]$

$\left[\begin{array}{c}{W}_1\\ W_3\\ W_5\\ W_7\end{array}\right]=\left[\begin{array}{cccc}a& c& e& g\\ c& -g& -a& -e\\ e& -a& g& c\\ g& -e& c& -a\end{array}\right]\left[\begin{array}{c}{x}_0-x_7\\ x_1-x_6\\ x_2-x_5\\ x_3-x_4\end{array}\right]$

Wherein x₀-x₇It is input data, W₀-W₇It is calculated DCT coefficient, a=cos (π/16), b=cos (2 π/16), c=cos (3 π/ 16), d=cos (4 π/16), e=cos (5 π/16), f=cos (6 π/16), g=cos (7 π/16).Calculate according to above-mentioned matrix Need to use 22 full precision multipliers and 30 adders, owing to for multiplier relatively adder, area and power consumption are the biggest, It is the most undesirable that this directly results in the performance in terms of power consumption and area of traditional one-dimensional DCT circuit, also directly affects conventional two-dimensional The performance of DCT image processor.Multiplier is reduced to 8 by the method that present invention introduces approximate calculation, and concrete grammar is as follows: It can be seen that either calculate even coefficient still calculate strange coefficient from matrix multiplication, it is all to be multiplied by the right with different constants Column matrix, it is possible to utilize one of them constant to be multiplied by the result of column matrix and represent the computing of remaining constant by the way of displacement As a result, reach to save the purpose of multiplier.By analogue simulation and error analysis, finally determine that even coefficient is multiplied by row by constant d The result of matrix represents:

b≈d+d/4

f≈d/2

W₀=d₁+d₂+d₃+d₄

W₂=d₁+d₁/4+d₂/2-d₃/2-d₄-d₄/4

W₄=d₁-d₂-d₃+d₄

W₆=d₁/2-d₂-d₂/4+d₃+d₃/4-d₄/2

Wherein d₁,d₂,d₃,d₄It is respectively constant d and is multiplied by right-hand column matrix the first row, the second row, the third line and the result of fourth line.Strange system The result that number is multiplied by column matrix by constant c represents:

a≈c+c/4

e≈c/2+c/8

g≈c/4

W₁=c₁+c₁/4+c₂+c₃/2+c₃/8+c₄/4

W₃=c₁-c₂/4-c₃-c₃/4-c₄/2-c₄/8

W₅=c₁/2+c₁/8-c₂-c₂/4+c₃/4+c₄

W₇=c₁/4-c₂/2-c₂/8+c₃-c₄-c₄/4

Wherein c₁,c₂,c₃,c₄It is respectively constant c and is multiplied by right-hand column matrix the first row, the second row, the third line and the result of fourth line.From W₀-W₇Expression formula it can be seen that the one-dimensional DCT circuit of the present invention has only to 8 multipliers to calculate d₀-d₄And c₀-c₄, And expression formula has a lot of identical subexpressions, these subexpressions can be shared the when of hardware designs, subtract further The use of few adder, reduces area and the power consumption of circuit.

As shown in Figure 4, one-dimensional DCT module comprises the fixing bit wide multiplier of variable precision, adder, and subtractor, threshold value is sentenced Disconnected module and streamline are deposited.First input carries out addition and subtraction, the addition in the most above-mentioned column matrix and subtraction behaviour Make, then result of calculation is input to threshold value judgment module.Mode control signal determines current operation mode, threshold value judgment module According to the size of current operation mode decision threshold, screen out incongruent input data, reduce rear stage and fix bit wide multiplier Operation times, reduces the purpose of system energy consumption.The pattern that precision is higher chooses relatively small threshold value, is ensureing the same of precision Time reduce operation times by a small margin, the relatively low pattern of precision chooses relatively large threshold value, in the range of precision acceptable significantly Degree reduces operation times.Through Multi simulation running simulation and error analysis, finally determine that the threshold value of pattern 4 is set to 2, namely Just can enter fixing bit wide multiplier when input is more than 2 to calculate, otherwise not calculate and directly multiplication result be set to 0, The threshold value of pattern 3 is 3 simultaneously, and the threshold value of pattern 2 is 4, and the threshold value of pattern 1 is 10.In input data not by threshold value mould During block, in order to reduce circuit upset, add one-level depositor and keep original data of fixing bit wide multiplier, namely scheme Pipeline register in 4.Introduce pipeline register and can also shorten the critical path of this image processor, increase work frequency Rate.

In figure, the fixing bit wide multiplier of variable precision has two kinds of computation schemas, respectively high precision computation pattern and low accuracy computation Pattern, is determined the computation schema of fixing bit wide multiplier by the mode of operation of image processor.Pattern 4 He that precision is of a relatively high Pattern 3 uses high precision computation pattern, and pattern 2 and pattern 1 that precision is relatively low use low accuracy computation pattern, thus reach To the purpose reducing operational precision minimizing system energy consumption.Afterbody is the pure combinational logic circuit including adder and subtractor, By the operation result of fixing bit wide multiplier through a series of additions and subtraction, obtain final DCT coefficient.Because W₀-W₇ Arithmetic expression in have the most identical subexpression, so this partial circuit have employed common subexpression eliminate method, from calculation Method aspect reduces operand, reduces the complexity of circuit.In order to reduce the energy consumption of system further, the precision of system work reduces Time calculative DCT coefficient reduced, need the adder of work and subtractor to reduce the most accordingly.DCT coefficient Importance is from W₀To W₇Gradually weaken, so first the coefficient reduced should be W₇, next to that W₆, the rest may be inferred.Work Pattern 4 precision is the highest, needs to calculate whole DCT coefficient, and pattern 3 calculates W₀-W₆, pattern 2 calculates W₀-W₅, precision Worst pattern is abandoned calculating three DCT coefficient, namely calculates W₀-W₄。

What Fig. 5 showed is shift register array structural representation, and as can be seen from the figure this array is by 64 12 bit registers Composition, every 8 is a row, constitutes 8 and takes advantage of the matrix array of 8.During row calculating state, shift register array stores one line by line The results of intermediate calculations of dimension DCT module output, signal control the data in shift register array be moved downwardly until all of in Between result be all stored in shift register array.During column count state, shift register array is by the results of intermediate calculations after transposition Output is to one-dimensional DCT module by column, and signal controls the data in shift register array and is moved to the left until all of intermediate object program All out of shift register array.Having two kinds of shift register in register array, one is by mode signal control Pattern shift register concerned, another is the conventional shift depositor not controlled by mode signal.Fig. 6 is conventional shift Register logical circuit diagram, this depositor can receive data from depositor above, it is also possible to the depositor from the left side receives number According to, select with a multiplexer, select signal to be provided by status control module.It also has two to enable signal, point Not Kong Zhi row calculating state time displacement storage and the storage of displacement during column count state, be also to be provided by status control module.Figure 7 is the pattern shift register concerned logical circuitry controlled by mode signal, integrated circuit structure and conventional shift depositor class Seemingly, only difference is that mode signal many and controlled opening and closing of depositor.In array Far Left three be classified as pattern be correlated with Shift register, stores W respectively₇, W₆, W₅These three DCT coefficient, remaining 5 row is all conventional shift depositor.When this When the image processor of invention is operated in pattern 3, design factor W can be abandoned₇, now mode signal may turn off Far Left this The model specific registers of row, to save energy consumption, closes the left side two column register when being operated in pattern 2, closes the left side during pattern 1 Three column registers.

Comparing traditional image processor, the low energy consumption two-dimensional dct image processor of the variable precision that the present invention proposes can basis The mode of operation of the accuracy requirement regulation of different occasions oneself, has lower energy consumption while meeting system requirements.This image Processor is when mode of operation 4 is switched to pattern 3, and the PSNR of picture reduces 2.8dB, and energy consumption reduces by 17.4%；From Working mould When formula 3 is switched to pattern 2, the PSNR of picture reduces 2.6dB, and energy consumption reduces by 21.4%；It is switched to pattern from mode of operation 2 When 1, the PSNR of picture reduces 2.9dB, and energy consumption reduces by 26.3%.

Claims (1)

1. a two-dimensional dct image processor, this image processor includes data selecting module, status control module, one-dimensional DCT module and shift register array；The data input pin of described data selecting module connects outer input data and shift register The outfan of array, the outfan of control signal input termination status control module, the output termination of control signal input is one-dimensional The data input pin of DCT module；The control signal input termination external control signal of described status control module, it exports termination The control signal input of shift register array and the control signal input of data selecting module；Described one-dimensional DCT module Data input pin connects the outfan of data selecting module, the control signal input termination external control signal of one-dimensional DCT module, and one The data input pin of the output termination shift register array of dimension DCT module, and be also the data output of whole image processor End；

Described status control module is made up of a finite state machine, and the state of described finite state machine includes original state, row meter Calculation state and column count state, finite state machine can change according to external control signal and internal data and carry out state switching；Limited The control signal that state machine is exported determines the source that enters data to and the movement of shift register array of one-dimensional DCT module Direction；

Described data selecting module determines to input the data into one-dimensional DCT module according to control signal, during row calculating state, controls Signal behavior outer input data enters one-dimensional DCT module, and during column count state, control signal selects shift register array defeated The data going out end enter one-dimensional DCT module；

Described one-dimensional DCT module comprise be sequentially connected with adder-subtractor, threshold value judgment module, pipeline register, variable precision Fixing bit wide multiplier, adder-subtractor；The fixing bit wide multiplier of described variable precision has two kinds of computation schemas, is respectively height Accuracy computation pattern and low accuracy computation pattern；Outer input data inputs into threshold decision after first order addition and subtraction Module, described threshold value judgment module is according to current operation mode decision threshold size, and the data of input are only the most permissible more than threshold value Send into pipeline register, be input into fixing bit wide multiplier at next clock and continue to calculate；The result of fixing bit wide multiplier is again Final result of calculation is obtained after addition and subtraction；

Described shift register array is made up of 64 12 bit registers, and every 8 is a row, constitutes 8 and takes advantage of the matrix array of 8； Opening, according to current operation mode, the depositor needing to use and carry out shifting function, the precision of mode of operation is the highest, one-dimensional DCT The DCT coefficient that module calculates is the most, and the depositor needing displacement is the most；During row calculating state, shift register array Storing the results of intermediate calculations of one-dimensional DCT module output line by line, the data that signal controls in shift register array move down directly Shift register array all it is stored in all of intermediate object program；During column count state, shift register array is by after transposition Between result of calculation export one-dimensional DCT module by column, signal controls the data in shift register array and is moved to the left until all Intermediate object program all out of shift register array.