CN106027045A - Direct digital frequency synthesizer based on improved CORDIC algorithm - Google Patents

Abstract

The present invention discloses a direct digital frequency synthesizer based on an improved CORDIC algorithm, including: a phase accumulator and a phase amplitude converter, wherein the phase accumulator is 32 bits wide, and 19 bits wide after the output is truncated; and the phase amplitude converter consists of a lookup table ROM, a multiplier, a super-four rotation module and a block selection module, wherein addressing is performed by the lookup table ROM using the 15-9th bit of a phase word to perform table lookup on the lookup table ROM so as to obtain a rough value of rotation, the rough value is input into the super-four rotation module after being operated by the multiplier, a 9-bit phase word is also input into the super-four rotation module at the same time, rotation calculation is performed on the rough value by the super-four rotation module using the super-four CORDIC algorithm, and a corresponding mirroring operation or turnover operation is performed on data output by the super-four rotation module by the block selection module according to the 18-16th bit finally, thereby obtaining a final output result. The synthesizer disclosed by the present invention has the advantages of lower noise, short conversion time, high SFDR, and few consumption of resources of hardware circuits.

Description

Based on the Direct Digital Frequency Synthesizers improving cordic algorithm

Technical field

The present invention relates to a kind of Direct Digital Frequency Synthesizers, be specifically related to a kind of based on improvement The Direct Digital Frequency Synthesizers of cordic algorithm.

Background technology

Direct Digital Frequency Synthesizers is referred to as DDS, and this is just to develop a kind of some years recently The novel frequency combining apparatus come.This equipment relies on the integrated circuit skill of fast development Art, modern integrated circuits technology is constantly improving according to the prediction of Moore's Law, Direct Digital Frequency synthesizer is the most more and more paid attention under this environment.This frequency synthesis ratio Legacy frequencies synthesis device resolution before equipment is higher, and the conversion time, faster noise was lower, So being widely used in the middle of many electronic systems.

Phase accumulator and phase amplitude converter two parts constitute Direct Digital Frequency Synthesizers Digital circuits section.

In phase amplitude converter, with reference to Fig. 1, traditional CORDIC computing unit calculates Result output can carry out some calculation process, feeds back to input signal end the most again, allows this signal Loop iteration calculating processes with the calculating realizing cosine and sine signal.Purpose is realized by this structure If, the speed of circuit work can be very slow, and the time of general several clock cycle can calculate Export a signal data, in general, if output data are M positions, it is necessary to M The time of clock cycle.

In order to avoid the problems referred to above, conventional way is that the structure using streamline is to design realization The calculating of cosine and sine signal, namely uses polyalgorithm core, carries out repeatedly within the same cycle Process for calculating, can calculate, in each cycle, the data that output is complete thus.If Use the cordic algorithm core of routine, if its input N position, then need N-2 secondary flow Waterline is iterated, and high two select position as quadrant.

But, use the cordic algorithm core of above-mentioned routine to realize the calculating of cosine and sine signal Time, however it remains some problems below, such as:

(1), output time delay is longer；

(2), need to calculate through multiple rotary；

(3) hardware resource, consumed is more.

Summary of the invention

For solving the deficiencies in the prior art, it is an object of the invention to provide a kind of based on improvement The Direct Digital Frequency Synthesizers of cordic algorithm, itself it can be avoided that longer output time delay and Bigger hardware resource consumption.

In order to realize above-mentioned target, the present invention adopts the following technical scheme that:

A kind of Direct Digital Frequency Synthesizers based on improvement cordic algorithm, including: phase place Accumulator and phase amplitude converter, it is characterised in that

Such phase accumulator is made up of adder and phase register, and its bit wide is 32, defeated Going out to block is 19 afterwards, and high 3 are used for carrying out block selection, and ensuing 7 are used for Making a look up table ROM addressing, low 9 rotations for cordic algorithm calculate；

Such phase amplitude converter by look-up table ROM, multiplier, surpass four rotary modules and district Block selects module to form:

Look-up table ROM stores high 7 the corresponding sine and cosine values of phase place word, utilizes phase place Look-up table ROM is tabled look-up and obtains the thick value (X, Y) of rotation by word 15-9 bit addressing, utilizes The value obtained through look-up table ROM addressing is processed by phase place word the 16th, if the 16 is the computing that 0 value obtained of tabling look-up is directly used in next step, if the 16th is 1 Gained (X, Y) value of then tabling look-up is exchanged, and the value that this step obtains is taken advantage of through multiplier Method computing, the coefficient of multiplication isWithData after multiplying are input to surpass In four rotary modules, it is input simultaneously to this phase place word also having 9 surpassing four rotary modules, super Four rotary modules use surpass four cordic algorithms to being slightly worth rotation through look-up table ROM after Remaining 9 phase place words carry out rotating calculating, and utilize the 16th phase place word to different blocks Direction of rotation during CORDIC computing processes, if the 16th is 0, to 0 to 3 Block turns clockwise, and 5 to 7 blocks rotate counterclockwise, and the 4th block is not carried out Rotate, if the 16th is 1,0 to 3 blocks are rotated counterclockwise, to 5 to 7 Block turns clockwise, and the 4th block does not rotates, after rotating calculating, super Four rotary module outputsThe sine and cosine data in region, block selects module according to the 18-16 position is to surpassing four rotary module outputsThe sine and cosine data in region are carried out accordingly Mirror image operation or turning operation, thus obtain last output result.

Aforesaid Direct Digital Frequency Synthesizers based on improvement cordic algorithm, its feature exists In, aforementioned four rotary modules that surpass are surpassed Unit four by three and form,

The binary sequence code of phase place word is by the packet of position from high to low, and three is one group, and it is right often to organize Answer one to surpass Unit four, when carrying out rotation process, with one group as target rotation every time, surpass four single Unit adds certain offset angle value " 100 " on each group, and utilizes the 16th phase place word pair The direction of rotation during computing of different blocks CORDIC processes, if the 16th is 0, Turning clockwise 0 to 3 blocks, 5 to 7 blocks rotate counterclockwise, the 4th district Block does not rotates, if the 16th is 1, rotates 0 to 3 blocks counterclockwise, Turning clockwise 5 to 7 blocks, the 4th block does not rotates.

Aforesaid Direct Digital Frequency Synthesizers based on improvement cordic algorithm, its feature exists In, the phase amplitude converter of aforementioned Direct Digital Frequency Synthesizers uses 16 tunnel interpolations Mode.

The invention have benefit that:

(1), the Direct Digital Frequency Synthesizers of the present invention, because of to tradition cordic algorithm Mode that four cordic algorithms combine is surpassed with look-up table ROM to realize phase place after improvement Amplitude is changed, and decreases calculating iterations, and surpasses four cordic algorithms and carrying out essence Certain phase compensation can be carried out, the phase place width of Direct Digital Frequency Synthesizers while thin rotation Degree transducer uses the mode of 16 tunnel interpolations, so its noise is less, change the time more Short, SFDR is higher；

(2), improve after cordic algorithm because using look-up table to draw and be slightly worth warp again Cross and surpass three the fine rotations of four cordic algorithms and obtain the sin cos functions value of 8 cyclotomy phase places, The symmetry of recycling sine and cosine waveform, obtains the sin cos functions value of whole phase place, and traditional The output of cordic algorithm phase accumulator N position need to carry out N-2 loop iteration, Gao Liangwei Select position as quadrant, so the number of times calculating iteration after Gai Jining reduces, thus decrease hardware The resource consumption of circuit.

Accompanying drawing explanation

Fig. 1 is the structural representation of traditional cordic algorithm；

Fig. 2 is the structural representation of the Direct Digital Frequency Synthesizers of the present invention.

Detailed description of the invention

Below in conjunction with the drawings and specific embodiments, the present invention made concrete introduction.

With reference to Fig. 2, phase accumulator and phase amplitude converter two parts constitute the present invention's The digital circuits section of Direct Digital Frequency Synthesizers.

One, phase accumulator

Phase accumulator is made up of adder and phase register, and wherein, adder is used for phase Adding up in position, phase register is used for depositing phase place, to add up next time, in system Clock f_sControl under, frequency control word FCW from its depositor output enter adder, its Output result backs into adder, the most constantly carries out reciprocal, forms cumulative process.

The arrangement of phase place word: the bit wide of phase accumulator is 32, just remaining due to finally export String value is 16, and therefore a length of 16 blocks increasing 3 of phase place word divide, the most defeated Going out intercepting is 19, and remaining low level is then truncated.

1, high 3 are used for carrying out block selection

Due to sinusoidal wave symmetry and cordic algorithm can calculate simultaneously sine function and Cosine function value, so sinusoidal wave form can be by 8 parts, piecemeal position, high 3 of phase place word is to use In selecting these 8 blocks, the cube of 2 is equal to 8, therefore uses high 3 to carry out block Select.

2, middle 7 are used for making a look up table ROM addressing

Last sine and cosine value is 16 bits, cordic algorithm employed herein The angle rotated in single rotates is 0,1 α, 2 α, 3 α, 4 α respectively, and α is this rotation The basic angle turned, because the error caused during 4 times of angle (i.e. 4 α) is maximum, institute It is less than minimum precision with the error having only to now.The bar that so basis angle [alpha] meets Part is:

$\frac{{\left(4\mathrm{\&alpha;}\right)}^2}{2}<2^{-16}$

So it is known that the requirement that α needs meet is: α < 2^-10。

Cordic algorithm owing to using herein is that (next joint will be concrete in once rotation 3 Illustrate detailed cordic algorithm employed herein), the lowest order in 3 of rotation is just It is the basic angle this time rotated, therefore needs to use 7 phase place words as look-up table ROM's Addressable address.First 3 due to phase place word are used to divide block, the most formal counting again From the beginning of the 4th, namely the 4th to the 10th these 7 as look-up table ROM Addressable address.

3, low 9 rotations for cordic algorithm calculate

Cordic algorithm herein uses and surpasses four cordic algorithms, the most once rotates 3, remain 9 needs and rotate three times.

Two, phase amplitude converter

Phase amplitude converter by look-up table ROM, multiplier, surpass four rotary modules and block choosing Select module composition.

1, look-up table ROM

Look-up table ROM is used for the phase place word of phase accumulator output is slightly worth rotation.

Look-up table ROM stores high 7 the corresponding sine and cosine values of phase place word, utilizes phase place Look-up table ROM is tabled look-up and obtains the thick value (X, Y) of rotation by word 15-9 bit addressing, utilizes Phase place word the 16th (the 16th is block selector, has only to a block herein and selects word) The value obtained through look-up table ROM addressing is processed, if the 16th is 0, looks into The value that table obtains is directly used in next step computing, if the 16th is 1, and gained of tabling look-up (X, Y) value is exchanged, and this is according to sinusoidal wave formRegion withRegion Interior sine and the principle of cosine value specular.

If needed a vector, (x, y) rotates certain angle [alpha], if temporarily not considering amplitude If scaling, then this computing can be represented with the matrix multiplication of formula (1):

If the size of angle [alpha] is sufficiently small, then these just can be used to approximate: sin α ≈ α, Cos α ≈ 1, tan α ≈ 1.

So matrix in formula (1) just can simplify the form of an accepted way of doing sth (2):

This matrix can be used for the original matrix in substituted (1), in actual rotation calculates It also is able to use formula (2) this matrix.

If original matrix is extracted a common factor formula cos α, then the form obtained and formula (2) Form will be closely similar, extract the matrix after common factor formula as follows:

If describing these matrixes more accurately, the simplification matrix in formula (2) is actual The angle rotated not is α, but β=arctan α.If it is to say, using simplification If matrix calculates, due to the actual anglec of rotation and the plan anglec of rotation unequal, An error can be introduced, between the actual anglec of rotation and the plan anglec of rotation, have formula (4) Relation:

Clearly from formula (4) it can be seen that come, the rotation process of approximation can cause the generation of error, Approximation operation also results in the existence of amplitude scaled error simultaneously, and amplitude scaling factor can represent Become following form:

When rotating by the angle of approximation, the error size caused is μ, μ and angle Relation is:

μ≈-α²Formula (6)

When using approximate calculation, if desired the sine and cosine result finally calculated is not produced by error Raw impact, then error μ is necessarily less than the minimum precision of result of calculation.

Last sine and cosine value is 16 bits, cordic algorithm employed herein The angle rotated in single rotates is 0,1 α, 2 α, 3 α, 4 α respectively, and α is this rotation The basic angle turned, because the error caused during 4 times of angle (i.e. 4 α) is maximum, institute It is less than minimum precision with the error having only to now.The bar that so basis angle [alpha] meets Part is:

So it is known that the requirement that α needs meet is: α < 2^-10。

Cordic algorithm owing to using herein is once to rotate 3, in 3 of rotation Lowest order is exactly the basic angle this time rotated, therefore needs to use 7 phase place words as look-up table The addressable address of ROM.First 3 due to phase place word are used to divide block, the most again The counting of formula is from the beginning of the 4th, and namely the 4th to the 10th these 7 conducts are looked into Look for the addressable address of table ROM.

2, multiplier

Multiplier be used for sine and cosine that look-up table ROM is obtained slightly be worth withWithCarry out multiplication Computing.

The value obtained through look-up table ROM addressing carries out multiplying, multiplication through this multiplier Coefficient beWith

Do at this multiplying be in order to rear class surpass four cordic algorithms required for value carry Before calculate, in order to rear class surpass four cordic algorithms realize rotate time have only to carry out Displacement and addition and subtraction operate.

Why the coefficient of multiplication is selectedWithIt is because use when surpassing four cordic algorithms Angle corresponding to fine rotation is the least, now can replace tangent value, algorithm by angle In directly use weight 2 representated by phase place word^-iRepresent angle value, and this weight represents isWeight,Just represent actual angle, so willExtract as common factor formula Calculate in advance in this one-level of multiplier, and useIt is because in algorithm needing as multiplication coefficient Want the data of three times as input.

3, four rotary modules are surpassed

Surpass four rotary modules for after being slightly worth rotation through look-up table ROM remaining 9 Phase place word carries out rotating calculating, and it uses the cordic algorithm after improvement, i.e. surpasses four Cordic algorithm.

Data after multiplying are input to surpass in four rotary modules, are input simultaneously to this Surpass the phase place word also having 9 of four rotary modules, surpass four rotary modules employings and surpass four CORDIC These 9 phase place words are carried out rotating calculating by algorithm, and utilize the 16th phase place word to not same district Direction of rotation during block CORDIC computing processes, if the 16th is 0, arrives 0 3 blocks turn clockwise, and 5 to 7 blocks rotate counterclockwise, and the 4th block does not enters Row rotates, if the 16th is 1, rotates 0 to 3 blocks counterclockwise, arrives 5 7 blocks turn clockwise, and the 4th block does not rotates.

Surpass four rotary modules to use and surpass four cordic algorithms and be slightly worth rotation to through look-up table ROM Turn after remaining 9 phase place words carry out rotate calculate detailed process as follows:

The binary sequence code of phase place word is by the packet of position from high to low, and three is one group, these three Byte determines the angle of rotation, and often corresponding one of group surpasses Unit four, carries out rotation process every time Time, with one group as target rotation, surpass Unit four on each group plus certain offset angle value " 100 ", and utilize the 16th phase place word to direction of rotation during same block CORDIC computing Process, if the 16th is 0,0 to 3 blocks are turned clockwise, 5 to 7 Block rotates counterclockwise, and the 4th block does not rotates, if the 16th is 1, right 0 to 3 blocks rotate counterclockwise, turn clockwise 5 to 7 blocks, the 4th district Block does not rotates, and the phase place word that entirety adds is then " 100100100 ".

Consequently, it is possible to just can rotate the angle of 4 units less when carrying out and rotating and calculate, rotation The number of times turned reduces, and so can simplify calculating.

In the phase amplitude converter of the present invention, we by look-up table ROM with surpass four Cordic algorithm combines, and first uses look-up table ROM to be slightly worth rotation, draws thick value, Calculate exact value through surpassing four cordic algorithms again, thus the effect obtained is: phase Position amplitude converter noise is less, the time is shorter, SFDR is higher, hardware resource consumption in conversion Less.

4, block selects module

Block selector is used for surpassing four rotary module outputsThe sine and cosine value in region is entered The corresponding mirror image operation of row or turning operation.

Four rotary modules outputs are surpassed after rotating calculatingThe sine and cosine data in region, Block selects module according to 18-16 position to surpassing four rotary module outputsRegion is just Cosine data carry out corresponding mirror image operation or turning operation, thus obtain last output As a result, this result is exactly the sine and cosine value using this phase width transducer to calculate gained.

The Direct Digital Frequency Synthesizers of the present invention, its phase amplitude converter uses 16 tunnels The mode of interpolation, which can improve bandwidth.

With reference to Fig. 2, the work process of the Direct Digital Frequency Synthesizers of the present invention is as follows:

Phase accumulator 19 phase place words of output, high 3 are used for carrying out block selection, next 7 be used for making a look up table ROM addressing, low 9 rotations for cordic algorithm Calculating, the look-up table ROM in phase amplitude converter utilizes phase place word 15-9 bit addressing pair Look-up table ROM tables look-up and obtains the thick value (X, Y) of rotation, utilizes phase place word the 16th right The value obtained through look-up table ROM addressing processes, if the 16th is 0, tables look-up The value obtained is directly used in next step computing, if the 16th is 1, gained of tabling look-up (X, Y) value is exchanged, and the value that this step obtains carries out multiplying through multiplier, the coefficient of multiplication It isWithData after multiplying are input to surpass in four rotary modules, simultaneously It is input to this phase place word also having 9 surpassing four rotary modules, surpasses four rotary modules employings and surpass four 9 phase place words remaining after being slightly worth rotation through look-up table ROM are entered by cordic algorithm Row rotates and calculates, and utilizes the 16th phase place word to the rotation during computing of different blocks CORDIC Turn direction to process, if the 16th is 0,0 to 3 blocks turned clockwise, 5 to 7 blocks rotate counterclockwise, and the 4th block does not rotates, if the 16th is 1 Then 0 to 3 blocks are rotated counterclockwise, 5 to 7 blocks are turned clockwise, the 4 blocks do not rotate, and surpass four rotary modules outputs after rotating calculatingRegion Sine and cosine data, block select module according to 18-16 position to surpass four rotary modules outputThe sine and cosine data in region carry out corresponding mirror image operation or turning operation, thus Obtain last output result.

The Direct Digital Frequency Synthesizers of the present invention, because after improving tradition cordic algorithm The mode that four cordic algorithms combine with look-up table ROM that surpasses turn to realize phase amplitude Change, decrease calculating iterations, and surpass four cordic algorithms and finely rotating While can carry out certain phase compensation, the conversion of the phase amplitude of Direct Digital Frequency Synthesizers Device uses the mode of 16 tunnel interpolations, so its noise is less, the conversion time is shorter, SFDR Higher.

Additionally, the Direct Digital Frequency Synthesizers of the present invention, because which employs improvement Cordic algorithm (i.e. surpasses four cordic algorithms), because the cordic algorithm of this improvement Thick value process again surpasses three the fine rotations of four cordic algorithms and obtains 8 to use look-up table to draw The sin cos functions value of cyclotomy phase place, the symmetry of recycling sine and cosine waveform, obtain whole phase The sin cos functions value of position, and the output of tradition cordic algorithm phase accumulator N position need to be entered N-2 loop iteration of row, high two select position as quadrant, so calculating iteration after Gai Jining Number of times reduces, thus decreases the resource consumption of hardware circuit.

It should be noted that above-described embodiment limits the present invention, all employings etc. the most in any form The technical scheme obtained with the mode of replacement or equivalent transformation, all falls within the protection model of the present invention In enclosing.

Claims (3)

1. a Direct Digital Frequency Synthesizers based on improvement cordic algorithm, including: Phase accumulator and phase amplitude converter, it is characterised in that

Described phase accumulator is made up of adder and phase register, and its bit wide is 32, defeated Going out to block is 19 afterwards, and high 3 are used for carrying out block selection, and ensuing 7 are used for Making a look up table ROM addressing, low 9 rotations for cordic algorithm calculate；

Described phase amplitude converter by look-up table ROM, multiplier, surpass four rotary modules and district Block selects module to form:

Look-up table ROM stores high 7 the corresponding sine and cosine values of phase place word, utilizes phase place Look-up table ROM is tabled look-up and obtains the thick value (X, Y) of rotation by word 15-9 bit addressing, utilizes The value obtained through look-up table ROM addressing is processed by phase place word the 16th, if the 16 is the computing that 0 value obtained of tabling look-up is directly used in next step, if the 16th is 1 Gained (X, Y) value of then tabling look-up is exchanged, and the value that this step obtains is taken advantage of through multiplier Method computing, the coefficient of multiplication isWithData after multiplying are input to surpass In four rotary modules, it is input simultaneously to this phase place word also having 9 surpassing four rotary modules, super Four rotary modules use surpass four cordic algorithms to being slightly worth rotation through look-up table ROM after Remaining 9 phase place words carry out rotating calculating, and utilize the 16th phase place word to different blocks Direction of rotation during CORDIC computing processes, if the 16th is 0, to 0 to 3 Block turns clockwise, and 5 to 7 blocks rotate counterclockwise, and the 4th block is not carried out Rotate, if the 16th is 1,0 to 3 blocks are rotated counterclockwise, to 5 to 7 Block turns clockwise, and the 4th block does not rotates, after rotating calculating, super Four rotary module outputsThe sine and cosine data in region, block selects module according to the 18-16 position is to surpassing four rotary module outputsThe sine and cosine data in region are carried out accordingly Mirror image operation or turning operation, thus obtain last output result.

The most according to claim 1 based on the Direct Digital frequency improving cordic algorithm Rate synthesizer, it is characterised in that described four rotary modules that surpass are surpassed Unit four by three and form,

The binary sequence code of phase place word is by the packet of position from high to low, and three is one group, and it is right often to organize Answer one to surpass Unit four, when carrying out rotation process, with one group as target rotation every time, surpass four single Unit adds certain offset angle value " 100 " on each group, and utilizes the 16th phase place word pair The direction of rotation during computing of different blocks CORDIC processes, if the 16th is 0, Turning clockwise 0 to 3 blocks, 5 to 7 blocks rotate counterclockwise, the 4th district Block does not rotates, if the 16th is 1, rotates 0 to 3 blocks counterclockwise, Turning clockwise 5 to 7 blocks, the 4th block does not rotates.

The most according to claim 1 and 2 based on the directly number improving cordic algorithm Word frequency synthesizer, it is characterised in that the phase amplitude of described Direct Digital Frequency Synthesizers turns Parallel operation uses the mode of 16 tunnel interpolations.