CN106024727A - Package with UBM and methods of forming - Google Patents

Package with UBM and methods of forming Download PDF

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Publication number
CN106024727A
CN106024727A CN201510667052.9A CN201510667052A CN106024727A CN 106024727 A CN106024727 A CN 106024727A CN 201510667052 A CN201510667052 A CN 201510667052A CN 106024727 A CN106024727 A CN 106024727A
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China
Prior art keywords
dielectric layer
layer
pattern
connector
integrated circuit
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Granted
Application number
CN201510667052.9A
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Chinese (zh)
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CN106024727B (en
Inventor
陈宪伟
黄立贤
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/671,477 external-priority patent/US10147692B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106024727A publication Critical patent/CN106024727A/en
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Publication of CN106024727B publication Critical patent/CN106024727B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. The invention also relates to a package with UBM and methods of forming.

Description

Packaging part with UBM and forming method thereof
The application relates to the U.S. Patent Application No. 14/605,848 of entitled " Package with UBM and Methods of Forming " that on January 26th, 2015 submits to, and entire contents is incorporated herein by reference as reference.The application is involved in the U.S. Provisional Patent Application the 62/050th, 550 of entitled " the UBM Metal Profile for Reliability Improvement " of JIUYUE in 2014 submission on the 15th, and entire contents is incorporated herein by reference as reference.
Technical field
The present invention relates to packaging part with UBM and forming method thereof.
Background technology
Such as, semiconductor device is used in various electronic application, such as PC, cell phone, digital camera and other electronic equipments.Generally it is sequentially depositing insulation or dielectric layer, conductive layer and semiconductor material layer by side on a semiconductor substrate and uses each material layer of lithographic patterning to manufacture semiconductor device to be formed on circuit unit and element.On single semiconductor crystal wafer, generally manufacture tens of or hundreds of integrated circuits.Single tube core is split by carrying out sawing integrated circuit along line.The most such as, singulated dies is separately packaged the most individually or with multi-chip pattern or with other encapsulated types.
Semiconductor industry updates the integration density of various electronic building brick (such as, transistor, diode, resistor, capacitor etc.) by the size persistently reducing minimal parts, and this allows more assembly to be integrated in given region.In some applications, the less electronic building brick of these such as integrated circuit leads is also required to less packaging part, and these less packaging parts utilize less region than packaging part in the past.
Summary of the invention
In order to solve the problems of the prior art, according to some embodiments of the present invention, it is provided that a kind of package structure, including: integrated circuit lead；Sealant, the most laterally seals described integrated circuit lead；Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution structure includes that the first dielectric layer, described first dielectric layer have the first surface arranged away from described sealant and described integrated circuit lead；Support the connector of metal layer, described metal layer is connected to described redistribution structure, the connector of described support metal layer has Part I and Part II, and described Part I is positioned on the described first surface of described first dielectric layer and described Part II extends in the opening through described first dielectric layer；Pseudo-pattern, is positioned on the described first surface of described first dielectric layer and is positioned at around the connector of described support metal layer；Second dielectric layer, be positioned on the described first surface of described first dielectric layer and be positioned at described pseudo-pattern at least part of on, described second dielectric layer does not contact the connector of described support metal layer；And joint outer part, it is positioned on the connector of described support metal layer.
Other embodiments according to the present invention, it is provided that a kind of package structure, including: integrated circuit lead；Sealant, the most laterally seals described integrated circuit lead；Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution structure includes the first dielectric layer, and described first dielectric layer is arranged away from described sealant and described integrated circuit lead；Support the connector of metal layer, described metal layer is connected to described redistribution structure, the connector of described support metal layer has Part I, Part II and Part III, described Part I is positioned on the first surface of described first dielectric layer, described Part II extends along the bottom surface of the first opening through described first dielectric layer, and described Part III extends and between described Part I and described Part II along the sidewall of described first opening, and abutment is formed at described Part II and contacts the position of described Part III；Second dielectric layer, be positioned on the described first surface of described first dielectric layer and described support metal layer the described Part I of connector, described Part III and described Part II at least some of on；And joint outer part, through the second opening and be positioned at described support metal layer connector on, described second opening pass described second dielectric layer.
Other embodiment according to the present invention, it is provided that a kind of method, including: seal integrated circuit lead with sealant；Forming redistribution structure on described integrated circuit lead and described sealant, described redistribution structure includes that the first dielectric layer, described first dielectric layer have the first surface arranged away from described integrated circuit lead and described sealant；Forming underbump metallization layer (UBM) and pseudo-pattern on described redistribution structure, described puppet pattern is around the described UBM on the described first surface of described first dielectric layer；On the described first surface of described first dielectric layer and described pseudo-pattern at least some of on form the second dielectric layer, wherein, after forming described second dielectric layer, described second dielectric layer does not contact described UBM；And on described UBM, form external electrical connections.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, from described in detail below can best understanding each aspect of the present invention.It should be noted that according to the standard practices in industry, all parts not drawn on scale.It practice, in order to clearly discuss, the size of all parts can at random increase or reduce.
Fig. 1 to Figure 14 be according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.
Figure 15 is the sectional view of the package structure according to some embodiments.
Figure 16 is the sectional view of the package structure according to some embodiments.
Figure 17, Figure 18, Figure 19 A, Figure 20 and Figure 21 be according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.
Figure 19 B is the underbump metallization layer (UBM) according to some embodiments and the layout of pseudo-pattern.
Figure 22 is the sectional view of the package structure according to some embodiments.
Figure 23 is the sectional view of the package structure according to some embodiments.
Figure 24, Figure 25, Figure 26 A, Figure 27 and Figure 28 be according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.
Figure 26 B is the more detailed part of the sectional view in the intermediate steps during forming the technique of package structure according to some embodiments.
Figure 26 C is the UBM through dielectric layer according to some embodiments and the layout of opening.
Figure 29 is the sectional view of the package structure according to some embodiments.
Figure 30 is the sectional view of the package structure according to some embodiments.
Detailed description of the invention
Disclosure below provides many for realizing different embodiments or the example of the different characteristic of provided theme.The instantiation of assembly and layout is described below to simplify the present invention.Certainly, these are only example, and are not intended to limit the present invention.Such as, in the following description, above second component or on formed first component can include that first component is formed as the embodiment directly contacted with second component, and can also be included between first component and second component and can form extra parts, so that the embodiment that first component and second component can be not directly contacted with.Additionally, the present invention can repeat reference numerals and/or letter in various embodiments.This repeats to be for purposes of simplicity and clarity, and itself does not indicate the relation between each embodiment discussed and/or configuration.
And, for ease of describing, this can use such as " ... under ", " in ... lower section ", " bottom ", " ... on ", the space relative terms on " top " etc., in order to an element as depicted or parts and another (or other) element or the relation of parts are described.In addition to the orientation shown in figure, space relative terms is intended to include device different azimuth in use or operation.Device can otherwise orient (90-degree rotation or in other orientation), and space as used herein relative descriptors can be explained the most accordingly.
Embodiments discussed herein can be discussed in specific environment, i.e. there is fan-out or the package structure of fan-in wafer-level packaging part.Other embodiments expect that other are applied, and the most different encapsulated types or different configurations will be apparent from for reading those of ordinary skill in the art of the present invention.It should be noted that, embodiments discussed herein need not illustrate each assembly or parts being likely to be present in structure.Such as, such as when discuss assembly in an each side that can enough pass on embodiment time, multiple assemblies can omit from figure.Additionally, embodiment of the method discussed herein can be discussed as implementing according to particular order；However, it is possible to implement additive method embodiment with any logical order.
Fig. 1 to Figure 14 be according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.Fig. 1 shows carrier substrates 20 and the releasing layer 22 formed in carrier substrates 20.Carrier substrates 20 can be carrier substrate of glass, ceramic monolith substrate etc..Carrier substrates 20 can be wafer.Releasing layer 22 can be formed by polymer-based material, can remove releasing layer 22 and loading substrate 20 together from by the structure of the overlying formed subsequent step.In certain embodiments, releasing layer 22 is the hot releasable material of epoxy radicals of such as photothermal deformation (LTHC) release coating, and it will lose its bond properties when heated.In other embodiments, releasing layer 22 can be ultraviolet (UV) glue, and upon exposure to uv light, it loses its bond properties.Releasing layer 22 can be able to be the laminated film etc. being laminated in carrier substrates 20 as liquid distribution and solidify.Can be formed or spreading adhesive 24 on releasing layer 22.Binding agent 24 can be tube core attachment film (DAF), glue, polymeric material etc..
Integrated circuit lead 26 is attached to carrier substrates 20 (such as, by releasing layer 22) by binding agent 24.As it can be seen, one integrated circuit lead 26 of attachment, and in other embodiments, more integrated circuit lead can be attached.Before being attached to carrier substrates 20, integrated circuit lead 26 can be processed to form integrated circuit in integrated circuit lead 26 according to applicable manufacturing process.Such as, integrated circuit lead 26 includes bulk semiconductor substrate, semiconductor-on-insulator (SOI) substrate, MULTILAYER SUBSTRATE or gradient substrate etc..The quasiconductor of substrate can include any semi-conducting material, the elemental semiconductor of such as silicon, germanium etc., including SiC, GaAs, GaP, InP, InAs, indium antimonide, the compound semiconductor of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP etc. or alloy semiconductor；Or combinations thereof.The such as device of transistor, diode, capacitor, resistor etc. can be formed in Semiconductor substrate and/or goes up and can interconnect to be formed integrated circuit by interconnection structure, interconnection structure passes through, such as, the metallization pattern in the one or more dielectric layers in Semiconductor substrate is formed.
Integrated circuit lead 26 also includes the pad 28 of such as aluminum pad, manufactures the external connection to pad 28.Pad 28 is positioned on the side being properly termed as active side of integrated circuit lead 26.Passivating film 30 is positioned on integrated circuit lead 26 and on part pad 28.Opening passes passivating film 30 to pad 28.The such as tube core connector 32 of conductive pole (such as, including the metal of such as copper) is located across in the opening of passivating film 30 and mechanically and electrically to corresponding pad 28.For example, it is possible to form tube core connector 32 by plating etc..Tube core connector 32 electrically connects the integrated circuit of integrated circuit lead 26.For purpose that is clear and that simplify, integrated circuit lead 26 shows a pad 28 and a tube core connector 32, but it will appreciated by the skilled person that and can there is more than one pad 28 and tube core connector 32.
Dielectric material 34 is positioned in the active side of integrated circuit lead 26, is such as positioned on passivating film 30 and tube core connector 32.Dielectric material 34 laterally package die connector 32, and dielectric material 34 is laterally total to terminal with integrated circuit lead 26.Dielectric material 34 can be polymer, such as polybenzoxazoles (PBO), polyimides, benzocyclobutene (BCB) etc..In other embodiments, dielectric material 34 is that the oxide etc. of the nitride by such as silicon nitride, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG) etc. is formed.Dielectric material 34 can be formed by any acceptable depositing operation of such as spin coating, chemical vapor deposition (CVD), lamination etc. or combinations thereof.Such as can split integrated circuit lead 26 by sawing or cutting, and use such as pickup and place tool, by binding agent 24, integrated circuit lead 26 is bonded to carrier substrates 20.
In fig. 2, each assembly on the binding agent 24 around integrated circuit lead 26 and/or on integrated circuit lead 26 forms sealant 36.Sealant 36 can be moulding compound, epoxy resin etc., and can be applied by compression molding, transfer modling etc..After hardening, sealant 36 can experience grinding technics to expose tube core connector 32.After milling process, the end face of tube core connector 32, dielectric material 34 and sealant 36 is coplanar.In certain embodiments, if having exposed tube core connector 32, then grinding can be omitted.
In figure 3, the first dielectric layer 38 and the first metallization pattern 40 of redistribution structure is formed.Fig. 3 and the exemplary configuration illustrating redistribution structure afterwards, and in other embodiments, redistribution structure can include any amount of dielectric layer, metallization pattern and through hole, as shown in Figure 15 and Figure 16.
First dielectric layer 38 is formed on sealant 36, dielectric material 34 and tube core connector 32.In certain embodiments, the first dielectric layer 38 is formed by polymer, and it can be the light-sensitive material of the such as PBO, polyimides, BCB etc. that use mask easily to be patterned.In other embodiments, the first dielectric layer 38 is that the nitride by such as silicon nitride, such as silicon oxide, the oxide etc. of PSG, BSG, BPSG are formed.The first dielectric layer 38 can be formed by spin coating, lamination, CVD etc. or combinations thereof.Then the first dielectric layer 38 is patterned to form opening to expose part tube core connector 32.Can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, the first dielectric layer 38 is exposed to light or, such as, by using anisotropic etching to be etched.
First dielectric layer 38 is formed first metallization pattern 40 with through hole 42.As forming the first metallization pattern 40 and the example of through hole 42, above the first dielectric layer 38, form crystal seed layer (not shown).In certain embodiments, crystal seed layer is metal level, and it can be monolayer or the composite bed including the multiple sublayers formed by different materials.In certain embodiments, this crystal seed layer includes the layers of copper above titanium layer and titanium layer.It is, for example possible to use physical vapor deposition (PVD) etc. form crystal seed layer.Formed the most on the seed layer and pattern photoresist.This photoresist can be formed by spin coating etc. and can be exposed to light for patterning.The pattern of photoresist corresponds to the first metallization pattern 40.Pattern is formed through the opening of photoresist to expose crystal seed layer.Conductive material is formed in the opening of photoresist and on the expose portion of crystal seed layer.Conductive material can be formed by the plating of such as plating, chemical plating etc..Conductive material can include metal, such as copper, titanium, tungsten, aluminum etc..Then, remove photoresist and the part crystal seed layer being formed without conductive material on it.Photoresist can be removed by the acceptable ashing or stripping technology that such as use oxygen plasma etc..Once photoresist is removed, and such as by using acceptable etch process, is such as removed the expose portion of crystal seed layer by wet or dry ecthing.The remainder of crystal seed layer and conductive material forms the first metallization pattern 40 and through hole 42.Through hole 42 is formed in the opening through following layer (such as, the first dielectric layer 38).
One or more extra metallization pattern with through hole and dielectric layer can be formed in redistribution structure by the technique being recycled and reused for being formed the first dielectric layer 38 and the first metallization pattern 40.As set forth above, it is possible to form through hole during forming metallization pattern.Therefore through hole can interconnect and electrically connect each metallization pattern.One dielectric layer, such as, the first dielectric layer 38 and a metallization pattern described, such as, the first metallization pattern 40 be for the ease of with the purpose simply illustrated.
In the diagram, the first metallization pattern 40 and the first dielectric layer 38 form the second dielectric layer 44.In certain embodiments, the second dielectric layer 44 is formed by polymer, and it can be the light-sensitive material of the such as PBO, polyimides, BCB etc. that use mask easily to be patterned.In other embodiments, the second dielectric layer 44 is that the nitride by such as silicon nitride, such as silicon oxide, the oxide etc. of PSG, BSG, BPSG are formed.The second dielectric layer 44 can be formed by spin coating, lamination, CVD etc. or combinations thereof.Then the second dielectric layer 44 is patterned to form opening 46 to expose part the first metallization pattern 40.Can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, the second dielectric layer 44 is exposed to light or, such as, by using anisotropic etching to be etched.
Fig. 5 to Figure 13 shows underbump metallization layer (UBM) 56 and the formation of the external electrical connections 66 being positioned on a corresponding UBM56.In Figure 5, above the second dielectric layer 44 and in opening 46, such as, on the sidewall of the second dielectric layer 44 and on the first metallization pattern 40, crystal seed layer 48 is formed.In certain embodiments, crystal seed layer 48 is metal level, and it can be monolayer or the composite bed including the multiple sublayers formed by different materials.In certain embodiments, this crystal seed layer 48 includes the layers of copper above titanium layer and titanium layer.It is, for example possible to use PVD etc. form crystal seed layer 48.
In figure 6, photoresist 50 is formed the most on the seed layer.In this embodiment, photoresist 50 is negative photo glue material.Photoresist 50 can be formed on the seed layer by spin coating etc..
In the figure 7, crystal seed layer 48 patterns photoresist 50.Photoresist 50 can be exposed to light and develop subsequently for patterning.Owing to using negative photoresist, after patterning, the part being exposed to light of photoresist 50 still retains.After being exposed to light, lithographic glue 50 is to remove the soluble fraction of photoresist 50, so that the non-soluble fraction of photoresist 50 is retained on crystal seed layer 48, photoresist 50 has the opening 52 through photoresist 50.Opening 52 can have the sidewall 54 of inclination, such as, not vertical with the major surfaces of the such as crystal seed layer 48 below photoresist 50 and/or the second dielectric layer 44 sidewall.As discussed, the sidewall 54 tilted slopes inwardly towards opening on the direction away from following major surfaces.Corresponding angle, θ between sloped sidewall 54 and the table below face being located immediately in opening 52 is less than 90 °, such as between about 60 ° and about 85 °.The pattern of the photoresist 50 corresponding with UBM56 or other metal patterns will be formed.
In fig. 8, UBM56 and upper metal pattern 58 are formed in the corresponding opening 52 of photoresist 50 and on crystal seed layer 48.Such as in the opening 52 of photoresist 50 and on the expose portion of crystal seed layer 48, form conductive material by plating (such as plating or chemical plating etc.).Conductive material can include metal, such as copper, titanium, tungsten, aluminum etc..UBM56 and upper metal pattern 58 can also have the sloped sidewall corresponding with the sloped sidewall 54 of photoresist 50.Therefore, can be less than 90 ° with the angle that following major surfaces is formed by UBM56 and upper metal pattern 58, such as between about 60 ° and about 85 °.
Then, in fig .9, photoresist 50 is removed.Photoresist can be removed by acceptable ashing or stripping technology (such as using oxygen plasma etc.).In Fig. 10, removal crystal seed layer 48 is formed without the part of conductive material.Such as, by using the acceptable etch process of the wettest or dry ecthing to remove the expose portion of crystal seed layer 48.The remainder of crystal seed layer 48 and conductive material form UBM56 and upper metallization pattern 58.Their appropriate section of as directed UBM56 and crystal seed layer 48 is formed in the opening 46 of the second dielectric layer 44 and is positioned on the first metallization pattern 40.Therefore, UBM56 can be electrically connected to the first metallization pattern 40.
In fig. 11, the outer surface of UBM56 and upper metallization pattern 58 forms adhesive layer 60.Adhesive layer 60 can be oxide.Such as, when UBM56 and upper metallization pattern 58 include copper, adhesive layer 60 can include copper oxide.Can be by using acceptable process, such as oxidation processes etc. form adhesive layer 60.In certain embodiments, the surface of UBM 56 and upper metallization pattern 58 can be exposed to the plasma of oxygen carrier, such as, oxygen (O2) plasma, ozone (O3) plasma, noble gas and the combination of oxygen-containing gas, such as nitrogen (N2) and oxygen (O2) combination etc..Other can be used to process, and other adhesive layers can be formed.
In fig. 12, UBM56, on form the 3rd dielectric layer 62 on metallization pattern 58 and the second dielectric layer 44.In certain embodiments, the 3rd dielectric layer 62 is formed by polymer, and it can be the light-sensitive material of the such as PBO, polyimides, BCB etc. that use mask easily to be patterned.In other embodiments, the 3rd dielectric layer 62 is that the nitride by such as silicon nitride, such as silicon oxide, the oxide etc. of PSG, BSG, BPSG are formed.Spin coating, lamination, CVD etc. can be passed through or combinations thereof forms the 3rd dielectric layer 62.Then patterning the 3rd dielectric layer 62 is to form opening 64 with the part adhesive layer 60 on expose portion UBM56 and/or UBM56.Can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, the 3rd dielectric layer 62 is exposed to light or, such as, by using anisotropic etching to be etched.
In fig. 13, remove the part of the adhesive layer 60 exposed by opening 64, and on UBM56, form external electrical connections 66 through opening 64.In certain embodiments, when during ball mounting process, such as, during by melted formation external electrical connections 66, removing the expose portion of adhesive layer 60.In certain embodiments, external electrical connections 66 can include using acceptable ball the to fall reflowable material of low temperature that technique formed on UBM56, such as solder, such as lead-free solder.In certain embodiments, external electrical connections 66 is BGA (BGA) ball, controlled collapse chip connection (C4) projection, dimpling block etc..In a further embodiment, external electrical connections 66 can include metal column.
In fig. 14, implement carrier substrates to separate from package structure, carrier substrates 20 is separated (unsticking).According to some embodiments, separate and include being incident upon on releasing layer 22 light of such as laser or UV light, so that releasing layer 22 decomposes under the heat of light and can remove carrier substrates 20.
Although not describing, then this structure can overturn and be placed on adhesive tape and split.It will be appreciated by the skilled addressee that many such package structures can simultaneously form in carrier substrates 20, and therefore, the single packaging part of the description in such as Figure 14 can such as be split from other packaging parts by sawing or cutting.
Figure 15 shows another sectional view of the package structure according to some embodiments.In the embodiment described by Figure 15, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can be carried out by the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be with the first same or similar material of dielectric layer 38 and can with above in association with first dielectric layer 38 describe same or similar mode be formed.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.This technique then can be according to the carrying out discussed above in association with Fig. 4 to Figure 14, and wherein, the second dielectric layer 44 and the 3rd dielectric layer 62 correspond respectively to the 3rd dielectric layer 76 and the 4th dielectric layer 78 in Figure 15.
Figure 16 shows the further sectional view of the package structure according to some embodiments.In embodiment shown in figure 16, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can proceed the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be and the first same or similar material of dielectric layer 38, and can be formed in the same or similar mode described above in association with the first dielectric layer 38.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.
It is then possible to form the 3rd dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.3rd dielectric layer 80 can be and the first same or similar material of dielectric layer 38, and can be formed in the same or similar mode described above in association with the first dielectric layer 38.Then, the 3rd dielectric layer 80 is patterned with formation opening to expose part the second metallization pattern 72, such as in the same or similar mode described above in association with the first dielectric layer 38.Such as there is the 3rd metallization pattern 82 of through hole 84 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the 3rd dielectric layer 80 and in the opening through the 3rd dielectric layer 80 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.Second metallization pattern 72 is electrically connected to the 3rd metallization pattern 82 by through hole 84.Then can carry out this technique with the discussion above in association with Fig. 4 to Figure 14, wherein, the second dielectric layer 44 and the 3rd dielectric layer 62 correspond respectively to the 4th dielectric layer 86 and the 5th dielectric layer 88 in figure 16.
Figure 17 to Figure 21 show according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.Process according to the carrying out discussed above in association with Fig. 1 to Fig. 5.Then, in fig. 17, crystal seed layer 48 forms photoresist 90.In this embodiment, photoresist 90 can be positive-tone photo glue material or negative photo glue material.Photoresist 90 can be formed on crystal seed layer 48 by spin coating etc..Crystal seed layer 48 patterns photoresist 90.Photoresist 90 can expose to light and be developed to subsequently for patterning.Exposing after light, lithographic glue 90 is to remove the soluble fraction of photoresist 90, so that the non-soluble fraction of photoresist 90 is maintained on crystal seed layer 48, opening 92 is through photoresist 90.Opening 92 can have the sidewall of inclination or vertical sidewall.Other metallization patterns that the pattern of photoresist 90 maybe will be formed corresponding to UBM 94, pseudo-pattern 96.
In figure 18, in the respective openings 92 of photoresist 90 and on crystal seed layer 48, form UBM 94, pseudo-pattern 96 and upper metallization pattern 98.Such as in the opening 92 of photoresist 90 and on the expose portion of crystal seed layer 48, form conductive material by plating, such as plating or chemical plating etc..Conductive material can include metal, such as copper, titanium, tungsten, aluminum etc..UBM 94, pseudo-pattern 96 and upper metallization pattern 98 can also have the sidewall sidewall corresponding to the opening 92 of photoresist 90.
Then, in Figure 19, remove photoresist 50；Remove the expose portion of crystal seed layer 48；And pseudo-pattern 96, on form the 3rd dielectric layer 100 on metallization pattern 98 and the second dielectric layer 44.Photoresist can be removed by the acceptable ashing or stripping technology that such as use oxygen plasma etc..Then, removal crystal seed layer 48 is formed without the part of conductive material.Such as, by using the acceptable etch process of the wettest or dry ecthing to remove the expose portion of crystal seed layer 48.The remainder of crystal seed layer 48 and conductive material form UBM94, pseudo-pattern 96 and upper metallization pattern 98.Their appropriate section of as directed UBM94 and crystal seed layer 48 is formed in the opening 46 of the second dielectric layer 44 and is positioned on the first metallization pattern 40.Therefore, UBM94 can be electrically connected to the first metallization pattern 40.Pseudo-pattern 96 can electrically insulate and be not electrically connected to another metallization or device.Upper metallization pattern 98 can be electrically connected to another metallization pattern and/or device.
Pseudo-pattern 96, on form the 3rd dielectric layer 100 on metallization pattern 98 and the second dielectric layer 44.In certain embodiments, the 3rd dielectric layer 100 is formed by polymer, and it can be the light-sensitive material of the such as PBO, polyimides, BCB etc. that use mask easily to be patterned.In other embodiments, the 3rd dielectric layer 100 is that the nitride by such as silicon nitride, such as silicon oxide, the oxide etc. of PSG, BSG, BPSG are formed.Spin coating, lamination, CVD etc. can be passed through or combinations thereof forms the 3rd dielectric layer 100.Then patterning the 3rd dielectric layer 100 is to form opening 102, and UBM94 is exposed the part to adjacent pseudo-pattern 96 by each opening 102.Can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, the 3rd dielectric layer 100 be exposed to light or such as by using anisotropic etching to be etched.
Figure 19 B shows the exemplary layout of the opening 102 of the UBM 94 according to some embodiments, pseudo-pattern 96 and the 3rd dielectric layer 100.In layout, UBM 94 has octagonal shape, and pseudo-pattern 96 has annular shape, the such as octagonal ring around UBM 94.The layout of Figure 19 B shows the section A-A illustrated in fig. 19 a.Figure 19 A and Figure 19 B shows the size of separation D1 separated by UBM 94 with pseudo-pattern 96.Additionally, Figure 19 A and Figure 19 B shows that dimension D 2, dimension D 2 are the width of pseudo-pattern 96.In certain embodiments, size of separation D1 is greater than or equal to about 40 μm, and dimension D 2 can be in the range of about 5 μm to about 10 μm.
3rd dielectric layer 100 covers at least part of of pseudo-pattern 96, but does not cover UBM 94.In the illustrated embodiment, opening 102 has the sidewall still not contacting with the second dielectric layer 44 or having a common boundary with pseudo-pattern 96.At opening 102, there is not the second dielectric layer 44 and interface of the 3rd dielectric layer 100.Exposed the part of pseudo-pattern 96 by opening 102, and the expose portion of pseudo-pattern 96 has dimension D 3.Dimension D 3 can be about half of dimension D 2 or less.
In fig. 20, external electrical connections 104 is formed on the UBM94 of opening 102.In certain embodiments, the reflowable material of low temperature of external electrical connections 104 can include using acceptable ball to fall such as solder (such as lead-free solder) that technique formed on UBM94.In certain embodiments, external electrical connections 66 is BGA ball, C4 projection, dimpling block etc..In extra embodiment, external electrical connections 104 can include metal column.
In figure 21, implement carrier substrates to separate from package structure, carrier substrates 20 is separated (unsticking).According to some embodiments, separate and include being incident upon on releasing layer 22 light of such as laser or UV light, so that releasing layer 22 decomposes under the heat of light and can remove carrier substrates 20.
Although not describing, then this structure can overturn and be placed on adhesive tape and split.It will be appreciated by the skilled addressee that many such package structures can simultaneously form in carrier substrates 20, and therefore, the single packaging part of the description in such as Figure 21 can such as be split from other packaging parts by sawing or cutting.
Figure 22 shows another sectional view of the package structure according to some embodiments.In embodiment described in fig. 22, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can be carried out by the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be with the first same or similar material of dielectric layer 38 and can with above in association with first dielectric layer 38 describe same or similar mode be formed.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.This technique then can be according to the carrying out discussed above in association with Fig. 4, Fig. 5 and Figure 17 to Figure 21, and wherein, the second dielectric layer 44 and the 3rd dielectric layer 100 correspond respectively to the 3rd dielectric layer 76 and the 4th dielectric layer 106 in Figure 22.
Figure 23 shows the further sectional view of the package structure according to some embodiments.In embodiment shown in fig 23, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can proceed the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be and the first same or similar material of dielectric layer 38, and can be formed in the same or similar mode described above in association with the first dielectric layer 38.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.
It is then possible to form the 3rd dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.3rd dielectric layer 80 can be with the first same or similar material of dielectric layer 38 and can with above in association with first dielectric layer 38 describe same or analogous mode be formed.Then, the 3rd dielectric layer 80 is patterned with formation opening to expose part the second metallization pattern 72, such as in the same or similar mode described above in association with the first dielectric layer 38.Such as there is the 3rd metallization pattern 82 of through hole 84 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the 3rd dielectric layer 80 and in the opening through the 3rd dielectric layer 80 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.Second metallization pattern 72 is electrically connected to the 3rd metallization pattern 82 by through hole 84.Then this technique can carry out the technique discussed above in association with Fig. 4, Fig. 5 and Figure 17 to Figure 21, and wherein, the second dielectric layer 44 and the 3rd dielectric layer 100 correspond respectively to the 4th dielectric layer 86 and the 5th dielectric layer 108 in fig 23.
Figure 24 to Figure 28 show according to some embodiments at the sectional view for forming the intermediate steps during the technique of package structure.Process according to the carrying out discussed above in association with Fig. 1 to Fig. 5.Then, in fig. 24, crystal seed layer 48 forms photoresist 120.In this embodiment, photoresist 120 can be positive-tone photo glue material or negative photo glue material.Photoresist 120 can be formed on crystal seed layer 48 by spin coating etc..Crystal seed layer 48 patterns photoresist 120.Photoresist 120 can expose to light and be developed to subsequently for patterning.Exposing after light, lithographic glue 120 is to remove the soluble fraction of photoresist 120, so that the non-soluble fraction of photoresist 120 is maintained on crystal seed layer 48, opening 122 is through photoresist 120.Opening 122 can have the sidewall of inclination or vertical sidewall.The upper metallization pattern 126 that the pattern of photoresist 120 maybe will be formed corresponding to UBM 124.
In fig. 25, in the respective openings 122 of photoresist 120 and on crystal seed layer 48, UBM 94 and upper metallization pattern 126 are formed.Such as by plating, such as plating or chemical plating etc. form conductive material in the opening 122 of photoresist 120 and on the expose portion of crystal seed layer 48.Conductive material can include metal, such as copper, titanium, tungsten, aluminum etc..UBM 124 and upper metallization pattern 126 can also have the sidewall of the opening 122 corresponding to photoresist 120.
Then, in Figure 26 A, remove photoresist 120；Remove the expose portion of crystal seed layer 48；And on upper metallization pattern the 126, second dielectric layer 44 and part UBM124, form the 3rd dielectric layer 128.Photoresist can be removed by the acceptable ashing or stripping technology that such as use oxygen plasma etc..Then, removal crystal seed layer 48 is formed without the part of conductive material.Such as, by using the acceptable etch process of the wettest or dry ecthing to remove the expose portion of crystal seed layer 48.The remainder of crystal seed layer 48 and conductive material form UBM124 and upper metallization pattern 126.Their appropriate section of as directed UBM124 and crystal seed layer 48 is formed in the opening 46 of the second dielectric layer 44 and is positioned on the first metallization pattern 40.Therefore, UBM124 can be electrically connected to the first metallization pattern 40.
Upper metallization pattern 126 and the second dielectric layer 44 and part UBM124 are formed the 3rd dielectric layer 128.In certain embodiments, the 3rd dielectric layer 128 is formed by polymer, and it can be the light-sensitive material of the such as PBO, polyimides, BCB etc. that use mask easily to be patterned.In other embodiments, the 3rd dielectric layer 128 is that the nitride by such as silicon nitride, such as silicon oxide, the oxide etc. of PSG, BSG, BPSG are formed.Spin coating, lamination, CVD etc. can be passed through or combinations thereof forms the 3rd dielectric layer 128.Then patterning the 3rd dielectric layer 128 is to form opening 130, and each opening 130 exposes part UBM124.Can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, the 3rd dielectric layer 128 be exposed to light or such as by using anisotropic etching to be etched.
Figure 26 B shows the UBM 124 in Figure 26 A and the more detailed sectional view of the opening 130 through the 3rd dielectric layer 128, and Figure 26 C shows UBM 124 and the layout of the opening 130 through the 3rd dielectric layer 128.Figure 26 C shows the section A-A shown in Figure 26 A and Figure 26 B.Figure 26 B and Figure 26 C shows the first planar section 124a, sidewall sections 124b and the second planar section 124c of UBM 124.The first planar section 124a plane earth of UBM 124 extends on the end face of the 3rd dielectric layer 128.The sidewall sections 124b of UBM 124 extends along the sidewall of the opening 46 of the second dielectric layer 44.The second planar section 124c of UBM 124 be in the opening 46 of the second dielectric layer 44 and along the first metallization pattern 40 top surface plane extend.Opening 130 through the 3rd dielectric layer 128 exposes the second planar section 124c of part.3rd dielectric layer 128 covers the first planar section 124a and sidewall sections 124b.3rd dielectric layer 128 extends dimension D 4 from the binding site between sidewall sections 124b and the second planar section 124c.In certain embodiments, dimension D 4 is greater than or equal to about 10 μm.
In figure 27, external electrical connections 132 is formed on the UBM124 of opening 130.In certain embodiments, the reflowable material of low temperature of external electrical connections 132 can include using acceptable ball to fall such as solder (such as lead-free solder) that technique formed on UBM124.In certain embodiments, external electrical connections 132 is BGA ball, C4 projection, dimpling block etc..In extra embodiment, external electrical connections 132 can include metal column.
In Figure 28, implement carrier substrates and separate from package structure, carrier substrates 20 is separated (unsticking).According to some embodiments, separate and include being incident upon on releasing layer 22 light of such as laser or UV light, so that releasing layer 22 decomposes under the heat of light and can remove carrier substrates 20.
Although not describing, then this structure can overturn and be placed on adhesive tape and split.It will be appreciated by the skilled addressee that many such package structures can simultaneously form in carrier substrates 20, and therefore, the single packaging part of the description in such as Figure 28 can such as be split from other packaging parts by sawing or cutting.
Figure 29 shows another sectional view of the package structure according to some embodiments.In embodiment described in Figure 29, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can be carried out by the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be with the first same or similar material of dielectric layer 38 and can with above in association with first dielectric layer 38 describe same or similar mode be formed.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.This technique then can be according to the carrying out discussed above in association with Fig. 4, Fig. 5 and Figure 24 to Figure 28, and wherein, the second dielectric layer 44 and the 3rd dielectric layer 128 correspond respectively to the 3rd dielectric layer 76 and the 4th dielectric layer 134 in Figure 29.
Figure 30 shows the further sectional view of the package structure according to some embodiments.In embodiment shown in fig. 30, redistribution structure includes extra dielectric layer and metallization pattern.In order to form this package structure, technique can proceed the step discussed above in association with Fig. 1 to Fig. 3.It is then possible to form the second dielectric layer 70 on the first dielectric layer 38 and the first metallization pattern 40.Second dielectric layer 70 can be and the first same or similar material of dielectric layer 38, and can be formed in the same or similar mode described above in association with the first dielectric layer 38.The most such as to pattern the second dielectric layer 70 to form opening to expose part the first metallization pattern 40 above in association with the first same or similar mode of dielectric layer 38.Such as there is the second metallization pattern 72 of through hole 74 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the second dielectric layer 70 and in the opening through the second dielectric layer 70 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.First metallization pattern 40 is electrically connected to the second metallization pattern 72 by through hole 74.
It is then possible to form the 3rd dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.3rd dielectric layer 80 can be with the first same or similar material of dielectric layer 38 and can with above in association with first dielectric layer 38 describe same or analogous mode be formed.Then, the 3rd dielectric layer 80 is patterned with formation opening to expose part the second metallization pattern 72, such as in the same or similar mode described above in association with the first dielectric layer 38.Such as there is the 3rd metallization pattern 82 of through hole 84 with the same or similar material described above in association with the first metallization pattern 40 and through hole 42 and being formed on the 3rd dielectric layer 80 and in the opening through the 3rd dielectric layer 80 in the same or similar mode described above in association with the first metallization pattern 40 and through hole 42.Second metallization pattern 72 is electrically connected to the 3rd metallization pattern 82 by through hole 84.Then this technique can carry out the technique discussed above in association with Fig. 4, Fig. 5 and Figure 24 to Figure 28, and wherein, the second dielectric layer 44 and the 3rd dielectric layer 128 correspond respectively to the 4th dielectric layer 86 and the 5th dielectric layer 136 in fig. 30.
Embodiment can realize advantage.By forming adhesive layer 60 on UBM56 and upper metallization pattern 58, the 3rd dielectric layer 62 can have to UBM 56 and the adhesion of the enhancing of upper metallization pattern 58, and it and then can reduce the layering of the 3rd dielectric layer 62.Further, by having sloped sidewall and the sloped sidewall of upper metallization pattern 58 of UBM56, the more surface area that the 3rd dielectric layer 62 can adhere to can obtain, and it can reduce layering.Equally, the sloped sidewall of UBM 56 can reduce protuberance or other accumulations of the 3rd dielectric layer 62 on UBM 56, such as when the 3rd dielectric layer 62 is PBO or another polymeric layer.This can improve the uniformity of the 3rd dielectric layer 62, and it can improve the reliability of packaging part.
Additionally, by having upper dielectric layer, such as with the 3rd dielectric layer 100 and 128 of configuration in some modes discussed above, it is possible to reduce the layering caused by melted infiltration.Such as, by making upper dielectric layer not contact UBM, all as shown in Figure 21, melted on the UBM of technique or the projection landing technique of falling from ball may not contact the interface between upper dielectric layer and another assembly.Do not contact such interface if melted, then can avoid the layering caused by melted infiltration interface.Equally, by having the upper dielectric layer of large area covering UBM, all as shown in Figure 28, melted may have to permeate the interface between upper dielectric layer and UBM further to cause any significant layering of upper dielectric layer.Further seepage distance can reduce the probability of infiltration causing significantly being layered.
Although discussing each embodiment the most respectively, but one ordinarily skilled in the art will readily appreciate that the aspect of some embodiments can be applied to other embodiments.Such as, adhesive layer 60 can apply the upper metallization pattern to the embodiment of Figure 21 and Figure 28 and/or UBM.Additionally, the sloped sidewall of upper metallization pattern in the embodiment that figure 16 illustrates and/or UBM can apply in the embodiment of Figure 21 and Figure 28.
First embodiment is a kind of package structure.Package structure includes: integrated circuit lead；The most laterally seal the sealant of integrated circuit lead；It is positioned at the redistribution structure on integrated circuit lead and sealant；The connector supporting metal layer being connected to redistribution structure and the joint outer part being positioned on the connector supporting metal layer.Redistribution structure includes the first dielectric layer, and the first dielectric layer is arranged away from sealant and integrated circuit lead.The connector supporting metal layer has Part I and Part II, and Part I is positioned on the first surface of the first dielectric layer and Part II extends in the opening through the first dielectric layer.The Part I of the connector supporting metal layer has at the upwardly extending sloped sidewall in the side of the first surface away from the first dielectric layer.
Another embodiment is a kind of package structure.Package structure includes: composite construction, the redistribution structure being positioned on composite construction and the underbump metallization layer (UBM) being positioned on redistribution structure.Composite construction includes integrated circuit lead and the most laterally seals the encapsulant of integrated circuit lead.The first surface of redistribution structure is away from composite construction.UBM has the Part I being positioned on first surface.The sidewall of Part I forms non-perpendicular angles with first surface, and in UBM internal measurement non-perpendicular angles.Adhesive layer is positioned on the Part I of UBM.First dielectric layer is positioned on redistribution structure and adjacent adhesive layer.External electrical connections is arranged through the first dielectric layer and is positioned on UBM.
Further embodiment is a kind of method.The method includes: seals integrated circuit lead with sealant and forms redistribution structure on integrated circuit lead and sealant.Redistribution structure includes metallization pattern and the first dielectric layer being positioned on metallization pattern.First dielectric layer has the first surface away from integrated circuit lead and sealant.The method is additionally included on redistribution structure formation underbump metallization layer (UBM).UBM has the Part I that is positioned on first surface and the Part II being provided through in the opening of the first dielectric layer to metallization pattern.The Part I of UBM has the first surface off plumb sidewall surfaces with the first dielectric layer.The method is additionally included on the first surface of the first dielectric layer and on the Part I of UBM and forms the second dielectric layer and form the external electrical connections through opening to UBM, and opening passes the second dielectric layer.
Another embodiment is a kind of package structure.This package structure includes integrated circuit lead；The most laterally seal the sealant of integrated circuit lead；It is positioned at the redistribution structure on integrated circuit lead and sealant, is connected to the connector supporting metal layer of redistribution structure, pseudo-pattern, the second dielectric layer, and the joint outer part being positioned on the connector supporting metal layer.Redistribution structure includes that the first dielectric layer, the first dielectric layer have the first surface arranged away from sealant and integrated circuit lead.The connector supporting metal layer has Part I and Part II, and Part I is positioned on the first surface of the first dielectric layer and Part II extends in the opening through the first dielectric layer.Pseudo-pattern is positioned on the first surface of the first dielectric layer and supports around the connector of metal layer.Second dielectric layer be positioned on the first surface of the first dielectric layer and pseudo-pattern at least part of on.Second dielectric layer does not contact the connector supporting metal layer.
Further embodiment is a kind of package structure.This package structure includes integrated circuit lead；The most laterally seal the sealant of integrated circuit lead；It is positioned at the redistribution structure on integrated circuit lead and sealant, is connected to the connector supporting metal layer of redistribution structure, the second dielectric layer, and the joint outer part being positioned on the connector supporting metal layer.Redistribution structure includes the first dielectric layer, and the first dielectric layer is arranged away from sealant and integrated circuit lead.The connector supporting metal layer has Part I, Part II and Part III, Part I is positioned on the first surface of the first dielectric layer, Part II extends along the bottom surface of the first opening through the first dielectric layer, and Part III is along the sidewall extension of the first opening and between Part I and Part II.Abutment is formed at the position of Part II contact Part III.Second dielectric layer be positioned on the first surface of the first dielectric layer and support metal layer the Part I of connector, Part III and Part II at least part of on.Joint outer part passes the second opening, and the second opening passes the second dielectric layer.
Another embodiment is a kind of method.The method includes: seal integrated circuit lead with sealant；Forming redistribution structure on integrated circuit lead and sealant, redistribution structure includes that the first dielectric layer, the first dielectric layer have the first surface away from integrated circuit lead and sealant；Forming underbump metallization layer (UBM) and pseudo-pattern on redistribution structure, puppet pattern is around the UBM on the first surface of the first dielectric layer；On the first surface of the first dielectric layer and pseudo-pattern at least part of on form the second dielectric layer, wherein, after forming the second dielectric layer, the second dielectric layer does not contact UBM；And on UBM, form external electrical connections.
Foregoing has outlined the feature of some embodiments so that those skilled in the art may be better understood the aspect of the present invention.It should be appreciated by those skilled in the art that they design or revise based on can readily using the present invention for realizing the purpose identical with in this introduced embodiment and/or realizing other techniques and the structure of identical advantage.Those skilled in the art are it should also be appreciated that this equivalent constructions is without departing from the spirit and scope of the present invention, and without departing from the spirit and scope of the present invention, at this, they can make multiple change, replace and change.
In order to solve the problems of the prior art, according to some embodiments of the present invention, it is provided that a kind of package structure, including: integrated circuit lead；Sealant, the most laterally seals described integrated circuit lead；Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution structure includes that the first dielectric layer, described first dielectric layer have the first surface arranged away from described sealant and described integrated circuit lead；Support the connector of metal layer, described metal layer is connected to described redistribution structure, the connector of described support metal layer has Part I and Part II, and described Part I is positioned on the described first surface of described first dielectric layer and described Part II extends in the opening through described first dielectric layer；Pseudo-pattern, is positioned on the described first surface of described first dielectric layer and is positioned at around the connector of described support metal layer；Second dielectric layer, be positioned on the described first surface of described first dielectric layer and be positioned at described pseudo-pattern at least part of on, described second dielectric layer does not contact the connector of described support metal layer；And joint outer part, it is positioned on the connector of described support metal layer.
In above-mentioned packaging part, also include being positioned at described pseudo-pattern at least part of on adhesive layer.
In above-mentioned packaging part, wherein, described pseudo-pattern is around the region with the described first surface limiting described first dielectric layer, in the described region of the described first surface that the connector of described support metal layer is positioned at described first dielectric layer, described second dielectric layer does not contact the described region of the described first surface of described first dielectric layer.
In above-mentioned packaging part, wherein, the width of described pseudo-pattern is parallel with the described first surface of described first dielectric layer, at least half of the described width that described second dielectric layer is positioned at the described pseudo-pattern of the connector being laterally away from described support metal layer.
In above-mentioned packaging part, wherein, the width of described pseudo-pattern is parallel with the described first surface of described first dielectric layer, in the half of the described width that described second dielectric layer is positioned at the described pseudo-pattern of the connector being laterally away from described support metal layer, in the half of the described width that described second dielectric layer is not positioned at the described pseudo-pattern of the connector being laterally adjacent described support metal layer.
In above-mentioned packaging part, wherein, the width of described pseudo-pattern is parallel with the described first surface of described first dielectric layer, and described width is in the range of 5 μm to 10 μm.
In above-mentioned packaging part, wherein, described pseudo-pattern laterally and is physically separated with the connector of described support metal layer.
In above-mentioned packaging part, wherein, described pseudo-pattern laterally and is physically separated with the connector of described support metal layer；Wherein, described pseudo-pattern laterally and is physically separated at least 40 μm with the connector of described support metal layer.
Other embodiments according to the present invention, it is provided that a kind of package structure, including: integrated circuit lead；Sealant, the most laterally seals described integrated circuit lead；Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution structure includes the first dielectric layer, and described first dielectric layer is arranged away from described sealant and described integrated circuit lead；Support the connector of metal layer, described metal layer is connected to described redistribution structure, the connector of described support metal layer has Part I, Part II and Part III, described Part I is positioned on the first surface of described first dielectric layer, described Part II extends along the bottom surface of the first opening through described first dielectric layer, and described Part III extends and between described Part I and described Part II along the sidewall of described first opening, and abutment is formed at described Part II and contacts the position of described Part III；Second dielectric layer, be positioned on the described first surface of described first dielectric layer and described support metal layer the described Part I of connector, described Part III and described Part II at least some of on；And joint outer part, through the second opening and be positioned at described support metal layer connector on, described second opening pass described second dielectric layer.
In above-mentioned packaging part, wherein, the described Part I of the connector that described second dielectric layer is positioned at described support metal layer extends the distance of at least 10 μm towards the center of the described Part I of the connector of described support metal layer from described abutment.
In above-mentioned packaging part, also include: adhesive layer, on the most described Part I of the connector being positioned at described support metal layer.
In above-mentioned packaging part, wherein, described redistribution structure includes metallization pattern, and described metallization pattern limits at least some of of the described bottom surface of described first opening.
In above-mentioned packaging part, wherein, the described Part II of the connector of described support metal layer contacts the metallization pattern of described redistribution structure.
In above-mentioned packaging part, wherein, described joint outer part includes solder.
Other embodiment according to the present invention, it is provided that a kind of method, including: seal integrated circuit lead with sealant；Forming redistribution structure on described integrated circuit lead and described sealant, described redistribution structure includes that the first dielectric layer, described first dielectric layer have the first surface arranged away from described integrated circuit lead and described sealant；Forming underbump metallization layer (UBM) and pseudo-pattern on described redistribution structure, described puppet pattern is around the described UBM on the described first surface of described first dielectric layer；On the described first surface of described first dielectric layer and described pseudo-pattern at least some of on form the second dielectric layer, wherein, after forming described second dielectric layer, described second dielectric layer does not contact described UBM；And on described UBM, form external electrical connections.
In the above-mentioned methods, also include: in the most described part of described pseudo-pattern, form adhesive layer.
In the above-mentioned methods, wherein, the width of described pseudo-pattern is parallel with the described first surface of described first dielectric layer, at least half of the described width that described second dielectric layer is positioned at the described pseudo-pattern being laterally away from described UBM.
In the above-mentioned methods, wherein, the width of described pseudo-pattern is parallel with the described first surface of described first dielectric layer, in the half of the described width that described second dielectric layer is positioned at the described pseudo-pattern being laterally away from described UBM, in the half of the described width that described second dielectric layer is not positioned at the described pseudo-pattern being laterally adjacent described UBM.
In the above-mentioned methods, wherein, described pseudo-pattern is physically separated with described UBM.
In the above-mentioned methods, wherein, described UBM contacts the metallization pattern of described redistribution structure.

Claims (10)

1. a package structure, including:
Integrated circuit lead；
Sealant, the most laterally seals described integrated circuit lead；
Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution is tied Structure includes that the first dielectric layer, described first dielectric layer have away from described sealant and described integrated circuit The first surface that tube core is arranged；
Supporting the connector of metal layer, described metal layer is connected to described redistribution structure, described The connector supporting metal layer has Part I and Part II, and described Part I is positioned at described On the described first surface of the first dielectric layer and described Part II is through described first dielectric layer Opening extends；
Pseudo-pattern, is positioned on the described first surface of described first dielectric layer and is positioned at described support gold Around the connector of genusization layer；
Second dielectric layer, is positioned on the described first surface of described first dielectric layer and is positioned at described puppet Pattern at least part of on, described second dielectric layer does not contact the connector of described support metal layer； And
Joint outer part, is positioned on the connector of described support metal layer.
Packaging part the most according to claim 1, also includes being positioned at least part of of described pseudo-pattern On adhesive layer.
Packaging part the most according to claim 1, wherein, described pseudo-pattern is around described with restriction The region of the described first surface of the first dielectric layer, the connector of described support metal layer is positioned at described In the described region of the described first surface of the first dielectric layer, described second dielectric layer does not contact described The described region of the described first surface of one dielectric layer.
Packaging part the most according to claim 1, wherein, the width of described pseudo-pattern and described the The described first surface of one dielectric layer is parallel, and described second dielectric layer is positioned at and is laterally away from described support In at least half of the described width of the described pseudo-pattern of the connector of metal layer.
Packaging part the most according to claim 1, wherein, the width of described pseudo-pattern and described the The described first surface of one dielectric layer is parallel, and described second dielectric layer is positioned at and is laterally away from described support In the half of the described width of the described pseudo-pattern of the connector of metal layer, described second dielectric layer is not Be positioned at the described pseudo-pattern of the connector being laterally adjacent described support metal layer described width one On Ban.
Packaging part the most according to claim 1, wherein, the width of described pseudo-pattern and described the The described first surface of one dielectric layer is parallel, and described width is in the range of 5 μm to 10 μm.
Packaging part the most according to claim 1, wherein, described pseudo-pattern and described support metal The connector changing layer laterally and is physically separated.
Packaging part the most according to claim 7, wherein, described pseudo-pattern and described support metal The connector changing layer laterally and is physically separated at least 40 μm.
9. a package structure, including:
Integrated circuit lead；
Sealant, the most laterally seals described integrated circuit lead；
Redistribution structure, is positioned on described integrated circuit lead and described sealant, and described redistribution is tied Structure includes the first dielectric layer, and described first dielectric layer is away from described sealant and described integrated circuit lead Arrange；
Supporting the connector of metal layer, described metal layer is connected to described redistribution structure, described The connector supporting metal layer has Part I, Part II and a Part III, described first Dividing and be positioned on the first surface of described first dielectric layer, described Part II is situated between along through described first The bottom surface of the first opening of electric layer extends, and described Part III is along the sidewall of described first opening Extending and between described Part I and described Part II, abutment is formed at described second Tap touches the position of described Part III；
Second dielectric layer, is positioned on the described first surface of described first dielectric layer and described support metal Change the described Part I of connector, described Part III and at least one of described Part II of layer On Fen；And
Joint outer part, through the second opening and be positioned at described support metal layer connector on, Described second opening passes described second dielectric layer.
10. a method, including:
Integrated circuit lead is sealed with sealant；
Forming redistribution structure on described integrated circuit lead and described sealant, described redistribution is tied Structure includes that the first dielectric layer, described first dielectric layer have away from described integrated circuit lead and described close The first surface that envelope agent is arranged；
Described redistribution structure is formed underbump metallization layer (UBM) and pseudo-pattern, described puppet Pattern is around the described UBM on the described first surface of described first dielectric layer；
On the described first surface of described first dielectric layer and described pseudo-pattern at least some of on Forming the second dielectric layer, wherein, after forming described second dielectric layer, described second dielectric layer is not Contact described UBM；And
Described UBM is formed external electrical connections.
CN201510667052.9A 2015-03-27 2015-10-15 Packaging part and forming method thereof with UBM Active CN106024727B (en)

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