CN106018910A

CN106018910A - Ethernet protocol analysis and trigger circuit and method in oscilloscope

Info

Publication number: CN106018910A
Application number: CN201610323398.1A
Authority: CN
Inventors: 邵成华; 向前; 杨江涛; 吴恒奎
Original assignee: CETC 41 Institute
Current assignee: CETC 41 Institute
Priority date: 2016-05-16
Filing date: 2016-05-16
Publication date: 2016-10-12
Anticipated expiration: 2036-05-16
Also published as: CN106018910B

Abstract

The invention discloses an Ethernet protocol analysis and trigger circuit and method in an oscilloscope, specifically relates to the technical field of test, and solves the defects of high cost, slow decoding speed and short decoding length since the Ethernet protocol analysis and trigger function of the oscilloscope in the prior art is mainly realized by an Ethernet reception chip or software. The Ethernet protocol analysis and trigger circuit in the oscilloscope comprises a channel, a comparator, an analog-digital converter and an FPGA. The FPGA is provided with a peak detection circuit, a sample data processing circuit, a receiving speed-down circuit, a sampling clock generation circuit, a storage control circuit and a receiving processing unit. The receiving processing unit comprises a decoding clock generating circuit, an acquisition circuit, an unwinding start detection circuit, a unwinding circuit, a lead code detection circuit, a 5B/4B encoding-decoding circuit and a frame content detection analysis trigger circuit, wherein the acquisition circuit, the unwinding start detection circuit, the unwinding circuit, the lead code detection circuit, the 5B/4B encoding-decoding circuit and the frame content detection analysis trigger circuit are connected in sequence.

Description

Ethernet protocol analysis and triggering circuit and method in a kind of oscillograph

Technical field

The invention belongs to technical field of measurement and test, be specifically related to Ethernet protocol analysis and triggering circuit and method in a kind of oscillograph.

Background technology

Along with oscillograph needs the signal of test to become increasingly complex, function gets more and more, and how to add cost not increasing or reduce In the case of realize these functions and become particularly important.

Ethernet protocol analysis in oscillograph at present mainly receives chip by Ethernet with Trigger Function or software realizes.Make With Ethernet receive chip scheme as it is shown in figure 1, receive chip mainly realize unwinding, 5B be encoded to 4B coding conversion, The functions such as synchronised clock extraction, send into FPGA be handle well by trigger start frame delimiter, MAC Address, MAC Q-Tag The binary code of the information compositions such as control information, MAC length/type, IP packet header.FPGA only need to do subsequent treatment.

The theory diagram of software implement scheme is as in figure 2 it is shown, FPGA stores the data collected in RAM, and software passes through again FPGA read gather data, then carry out unwinding, 5B be encoded to 4B coding conversion etc..

The shortcoming using the scheme of Ethernet reception chip is relatively costly；The shortcoming of software implement scheme is that decoding speed is very slow, And decoded length is shorter.

Summary of the invention

It is an object of the invention to mainly be received by Ethernet with Trigger Function for the Ethernet protocol analysis in existing oscillograph Chip or software realize, and have that cost is high, decoding speed slow and deficiency that decoded length is shorter, it is proposed that a kind of by setting Put reception processing unit, match and realize Ethernet protocol by receiving processing unit hardware existing with oscillograph and circuit and divide Analysis and Ethernet protocol analysis in a kind of oscillograph triggered and triggering circuit and method.

The present invention specifically adopts the following technical scheme that

Ethernet protocol analysis and triggering circuit in a kind of oscillograph, including passage, comparator, analog-digital converter and FPGA, institute The data signal stating comparator and analog-digital converter all flows to FPGA, devises peak detection circuit, hits in described FPGA According to processing circuit, receiving reduction of speed circuit, sampling clock generation circuit and storage control circuit, the signal of described reception reduction of speed circuit Flowing to peak detection circuit and sampled-data processing circuit respectively, the signal of peak detection circuit flows to passage, described sampled data The signal processing circuit flows to storage control circuit, and described FPGA have also been devised reception processing unit, described reception processing unit bag Include decoding clock generating circuit and the Acquisition Circuit being sequentially connected with, unwinding initiate testing circuit, unwinding circuit, preamble detection electricity Road, 5B/4B codec circuit and content frame detection are analyzed and are triggered circuit, and described decoding clock generating circuit is electric with collection respectively Road, unwinding initiate testing circuit, unwinding circuit, preamble detection circuit, 5B/4B codec circuit and content frame detection point Analysis triggers circuit and is connected.

Preferably, described FPGA have also been devised time base control circuit.

Preferably, described FPGA connects CPU, and described CPU is connected with the first SRAM.

Preferably, described storage control circuit is connected with the second SRAM.

Ethernet protocol analysis and triggering method in a kind of oscillograph, use in oscillograph as above Ethernet protocol analysis with Trigger circuit, it is characterised in that specifically comprise the steps of

Step one: arrange channel gain, then detects the amplitude of signal by peak detection circuit；

Step 2: if the amplitude of signal is the least or too greatly, then resets passage, until the amplitude of signal is sized to make signal Display suitable on oscillograph screen；

Step 3: the amplitude of signal arranges the comparative level of comparator, the Acquisition Circuit output signal to comparator after having adjusted It is acquired, is conveyed into unwinding around code signal and initiates testing circuit by collect and detect, when 11 companies " 1 " being detected Time, starting unwinding circuit and carry out unwinding, the signal of unwinding circuit output is 5B coding；

Step 4: after lead code testing circuit detects lead code, starts to become 4B to encode, then by 4B 5B code conversion Coding sends into content frame detection analysis triggering circuit, and content frame detection simultaneously is analyzed and triggered circuit generation triggering signal, and by data Store in the second SRAM.

The invention have the advantages that: Ethernet protocol analysis and triggering circuit and method in this oscillograph, decoding speed is fast, Decoded length can be arranged, and low cost.

Name said by accompanying drawing

Fig. 1 realizes Ethernet protocol analysis and trigger theory block diagram for using Ethernet to receive chip；

Fig. 2 is that software realizes Ethernet protocol analysis and trigger theory block diagram；

Fig. 3 is the Ethernet protocol analysis that proposes of the present invention and trigger circuit block diagram；

Fig. 4 is data receiver circuit schematic diagram；

Fig. 5 is that unwinding initiates testing circuit schematic diagram；

Fig. 6 is unwinding circuit diagram；

Fig. 7 is 5B/4B synopsis；

Fig. 8 is the Ethernet protocol analysis that proposes of the present invention and trigger flow.

Detailed description of the invention

With specific embodiment, the detailed description of the invention of the present invention is described further below in conjunction with the accompanying drawings:

As it is shown on figure 3, in a kind of oscillograph Ethernet protocol analysis with trigger circuit, including passage, comparator, analog digital conversion Device and FPGA, comparator all flows to FPGA with the data signal of analog-digital converter, devises peak detection circuit, adopts in FPGA Sample data processing circuit, reception reduction of speed circuit, sampling clock generation circuit and storage control circuit, receive the signal of reduction of speed circuit Flowing to peak detection circuit and sampled-data processing circuit respectively, the signal of peak detection circuit flows to passage, sampled-data processing The signal of circuit flows to storage control circuit, have also been devised reception processing unit in FPGA, receives processing unit and includes decoding clock Circuit and Acquisition Circuit, the unwinding being sequentially connected with is occurred to initiate testing circuit, unwinding circuit, preamble detection circuit, 5B/4B Codec circuit and content frame detection are analyzed and are triggered circuit, and decoding clock generating circuit initiates inspection with Acquisition Circuit, unwinding respectively Slowdown monitoring circuit, unwinding circuit, preamble detection circuit, 5B/4B codec circuit are analyzed triggering circuit with content frame detection and are connected. Wherein, FPGA is field programmable gate array.

Have also been devised time base control circuit in FPGA, FPGA connects CPU, and CPU is connected with the first SRAM, storage The second SRAM it is connected with in control circuit.

Decoding clock generating circuit produces Ethernet protocol analysis and triggers 125M and the 250M clock needed.

The signal of comparator output is sent into Acquisition Circuit and is sampled, and is then fed into data receiver circuit as shown in Figure 4, newly adopts The data of sample are assigned to D0, D0 and are assigned to D1, the like, output signal is Reg (0)-Reg (10).

As it is shown in figure 5, the Cleaning Principle that unwinding initiates testing circuit is: the original state of D0-D10 is " 00000000000 ", After startup, the value of D0 is assigned to the value of D1, D1 and is assigned to D2, the like, and D0 to be input signal D_in defeated with Acquisition Circuit The signal Reg (8) gone out and the XOR of Reg (10).Testing circuit needs to detect the state of D0-D10, when its state is Unwinding circuit is just started time " 11111111111 ".

As shown in Figure 6, the operation principle of unwinding circuit is: during unwinding circuit start, and it is defeated that the state of D0-D10 is set to Acquisition Circuit Signal Reg (0)-Reg (10) XOR " 11111111111 " gone out, in Fig. 6, the circuit in dashed box is the polynomial hardware of unwinding Circuit, the data that remaining circuit exports unwinding circuit are converted to 5B coding, input signal Reg (the 9)-Reg (5) of this circuit and Reg (4)-Reg (0) is exactly two 5B coded data.

As it is shown in fig. 7, the operation principle of preamble detection circuit is: compare the output signal of unwinding circuit, when signal is " JK " It is " 55 " afterwards, may be finally time " D5 ", to mean that initiateing of frame valid data containing multiple continuous " 55 ", Start 5B/4B decoding circuit.

5B/4B decoding circuit is exactly the circuit doing a similar look-up table in FPGA, and the input signal of circuit is 5B coding, root Export 4B according to its value according to the 5B/4B synopsis shown in Fig. 7 to encode.

Content frame detection is analyzed and is triggered the operation principle of circuit and be: according to the format detection beginning frame delimiter of frame, MAC Address, MAC Q-Tag controls the deliverings such as information, MAC length/type, IP packet header, TCP packet header and triggers signal, data is stored simultaneously To SRAM.

As shown in Figure 8, Ethernet protocol analysis and triggering method in a kind of oscillograph, use ether in oscillograph as above Network protocol analysis and triggering circuit, it is characterised in that specifically comprise the steps of

Step 2: if the amplitude of signal is the least or too big, (i.e. the amplitude of signal can reach grid on oscilloscope display screen 5～ About 8 lattice, what this amplitude can be suitable demonstrates signal) then reset passage, until the amplitude of signal is sized to make letter Number display suitable on oscillograph screen；

Step 3: the amplitude of signal arranges the comparative level of comparator, the Acquisition Circuit output signal to comparator after having adjusted It is acquired, the scrambler signal collected is conveyed into unwinding and initiates testing circuit and detect, when 11 companies " 1 " being detected Time, starting unwinding circuit and carry out unwinding, the signal of unwinding circuit output is 5B coding；

Certainly, described above is not limitation of the present invention, and the present invention is also not limited to the example above, the art Change that technical staff is made in the essential scope of the present invention, retrofit, add or replace, also should belong to the protection of the present invention Scope.

Claims

1. Ethernet protocol analysis and a triggering circuit in oscillograph, including passage, comparator, analog-digital converter and FPGA, Described comparator all flows to FPGA with the data signal of analog-digital converter, devises at peak detection circuit, sampled data in FPGA Reason circuit, reception reduction of speed circuit, sampling clock generation circuit and storage control circuit, the signal of described reception reduction of speed circuit is respectively Flowing to peak detection circuit and sampled-data processing circuit, the control signal that peak detection circuit produces flows to passage, described sampling The signal of data processing circuit flows to storage control circuit, it is characterised in that have also been devised reception processing unit in described FPGA, Described reception processing unit includes decoding clock generating circuit and Acquisition Circuit, the unwinding being sequentially connected with initiates testing circuit, unwinding Circuit, preamble detection circuit, 5B/4B codec circuit and content frame detection are analyzed and are triggered circuit, and decoding clock occurs electricity Road initiates testing circuit, unwinding circuit, preamble detection circuit, 5B/4B codec circuit respectively with Acquisition Circuit, unwinding Analyze triggering circuit with content frame detection to be connected.

2. Ethernet protocol analysis and triggering circuit in a kind of oscillograph as claimed in claim 1, it is characterised in that described FPGA have also been devised time base control circuit.

3. Ethernet protocol analysis and triggering circuit in a kind of oscillograph as claimed in claim 1, it is characterised in that described FPGA connects CPU, and described CPU is connected with the first SRAM.

4. in oscillograph as claimed in claim 1 a kind of Ethernet protocol analysis with trigger circuit, it is characterised in that described in deposit It is connected with the second SRAM in storage control circuit.

5. Ethernet protocol analysis and a triggering method in oscillograph, uses the oscillograph described in claim 1-4 any one Middle Ethernet protocol analysis and triggering circuit, it is characterised in that specifically comprise the steps of