CN105990313B - A kind of sealing ring of chip - Google Patents
A kind of sealing ring of chip Download PDFInfo
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- CN105990313B CN105990313B CN201510086640.3A CN201510086640A CN105990313B CN 105990313 B CN105990313 B CN 105990313B CN 201510086640 A CN201510086640 A CN 201510086640A CN 105990313 B CN105990313 B CN 105990313B
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- wiring layer
- via hole
- metal wiring
- metal
- sealing ring
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Abstract
This application provides a kind of sealing rings of chip.The sealing ring includes one or more sealing units, and each sealing unit includes: the first metal wiring layer, is arranged around chip, the first metal wiring layer includes mutually isolated the first metal portion and first medium material portion；Second metal wiring layer is oppositely arranged with the first metal wiring layer, and the second metal wiring layer includes mutually isolated the second metal portion and second medium material portion；Interlayer dielectric layer is arranged between the first metal wiring layer and the second metal wiring layer；One or more groups of vias, are arranged in interlayer dielectric layer around chip and the first metal portion of connection and the second metal portion, groups of vias include mutually independent multiple via holes.The problem of via hole forms the obstruction for the adhesion strength that mechanical stress is broken through between the first metal portion and the second metal portion and via hole, alleviates chip edge layering；The rigidity of another aspect via hole reduces the generation for causing deformability to increase, therefore effectively preventing chip edge layering.
Description
Technical field
This application involves technical field of manufacturing semiconductors, in particular to a kind of sealing ring of chip.
Background technique
In semiconductor fabrication process, it can be formed on a semiconductor substrate by techniques such as photoetching, etching and depositions
Semiconductor chip including semiconductor active device and the interconnection structure being arranged on device.In general, on a wafer may be used
To form multiple chips, finally these chips are cut down again from wafer, be packaged technique, forms integrated circuit area.
During cutting chip, stress caused by cutter can damage the edge of chip, result even in chip hair
Raw avalanche.In the prior art, chip is damaged in cutting in order to prevent, and in the active device area periphery of chip, setting is close
Seal ring, the stress which can stop cutter to generate cause the undesired stress fracture of active device area, and core
Piece sealing ring can stop steam infiltration for example containing chemical damage caused by acid substance, the diffusion containing alkaloid substance or pollution sources.
In semiconductor technology now, it is more and more solved using dual chip sealing ring it is more serious rupture ask
Topic, the semiconductor chip structure schematic diagram in the prior art with sealing ring as depicted in figs. 1 and 2.Fig. 1 shows sealing ring
The schematic diagram of the section structure being arranged around chip 2 ', Fig. 2 shows the schematic diagram of the section structure along A '-A ' shown in Fig. 1, wherein show
Sealing ring includes the stepped construction of more metal layers out, wherein each layer of stepped construction as shown in Figure 1 includes inter-level dielectric
Layer 300 ' and discrete metal wiring layer 100 ' that is interior positioned at interlayer dielectric layer 300 ' and being flushed with 300 ' surface of interlayer dielectric layer,
It is connected between neighbouring metal wiring layer 100 ' by via hole 500 '.
But when being sealed using the sealing ring of the prior art, however it remains the problem of 2 ' marginal portion of chip is layered.
This is because, the mechanical stress generated during scribing (die sawing) is entered in sealing ring by interlayer dielectric layer 300 '
Chip in, and then break through the adhesion strength between metal wiring layer 100 ' and via hole 500 ', eventually lead in chip edge generation
The problem of layering.
Summary of the invention
The application is intended to provide a kind of sealing ring of chip, chip marginal portion in the scribing processes to solve the prior art
The problem of being easy layering.
To achieve the goals above, according to the one aspect of the application, a kind of sealing ring of chip, including one are provided
Or multiple sealing units, each sealing unit include: the first metal wiring layer, are arranged around chip, the first metal wiring layer includes
Mutually isolated the first metal portion and first medium material portion；Second metal wiring layer is oppositely arranged with the first metal wiring layer,
Second metal wiring layer includes mutually isolated the second metal portion and second medium material portion；Interlayer dielectric layer is arranged first
Between metal wiring layer and the second metal wiring layer；One or more groups of vias are arranged in interlayer dielectric layer simultaneously around chip
The first metal portion and the second metal portion are connected, groups of vias includes mutually independent multiple via holes.
Further, the shape of above-mentioned via hole is diameter parallel in the cylindric of the first metal wiring layer.
Further, the diameter of above-mentioned via hole is 50~500nm.
Further, the shape of above-mentioned via hole is diameter parallel in the cylindrical shape of the first metal wiring layer.
Further, the outer diameter of above-mentioned via hole is 50~500nm, and the internal diameter of via hole is 20~200nm.
Further, the metal of above-mentioned first metal portion, the second metal portion and via hole is copper, tungsten or aluminium.
Further, the dielectric material in above-mentioned first medium material portion, second medium material portion and interlayer dielectric layer is formed
For the silica of SiOCH, silica, silicon nitride, fluorine silica glass or doped carbon.
Further, above-mentioned groups of vias is multiple, and the via hole face arrangement in adjacent vias group.
Further, above-mentioned groups of vias is multiple, and the via hole in adjacent vias group is staggered.
Further, said sealing unit is multiple, and each sealing unit is stacked on top of each other, and the first gold medal of adjacent seals unit
Belong to wiring layer and the second metal wiring layer is overlapped.
Further, the via hole face arrangement of above-mentioned adjacent seals unit.
Further, the via hole of above-mentioned adjacent seals unit is staggered.
Using the technical solution of the application, via hole therein is mutually indepedent on the direction around chip, therefore scribing
Transmission of the mechanical stress in interlayer dielectric layer is discontinuous in journey, for mechanical stress break through the first metal portion and the second metal portion with
Adhesion strength between via hole, which is formed, to be hindered, and the problem of chip edge is layered is alleviated；The via hole of another aspect the application relative to
The body volume of via hole reduces in the prior art, so that the rigidity of via hole reduces, and then is leading to the due to mechanical stress effect
When juxtaposition metamorphose between one metal portion, the second metal portion and via hole, the rigidity of via hole, which reduces, causes deformability to increase, therefore
Effectively prevent the generation of chip edge layering.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the schematic diagram of the section structure of sealing ring in the prior art；
Fig. 2 shows the schematic diagram of the section structure in the direction A '-A ' of sealing ring shown in Fig. 1；
Fig. 3 shows the schematic diagram of the section structure for the sealing ring that a kind of preferred embodiment of the application provides；
Fig. 4 shows the schematic diagram of the section structure in the direction A-A of sealing ring shown in Fig. 3；
Fig. 5 shows the schematic diagram of the section structure along the direction B-B of sealing ring shown in Fig. 4；
Fig. 6 shows section knot of the sealing ring along B-B direction shown in Fig. 4 of the application another kind preferred embodiment offer
Structure schematic diagram；
Fig. 7 shows section knot of the sealing ring along A-A direction shown in Fig. 3 of the application another kind preferred embodiment offer
Structure schematic diagram；
Fig. 8 shows the flow diagram that production has the sealing ring of cross-section structure shown in Fig. 4；
Fig. 9 to Figure 16 shows the schematic diagram of the section structure after executing each step shown in Fig. 8, wherein
Fig. 9 shows the schematic diagram of the section structure after forming first medium material；
Figure 10 shows etching first medium material shown in Fig. 9 and forms cuing open after first medium material portion and the first groove
Face structural schematic diagram；
Figure 11 shows the first medium material portion that the first metal wiring layer is formed in structure shown in Fig. 10 and
The schematic diagram of the section structure after one metal portion；
Figure 12 is shown on the first metal wiring layer shown in Figure 11 after deposits dielectric materials formation interlayer dielectric layer
The schematic diagram of the section structure；
Figure 13, which is shown, performs etching the signal of the cross-section structure after forming the second groove to interlayer dielectric layer shown in Figure 12
Figure；
Figure 14 shows deposited metal in the structure into Figure 13 with the second groove and carries out to the metal deposited flat
Smoothization processing forms the schematic diagram of the section structure after via hole；
Figure 15 shows the schematic diagram of the section structure deposited after second medium material on the surface of the structure shown in Figure 14；
Figure 16 shows to perform etching second medium material shown in figure 15 to form second medium material portion and third is recessed
The schematic diagram of the section structure after slot；And
It is carried out Figure 17 shows deposited metal material in the structure shown in Figure 16 and to the metal material deposited flat
Change processing, the schematic diagram of the section structure after obtaining the second metal portion.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also be intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As background technique is introduced, the mechanical stress generated in current scribing processes passes through interlayer dielectric layer and enters
In chip in sealing ring, and then the adhesion strength between metal wiring layer and via hole is broken through, eventually leads to and produced in chip edge
Layer estranged, in order to solve the problems, such as that chip is easy layering in scribing processes as above, present applicant proposes a kind of sealings of chip
Ring.
Fig. 3 and Fig. 4 shows sealing ring the cuing open in different directions for the chip that a kind of preferred embodiment of the application provides
Face structural schematic diagram, the sealing ring include one or more sealing units, each sealing unit include the first metal wiring layer 100,
Second metal wiring layer 400, interlayer dielectric layer 200, one or more groups of vias；First metal wiring layer 100 is set around chip 2
Set, including the first mutually isolated metal portion 101 and first medium material portion 102 (see Fig. 4), the second metal wiring layer 400 with
First metal wiring layer 100 is oppositely arranged, including the second mutually isolated metal portion 401 and second medium material portion 402 (see figure
4)；Interlayer dielectric layer 200 is arranged between the first metal wiring layer 100 and the second metal wiring layer 400；Groups of vias surrounds chip
2 are arranged in interlayer dielectric layer 200 and connect the first metal portion 101 and the second metal portion 401, and each groups of vias includes mutually indepedent
Multiple via holes 300.
Sealing ring with above structure, via hole 300 therein is mutually indepedent on the direction around chip, therefore scribing
Transmission of the mechanical stress in interlayer dielectric layer 200 is discontinuous in the process, breaks through the first metal portion 101 and second for mechanical stress
Adhesion strength between metal portion 102 and via hole 300 forms the problem of hindering, alleviating 2 edge delamination of chip；On the other hand this Shen
Via hole 300 please compared with the existing technology in via hole 500 ' body volume reduce so that via hole 300 rigidity reduce, in turn
When leading to the juxtaposition metamorphose between the first metal portion 101, the second metal portion 401 and via hole 300 due to mechanical stress effect, mistake
The rigidity in hole 300, which reduces, causes deformability to increase, therefore effectively prevents the generation of 2 edge delamination of chip.
The application in order to enable the rigidity of via hole 300 is uniformly distributed in the plane parallel with the first metal wiring layer 100,
It is preferred that as shown in figure 5, the shape of above-mentioned via hole 300 is axis perpendicular to the cylindric of the first metal wiring layer 100.In addition, this
When the via hole 300 of application is cylindric, the diameter of the cylinder can be big using the thickness of the via hole 500 ' of this field routine
Small, the diameter of preferably above-mentioned via hole 300 is 50~500nm, preferably 100~500nm, further preferred 100~400nm, more into
One step preferably 150~350nm, most preferably 200~300nm.
In another preferred embodiment of the application, the shape of preferably above-mentioned via hole 300 is axis perpendicular to first
The cylindrical shape of metal wiring layer 100.It is well known by those skilled in the art that the material of via hole 300 and the material of interlayer dielectric layer 200
Matter is different, therefore the two is different from the contact stress of the first adjacent metal portion 101 and the second metal portion 401, and machinery is caused to be answered
The transmission of power is also different, and under the action of the factors such as the rigidity reduction of via hole 300 as described above, more fully prevents
The generation of 2 edge delamination of chip.Equally, the application in order to enable via hole 300 rigidity parallel with the first metal wiring layer 100
Plane on be uniformly distributed, preferably as shown in figure 5, the shape of via hole 300 be diameter parallel in the circle of the first metal wiring layer 100
Tubular.It is analyzed from mechanics principle, the flexural stress of cylindrical body is gradually reduced from periphery to the center of circle, that is to say, that the center point
Flexural stress is smaller, therefore cylinder is set as hollow cylindrical shape and is not had much affect to the bending resistance of via hole itself, and
And after by via hole setting cylindrical shape, the body diameter of same consumptive material is less than drum diameter, and the increase of drum diameter compensated for
Therefore the decrease of the bending resistance in hole 300 sets the cylindric bending resistance for improving via hole 300, more for via hole 300
Effectively prevent the generation of 2 edge delamination of chip.
In addition, the outer diameter size of the cylinder can use the mistake of this field routine when the via hole 300 of the application is cylindric
The thickness size in hole 500 ', the outer diameter of preferably above-mentioned via hole 300 are 50~500nm, preferably 100~500nm, further preferably
100~400nm, still more preferably 150~350nm, most preferably 200~300nm, the internal diameter of via hole 300 are 20~200nm,
It is preferred that 30~200nm, further preferred 50~200nm, still more preferably 50~150nm, most preferably 50~100nm.
The application is in order to advanced optimize the effect for preventing 2 edge delamination of chip of above-mentioned sealing ring, preferably above-mentioned via hole
Group is multiple, 300 face of the via hole arrangement in preferably 3~6 and adjacent vias group.
In addition, the application prevents effect and the sealing ring of 2 edge delamination of chip to advanced optimize above-mentioned sealing ring
Sealing function, preferably above-mentioned groups of vias be it is multiple, the via hole 300 in preferably 3~6 and adjacent vias group is staggered.
As shown in fig. 6, the via hole 300 in adjacent vias group is staggered, in realizing on 2 direction of chip for interlayer dielectric layer 200
The sealing of metal material.
In a kind of preferred embodiment of the application, said sealing unit be it is multiple, preferably 6~8, each sealing is single
Member is stacked on top of each other, and the first metal wiring layer 100 of adjacent seals unit and the second metal wiring layer 400 are overlapped.Such as Fig. 7 institute
Show, sealing ring is stacked up and down, so as to by the first metal wiring layer 100 and the second metal wiring layer 400 of adjacent seals ring
It is overlapped setting, so that the total of entire sealing ring is more compact, sealing performance is more preferable.
When the sealing ring of the application has multiple sealing units, 300 face of via hole of adjacent seals unit can be set
Arrangement.Also the via hole 300 that adjacent seals unit can be set is staggered.If 300 face of via hole of adjacent seals unit is arranged
Cloth can be performed etching using mutually isostructural mask plate when making each via hole 300, save the cost of manufacture of sealing ring；Such as
The via hole of fruit adjacent seals unit is staggered, and the mask plate structure of use can be varied, but enable to sealing ring
Structure is more stable, can be better protected from the generation of 2 edge delamination of chip.
In addition, the application makes each metal portion and technology commonly used in the art can be used in the metal of via hole, preferably
Above-mentioned metal is copper, tungsten or aluminium.Equally, the dielectric material for forming each dielectric material portion can also use medium commonly used in the art
Material is preferably formed as above-mentioned first medium material portion 102, second medium material portion 402, interlayer dielectric layer 200 and central medium
The dielectric material in material portion 301 can be respectively the silica of SiOCH, silica, silicon nitride, fluorine silica glass or doped carbon.
In order to make those skilled in the art more fully understand the application sealing ring structure, now, with reference to the accompanying drawings more
Describe the manufacturing process of the seal ring structure of the application in detail.However, these illustrative embodiments can be by a variety of differences
Form implement, and should not be construed to be limited solely to embodiments set forth herein.It should be understood that providing this
A little embodiments are in order to enable disclosure herein is thorough and complete and the design of these illustrative embodiments is abundant
Those of ordinary skill in the art are communicated to, in the accompanying drawings, for the sake of clarity, expand the thickness of layer and region, and use
Identical appended drawing reference indicates identical device, thus will omit description of them.
Firstly, forming the first metal wiring layer 100 shown in Figure 11, which is further included steps of
First medium material 102 ' shown in Fig. 9 is set, it should be clear to those skilled in the art that the dielectric material is
Be arranged on the surface for the peripheral structure of chip for having completed the preceding road process structure of semiconductor, wherein Fig. 9 be not shown chip and
Its peripheral structure.The dielectric material 102 ' can use dielectric materials commonly used in the art, preferably SiOCH, silica, nitridation
The silica of silicon, fluorine silica glass or doped carbon.
The first medium material 102 ' is performed etching, first medium material shown in Fig. 10 portion 102 is formed and is located at it
In the first metal portion 101 where the first groove 101 '.The etching process uses wet etching or dry method commonly used in the art
Etching etching is implemented, it is preferred to use the dry etching method with anisotropic etching characteristic.
The deposited metal material in structure shown in Fig. 10, and planarization process is carried out to metal material, obtain Figure 11 institute
The first medium material portion 102 shown and the first metal portion 101 being located in the first groove 101 ' shown in Figure 10.It is above-mentioned to deposit
Journey can be used using implementation Process, planarization processes such as chemical vapor deposition commonly used in the art, physical vapour deposition (PVD)s
The chemical-mechanical planarization of this field routine is implemented.
Then, it after forming the first metal wiring layer 100 shown in Figure 11, deposits and is situated between on the first metal wiring layer 100
Material forms interlayer dielectric layer 200 shown in Figure 12.
Then interlayer dielectric layer 200 shown in Figure 12 is performed etching, forms the second groove 300 ' shown in Figure 13.The quarter
Erosion process includes: that photoresist is arranged on interlayer dielectric layer 200, is then carried out using designed mask plate to photoresist
The processing such as exposure, development, form patterned photoresist exposure mask；Then to interlayer dielectric layer under the protection of the photoresist exposure mask
200 perform etching, and form the second groove 300 ' shown in Figure 13；Remove the photoresist exposure mask.Etching process therein is using wet
Method etching or dry etching are implemented, it is preferred to use chemical drying method etching, make to be formed by the second groove 300 ' from upper and
Lower wall is more regular, and photoresist exposure mask is implemented using ashing method commonly used in the art, wherein the implementation of above-mentioned each specific steps
Condition those skilled in the art can refer to common process, and details are not described herein.
In the above process, covered according to the photoresist that the opening shape figure of applied mask plate dissolves different openings shape
Film, such as the circle or annular of the application, then performed etching under the protection of the photoresist exposure mask to be formed it is corresponding cylindric or
The second cylindric groove 300 '.
There is deposited metal in the structure of the second groove 300 ' into Figure 13 and the metal deposited is carried out at planarization
Reason forms via hole 300 shown in Figure 14, and the implementation of this field conventional technique can be used in above-mentioned deposition and planarization process,
This is repeated no more.
It is formed after via hole 300, forms the second gold medal on the surface of via hole 300 and interlayer dielectric layer 200 shown in Figure 14
Belong to wiring layer 400 (referring to Figure 17), which further includes steps of
Second medium material 402 ' is deposited in the structure shown in Figure 14, forms the sealing ring with cross-section structure shown in Figure 15
Structure.The second medium material 402 ' this time deposited is identical as the material of first medium material 102 ' that front is deposited, and
Deposition method can also be identical.
Second medium material 402 ' shown in figure 15 is performed etching, the second metal wiring layer 400 shown in Figure 16 is formed
Second medium material portion 402 and third groove 401 '.The etching process of the step can be with reference to first medium material 102 '
The etching process of etachable material, details are not described herein.
After forming third groove 401 ', deposited metal material and to the metal material deposited in the structure shown in Figure 16
Planarization process is carried out, the second metal portion 401 of the second metal wiring layer 400 shown in Figure 17 is obtained.It can be seen that the second gold medal
Belong to wiring layer 400 it is similar to the forming process of the first metal wiring layer 100, also in the prior art production metal wiring layer work
Skill is similar, and specific process implementing condition can also be carried out with reference to the prior art.
It can be seen from the above description that the application the above embodiments realize following technical effect:
1), the via hole of the application sealing ring is mutually indepedent on the direction around chip, therefore machinery is answered in scribing processes
Transmission of the power in interlayer dielectric layer is discontinuous, breaks through between the first metal portion and the second metal portion and via hole for mechanical stress
Adhesion strength, which is formed, to be hindered, and the problem of chip edge is layered is alleviated；
2), the via hole of the application compared with the existing technology in via hole body volume reduce so that via hole rigidity reduce,
And then when due to mechanical stress effect lead to the juxtaposition metamorphose between the first metal portion, the second metal portion and via hole when, via hole
Rigidity reduce cause deformability to increase, therefore effectively prevent chip edge layering generation；
3), the forming method of above-mentioned sealing ring is implemented using the combination of conventional technical means in the art, therefore,
Be conducive to the popularization and application of the sealing ring in practice.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (9)
1. a kind of sealing ring of chip, including one or more sealing units, each sealing unit include:
First metal wiring layer is arranged around the chip, and first metal wiring layer includes the first mutually isolated metal
Portion and first medium material portion；
Second metal wiring layer is oppositely arranged with first metal wiring layer, second metal wiring layer include mutually every
From the second metal portion and second medium material portion；
Interlayer dielectric layer is arranged between first metal wiring layer and the second metal wiring layer；
One or more groups of vias, around the chip be arranged in the interlayer dielectric layer and connect first metal portion and
Second metal portion, the groups of vias include mutually independent multiple via holes, which is characterized in that the shape of the via hole is axis
Line is cylindric or cylindric perpendicular to first metal wiring layer；Form first medium material portion, second medium material
The dielectric material of material portion and the interlayer dielectric layer is the silica of SiOCH, silica, silicon nitride, fluorine silica glass or doped carbon.
2. sealing ring according to claim 1, which is characterized in that the diameter of the cylindric via hole is 50~500nm.
3. sealing ring according to claim 1, which is characterized in that the outer diameter of the cylindrical shape via hole is 50~500nm, institute
The internal diameter for stating cylindric via hole is 20~200nm.
4. sealing ring according to claim 1, which is characterized in that first metal portion, the second metal portion and the mistake
The metal in hole is copper, tungsten or aluminium.
5. sealing ring according to claim 1, which is characterized in that the groups of vias is multiple, and the adjacent groups of vias
In the via hole face arrangement.
6. sealing ring according to claim 1, which is characterized in that the groups of vias is multiple, and the adjacent groups of vias
In the via hole it is staggered.
7. sealing ring according to claim 1, which is characterized in that the sealing unit is multiple, each sealing unit
It is stacked on top of each other, and the first metal wiring layer of the adjacent sealing unit and the second metal wiring layer are overlapped.
8. sealing ring according to claim 7, which is characterized in that the via hole face of the adjacent sealing unit is arranged.
9. sealing ring according to claim 7, which is characterized in that the via hole of the adjacent sealing unit is staggered.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510086640.3A CN105990313B (en) | 2015-02-17 | 2015-02-17 | A kind of sealing ring of chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510086640.3A CN105990313B (en) | 2015-02-17 | 2015-02-17 | A kind of sealing ring of chip |
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| CN105990313B true CN105990313B (en) | 2019-01-29 |
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| CN107946246B (en) * | 2016-10-12 | 2020-08-25 | 中芯国际集成电路制造(上海)有限公司 | Seal ring structure, semiconductor device, and electronic apparatus |
| CN111900131B (en) * | 2020-07-03 | 2022-01-07 | 沈佳慧 | Sealing ring structure of semiconductor wafer and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105321891A (en) * | 2014-07-30 | 2016-02-10 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing the same |
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| WO2004097916A1 (en) * | 2003-04-30 | 2004-11-11 | Fujitsu Limited | Method for fabricating semiconductor device, semiconductor wafer and semiconductor device |
| JP4280204B2 (en) * | 2004-06-15 | 2009-06-17 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device |
| JP5106933B2 (en) * | 2007-07-04 | 2012-12-26 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| US8334582B2 (en) * | 2008-06-26 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protective seal ring for preventing die-saw induced stress |
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| CN105321891A (en) * | 2014-07-30 | 2016-02-10 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing the same |
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