CN105978541A - Method capable of realizing fast signal tracking - Google Patents
Method capable of realizing fast signal tracking Download PDFInfo
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- CN105978541A CN105978541A CN201610275107.6A CN201610275107A CN105978541A CN 105978541 A CN105978541 A CN 105978541A CN 201610275107 A CN201610275107 A CN 201610275107A CN 105978541 A CN105978541 A CN 105978541A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to a method capable of realizing fast signal tracking. The processing for implementing the method includes the following steps that: a delay unit carries out delay processing on first signals SIGA, so as to generate a delayed signal group composed of n paths of delayed signals; a sampling unit selects m paths of signals from the first signals and the delayed signal group to form a first input signal group, and carries out sampling processing based on the first input signal group and second signals SIGB, so as to generate a sampling signal group composed of m paths of sampling signals; a judgment unit selects m path of sub signals from the delayed signal group, makes the m path of sub signals from the delayed signal group be in one-to-one correspondence with m paths of sub signals in the sampling signal group; and the judgment unit monitors the state of the sub signals in the sampling signal group according to a judgment rule, selects one path of sub signals from the sampling signal group which satisfy the judgment rule as judgment signals and triggers judgment operation when the sub signals in the sampling signal group satisfy the judgment rule, adopts sub signals of the delayed signal group corresponding to the judgment signals as output signals SIGO and maintains the situation until next judgment, so that the tracking of the second signals SIGB is realized.
Description
Technical field
The present invention relates to a kind of method realizing fast signal tracking.
Background technology
Signal trace is a kind of common signal of communication processing links, the signal tracking circuit in the process of conventional signal of communication
The problem that there is required tracking time length.For this problem, this patent proposes a kind of method realizing fast signal tracking
And circuit.
Summary of the invention
It is an object of the invention to provide a kind of method realizing fast signal tracking, exist to overcome in prior art
Defect.For achieving the above object, the technical scheme is that a kind of method realizing fast signal tracking, including: one
Delay cell, a sampling unit and a decision unit, realize in accordance with the following steps:
Step S1: described delay unit carries out delay process to the first signal SIGA, produces and postpones signal group, described delay signal
Group is made up of the n way signal of DL1 to DLn, and inputs described first signal SIGA and described delay signal group to described
Sampling unit, wherein, n is the integer not less than 1；
Step S2: described sampling unit will pick out m road signal structure from described first signal SIGA and described delay signal group
Become the first input signal group, in conjunction with described first input signal group and described secondary signal SIGB, carry out sampling processing, and produce
Sampled signal group, described sampled signal group is made up of the m way signal of SP1 to SPm, and wherein, m is the positive integer of no more than n；
Step S3: described decision unit receives described delay signal group and described sampled signal group respectively, and from described delay
Signal group is picked out m way signal, is allowed to and m way signal SP1 to SPm one_to_one corresponding in described sampled signal group；
Step S4: the state of each subsignal in described sampled signal group is monitored by described decision unit according to decision rule,
When described sampled signal group neutron signal meets decision rule, by from the described sampled signal group subsignal meeting decision rule
In pick out 1 way signal and as decision signal and trigger generation decision operation, the corresponding relation determined according to step S3, by institute
State the described delay signal group subsignal corresponding to decision signal as output signal SIGO and to maintain to adjudicating generation next time.
Subsignal DL1 to DLn phase in an embodiment of the present invention, in described step S1, in described delay signal group
First retardation differs respectively to the n-th retardation for described first signal SIGA, and described first retardation is prolonged to described n-th
Amount is incremented by order late.
In an embodiment of the present invention, in described step S2, described sampling unit using described secondary signal SIGB as
Sampling clock, samples to each subsignal in described first input signal group respectively, generates described sampled signal group.
In an embodiment of the present invention, in described step S4, described decision unit detects described sampled signal group respectively
In the voltage status of each subsignal, and when described in arbitrary neighborhood two-way, sampled signal group subsignal voltage status is contrary, trigger
Produce decision operation.
In an embodiment of the present invention, when the rising edge of described secondary signal SIGB is followed the trail of, in the most described step S4 when
When described adjacent two-way sampled signal group subsignal voltage status is respectively high level and low level, triggers and produce described criterion behaviour
Make.
In an embodiment of the present invention, in described step S2, described sampling unit will use described first input signal
In group, each subsignal is respectively as sampling clock, samples described secondary signal SIGB, generates described sampled signal group.
In an embodiment of the present invention, in described step S4, described decision unit detects described sampled signal group respectively
In the voltage status of each subsignal, and when described in arbitrary neighborhood two-way, sampled signal group subsignal voltage status is contrary, trigger
Produce decision operation.
In an embodiment of the present invention, when the rising edge of described secondary signal SIGB is followed the trail of, in the most described step S4 when
When described adjacent two-way sampling group's subsignal voltage status is respectively low level and high level, triggers and produce the operation of described criterion.
Compared to prior art, the method have the advantages that one proposed by the invention can realize quickly believing
Number method followed the tracks of, can quickly produce output signal and realize tracking to secondary signal.
Accompanying drawing explanation
Fig. 1 is a kind of circuit realizing fast signal tracking in the present invention.
Fig. 2 is that in the present invention, in an embodiment, sampling unit does not uses secondary signal to carry out rising edge as sampling clock to adopt
Each signal sequence during sample.
Fig. 3 is that in the present invention, in an embodiment, sampling unit uses secondary signal to carry out rising edge sampling as sampling clock
Time each signal sequence.
Fig. 4 is that in the present invention, in another embodiment, sampling unit uses secondary signal to carry out rising edge as sampling clock and adopt
Each signal sequence during sample.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is specifically described.
The circuit that realized fast signal in the present invention is followed the tracks of is made up of delay cell, sampling unit, decision unit, its
Structure is as shown in Figure 1.
Further, delay cell carries out delay disposal to input clock signal SIGA, produce n road postpone signal < DL1:
DLn > constitute time delayed signal group, wherein n is not less than 1；First signal SIGA, secondary signal SIGB and n road are postponed signal group defeated
Entering to sampling unit, sampling unit is from the first signal SIGA and postpones to pick out m road signal composition the first input letter signal group
Number group, has been combined sampling processing, and has produced the sampled signal that m road sampled signal<SP1:SPm>is constituted with secondary signal SIGB
Group, wherein m is not more than n but more than 0；By sampled signal group input to decision unit, decision unit is selected from delay signal group
Go out m way signal, be allowed to and m way signal SP1 to SPm one_to_one corresponding in described sampled signal group, and according to sampled signal group
Neutron signal<SP1:SPm>condition selecting goes out 1 tunnel and postpones signal group subsignal as output signal SIGO.
Further, in the present embodiment, the mode of selecting of subsignal is for arbitrarily selecting or being selected by preset rules
Select.
Further, in the present embodiment, make n take 5, namely delay cell creates 5 tunnels and postpones signal, wherein, each
Road signal has different retardations relative to the first signal SIGA, and named<DL1:DL5>, it is preferred that its retardation is gradually
It is incremented by, as shown in Figure 2,3.
Further, in the present embodiment, 5 tunnels delay signals are picked out formation the first input signal by sample circuit
Group, it is possible to select two kinds of working methods:
(1) first kind of way is that the 5 road signals that will be singled out carry out rising edge as sampling clock to secondary signal SIGB and adopt
Sample and produce 5 tunnel sampled signals, order as<SP1:SP5>, its process is as shown in Figure 2；
(2) second way is adopted for secondary signal SIGB is carried out rising edge as sampling clock to select 5 road signals
Sample and produce 5 tunnel sampled signals, order as<SP1:SP5>, its process is as shown in Figure 3.
Further, in the present embodiment, decision unit makes decisions process according to sampled signal<SP1:SP5>, when sentencing
Certainly unit finds when in<SP1:SP5>, the voltage status of arbitrary neighborhood two-way sampled signal is contrary, then trigger producing decision operation；
Decision unit selects a road sampled signal as criterion signal from the different adjacent two-way sampled signal of voltage status, will be with this road
Described delay signal corresponding to described sampled signal is as output signal SIGO, and keeps this mapping relations, until next time
Decision process occurs.
Further, in the present embodiment, if desired realize the rising edge to secondary signal SIGB to follow the trail of and sampling unit
Using each subsignal in the first input signal group as sampling clock, then Wei low level when adjacent two-way sampled signal voltage status
During with high level, trigger and produce criterion operation.If desired realize the tracking of the rising edge to secondary signal SIGB and sampling unit will
Secondary signal SIGB as sampling clock, then when adjacent two-way sampled signal voltage status not Wei high level and during low level, touch
Send out and produce criterion operation.
Further, in the present embodiment, if desired realize the rising edge to secondary signal SIGB to follow the trail of and sampling unit
Use the 5 road signals picked out as sampling clock secondary signal SIGB to do rising edge sampling, and produce sampled signal < SP1:
SP5>, and by<SP1:SP5>and<DL1:DL5>one_to_one corresponding；Assuming that adjacent two-way sampled signal SP3 and SP4 voltage status phase
Instead, wherein SP3 is low-voltage and SP4 is high voltage, then decision unit is using SP4 as decision signal, and is prolonged by corresponding with SP4
Signal DL4 maps and produces output signal SIGO late, and whole process is as shown in Figure 2.
Further, in the present embodiment, if desired realize the rising edge to secondary signal SIGB to follow the trail of and sampling unit
Use secondary signal SIGB as sampling clock the 5 road signals picked out to do rising edge sampling, and produce sampled signal < SP1:
SP5>, and by<SP1:SP5>and<DL1:DL5>one_to_one corresponding；Assuming that adjacent two-way sampled signal SP3 and SP4 voltage status phase
Instead, wherein SP3 is high voltage and SP4 is low-voltage, then decision unit is using SP4 as decision signal, and is prolonged by corresponding with SP4
Signal DL4 maps and produces output signal SIGO late, and whole process is as shown in Figure 3.
Further, in another embodiment, sample circuit the first input signal SIGA and 4 tunnels are postponed signal < SP1:
SP4 > pick out formation the first input signal group, and sampling unit uses secondary signal SIGB as sampling clock to selecting
The 5 road signals gone out do rising edge sampling and produce sampled signal<SP1:SP5>；Decision unit is by<SP1:SP5>and<DL1:DL5>
One is corresponding, and supposes that adjacent two-way sampled signal SP4 and SP5 voltage status are contrary, and wherein SP4 is high voltage and SP5 is low
Voltage, then decision unit is using SP5 as decision signal, and is mapped by the delay signal DL5 corresponding with SP5 and produces output signal
SIGO, whole process is as shown in Figure 4.
Being above presently preferred embodiments of the present invention, all changes made according to technical solution of the present invention, produced function is made
With during without departing from the scope of technical solution of the present invention, belong to protection scope of the present invention.
Claims (8)
1. one kind can realize fast signal follow the tracks of method, it is characterised in that including: a delay cell, a sampling unit and
One decision unit, realizes in accordance with the following steps:
Step S1: described delay unit carries out delay process to the first signal SIGA, produces and postpones signal group, described delay signal
Group is made up of the n way signal of DL1 to DLn, and inputs described first signal SIGA and described delay signal group to described
Sampling unit, wherein, n is the integer not less than 1；
Step S2: described sampling unit will pick out m road signal structure from described first signal SIGA and described delay signal group
Become the first input signal group, in conjunction with described first input signal group and described secondary signal SIGB, carry out sampling processing, and produce
Sampled signal group, described sampled signal group is made up of the m way signal of SP1 to SPm, and wherein, m is the positive integer of no more than n；
Step S3: described decision unit receives described delay signal group and described sampled signal group respectively, and from described delay
Signal group is picked out m way signal, is allowed to and m way signal SP1 to SPm one_to_one corresponding in described sampled signal group；
Step S4: the state of each subsignal in described sampled signal group is monitored by described decision unit according to decision rule,
When described sampled signal group neutron signal meets decision rule, by from the described sampled signal group subsignal meeting decision rule
In pick out 1 way signal and as decision signal and trigger generation decision operation, the corresponding relation determined according to step S3, by institute
State the described delay signal group subsignal corresponding to decision signal as output signal SIGO and to maintain to adjudicating generation next time.
A kind of method realizing fast signal tracking the most according to claim 1, it is characterised in that in described step S1
In, the subsignal DL1 to DLn in described delay signal group differs the first retardation extremely respectively relative to described first signal SIGA
N-th retardation, and described first retardation is incremented by order to described n-th retardation.
A kind of method realizing fast signal tracking the most according to claim 1, it is characterised in that in described step S2
In, described sampling unit using described secondary signal SIGB as sampling clock, respectively to each son in described first input signal group
Signal is sampled, and generates described sampled signal group.
A kind of method realizing fast signal tracking the most according to claim 3, it is characterised in that in described step S4
In, described decision unit detects the voltage status of each subsignal in described sampled signal group respectively, and when arbitrary neighborhood two-way institute
State sampled signal group subsignal voltage status contrary time, trigger produce decision operation.
A kind of method realizing fast signal tracking the most according to claim 4, it is characterised in that when to described second
The rising edge of signal SIGB is followed the trail of, when described adjacent two-way sampled signal group subsignal voltage status difference in the most described step S4
During for high level and low level, trigger and produce the operation of described criterion.
A kind of method realizing fast signal tracking the most according to claim 1, it is characterised in that in described step S2
In, described sampling unit will use in described first input signal group that each subsignal is respectively as sampling clock, to described second
Signal SIGB samples, and generates described sampled signal group.
A kind of method realizing fast signal tracking the most according to claim 6, it is characterised in that in described step S4
In, described decision unit detects the voltage status of each subsignal in described sampled signal group respectively, and when arbitrary neighborhood two-way institute
State sampled signal group subsignal voltage status contrary time, trigger produce decision operation.
A kind of method realizing fast signal tracking the most according to claim 7, it is characterised in that when to described second
The rising edge of signal SIGB is followed the trail of, the lowest when described adjacent two-way sampling group's subsignal voltage status in the most described step S4
When level and high level, trigger and produce the operation of described criterion.
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| CN201610275107.6A CN105978541B (en) | 2016-04-28 | 2016-04-28 | A kind of method of achievable fast signal tracking |
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| CN201610275107.6A CN105978541B (en) | 2016-04-28 | 2016-04-28 | A kind of method of achievable fast signal tracking |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773852A (en) * | 2004-11-12 | 2006-05-17 | 三洋电机株式会社 | Trap filter |
| CN101465632A (en) * | 2007-12-21 | 2009-06-24 | 瑞昱半导体股份有限公司 | Sampling circuit and sampling method |
| CN101997543A (en) * | 2010-11-30 | 2011-03-30 | 四川和芯微电子股份有限公司 | Frequency discriminator and method for realizing frequency discrimination |
| CN102870386A (en) * | 2012-06-21 | 2013-01-09 | 华为技术有限公司 | Decision feedback equalizer and receiver |
| CN105471787A (en) * | 2015-11-23 | 2016-04-06 | 硅谷数模半导体（北京）有限公司 | Signal sampling processing method and system thereof |
-
2016
- 2016-04-28 CN CN201610275107.6A patent/CN105978541B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773852A (en) * | 2004-11-12 | 2006-05-17 | 三洋电机株式会社 | Trap filter |
| CN101465632A (en) * | 2007-12-21 | 2009-06-24 | 瑞昱半导体股份有限公司 | Sampling circuit and sampling method |
| CN101997543A (en) * | 2010-11-30 | 2011-03-30 | 四川和芯微电子股份有限公司 | Frequency discriminator and method for realizing frequency discrimination |
| CN102870386A (en) * | 2012-06-21 | 2013-01-09 | 华为技术有限公司 | Decision feedback equalizer and receiver |
| CN105471787A (en) * | 2015-11-23 | 2016-04-06 | 硅谷数模半导体（北京）有限公司 | Signal sampling processing method and system thereof |
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Effective date of registration: 20220905 Address after: Room 2006, 2nd Floor, Building 5, No. 2 Wanhong West Street, Chaoyang District, Beijing 100015 Patentee after: Beijing Digital Optical Core Integrated Circuit Design Co.,Ltd. Address before: 350108 new campus of Fuzhou University, No. 2, Xue Yuan Road, University Town, Minhou street, Minhou, Fujian. Patentee before: FUZHOU University |
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