CN105977305A - Thin-film transistor and preparation method thereof, array substrate and display panel - Google Patents
Thin-film transistor and preparation method thereof, array substrate and display panel Download PDFInfo
- Publication number
- CN105977305A CN105977305A CN201610439706.7A CN201610439706A CN105977305A CN 105977305 A CN105977305 A CN 105977305A CN 201610439706 A CN201610439706 A CN 201610439706A CN 105977305 A CN105977305 A CN 105977305A
- Authority
- CN
- China
- Prior art keywords
- grid
- source
- film transistor
- drain electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 title 1
- 238000009413 insulation Methods 0.000 claims description 26
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 8
- 239000012212 insulator Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a thin-film transistor, which comprises a grid, a gate insulator layer, a source and a drain, an active region and an auxiliary connection layer, wherein positive projections of the source and the drain in the plane in which the grid is located are separated from the grid; the active region and the grid are oppositely arranged; the size of the grid on a connection line of the source and the drain is not smaller than that of the active region on the connection line; and the auxiliary connection layer connects the active region and the source and the drain. By the thin-film transistor, the capacitance between the grid and the source and the drain can be eliminated.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of thin film transistor (TFT) and system thereof
Preparation Method, array base palte, display floater.
Background technology
Referring to Fig. 1, Fig. 1 is that ESL TFT (has the film crystal of etching barrier layer
Pipe) structural representation, the technological process of this ESL TFT generally: grid (Gate)
→ gate insulation layer (GI) → active layer Active (for IGZO) → etching barrier layer (ESL)
→ source-drain electrode (SD layer) → passivation layer (PVX).When ESL TFT applies,
After Gate upper loading high-voltage signal, by electric field at one layer of electronics of IGZO surface formation,
At this moment i.e. electron channel, if having voltage difference, then between source S ource and drain D rain
Source-drain electrode turns on, and the two has electric current (electronics) and flows through, namely TFT opens；By Gate
After the high-voltage signal of upper loading removes, electric field disappears, therefore, and the electronics ditch on IGZO
Road disappears, and at this moment source-drain electrode does not turns on, namely TFT turns off.In actual applications, for
Guarantee Gate to enable on IGZO and form electron channel, the area one of general Gate
As relatively big, as it is shown in figure 1, in this case, other problem: Gate will be produced
And form electric capacity C between source electrode or drain electrodep。
In the 3T1C circuit of AMOLED as shown in Figure 2, T2 write GTG letter
Turn off after number Vdata, then the data voltage of write will be by the shadow of signal
Ring, such as, work as G1=VghTime, T2 opens, and Vdata is written to G point；Work as G1=Vgl
Time, T2 turns off, and Vdata Hold is at CstIn, but due to CpExistence, the Data of write
Voltage can be pulled low, and variable quantity calculates according to equation below:
Similarly, it is similar that Vc write and the T2 that T3 controls controls Vdata write, writes
The voltage that enters is also due to electric capacity CpEffect be pulled low, therefore, in order to ensure this
The voltage dragged down is less not affect display, accordingly, it would be desirable to by CstDesign is relatively big, so
It is likely to result in CstArea increases, thus reduces aperture opening ratio or use more complicated electric capacity
Structure, causes yield relatively low.
Therefore, need a kind of reduction at present badly and even eliminate electric capacity CpThin film transistor (TFT).
Summary of the invention
The technical problem to be solved be for present in prior art above-mentioned not
Foot, it is provided that a kind of thin film transistor (TFT) and preparation method thereof, array base palte, display floater.
For solving at least one technical problem that the present invention proposes, the invention provides one
Thin film transistor (TFT), including grid, gate insulation layer, source-drain electrode and active area；Also include auxiliary
Help articulamentum；Described source-drain electrode described grid orthographic projection in the plane and described grid
Pole separates；Described active area is oppositely arranged with described grid, and described grid is in described source
Size on drain bond wires is not less than described active area size on this connecting line；Institute
State auxiliary connection layer and connect described active area and described source-drain electrode.
Preferably, described active area described grid orthographic projection in the plane with described
Grid is completely overlapped.
Preferably, described gate insulation layer is formed on described grid；Described active area is formed
On described gate insulation layer；Described auxiliary connection layer is formed on described gate insulation layer；Institute
State source-drain electrode to be formed on described auxiliary connection layer.
Preferably, described thin film transistor (TFT) also includes etching barrier layer；Described etch stopper
Layer is formed on described active layer and described auxiliary connection layer, and is provided with via；
Described source-drain electrode is formed on etching barrier layer, and by described via with described auxiliary even
Connect layer to be connected.
Preferably, described thin film transistor (TFT) also includes passivation layer；Described passivation layer is formed at
On described source-drain electrode and the described etching barrier layer that do not covered by described source-drain electrode.
The present invention also provides for a kind of array base palte, and including thin film transistor (TFT), described thin film is brilliant
Body pipe includes the thin film transistor (TFT) that the present invention provides.
The present invention also provides for a kind of display floater, including array base palte, described array base palte
Use the array base palte that the present invention provides.
The present invention also provides for the preparation method of a kind of thin film transistor (TFT), including: S1, formed
Grid, gate insulation layer, source-drain electrode, active area and auxiliary connection layer, and make source-drain electrode exist
Described grid orthographic projection in the plane separate with described grid, described active area and institute
State grid to be oppositely arranged, and the size that described grid is on described source-drain electrode connecting line is the least
In described active area size on this connecting line, described auxiliary connection layer connect described in have
Source region and described source-drain electrode.
Preferably, described step S1, also include: described active area is at described grid place
Orthographic projection in plane is completely overlapped with described grid.
Preferably, described step S1, including: form described grid；On described grid
Form described gate insulation layer；Described gate insulation layer is formed described active area；Described
Described auxiliary connection layer is formed on gate insulation layer；Described auxiliary connection layer is formed described
Source-drain electrode.
The thin film transistor (TFT) that the present invention provides, by source-drain electrode at grid in the plane
Orthographic projection separates with grid, and now, grid is the most relative with source-drain electrode, therefore, and will not
Produce electric capacity Cp；It addition, in order to ensure that thin film transistor (TFT) can normally work, by grid
Pole size on source-drain electrode connecting line is not less than active area size on this connecting line, this
Sample, it is ensured that active area can be formed as turning on district when grid loads useful signal, and
Realize source-drain electrode by auxiliary connection layer to connect, thus realize ensureing thin film transistor (TFT) TFT
Normal work.
Accompanying drawing explanation
Fig. 1 is the structural representation of ESL TFT；
Fig. 2 is the 3T1C circuit diagram of AMOLED；
The structural representation of the thin film transistor (TFT) that Fig. 3 provides for the embodiment of the present invention；
The top view of the thin film transistor (TFT) that Fig. 4 provides for the embodiment of the present invention；
The preparation method of the thin film transistor (TFT) that Fig. 5 a-Fig. 5 h provides for the embodiment of the present invention
The state diagram of each step.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, knot below
Close thin film transistor (TFT) and preparation side thereof that the present invention is provided by the drawings and specific embodiments
Method, array base palte, display floater are described in further detail.
Embodiment 1:
The structural representation of the thin film transistor (TFT) that Fig. 3 provides for the embodiment of the present invention；Fig. 4
Top view for the thin film transistor (TFT) that the embodiment of the present invention provides；See also Fig. 3 and
Fig. 4, the present embodiment provide thin film transistor (TFT), including grid G ate, gate insulation layer GI,
Source-drain electrode SD, active area Active (can be but be not limited to IGZO), auxiliary connect
Layer 10, etching barrier layer ESL and passivation layer PVX.
Wherein, source-drain electrode SD grid G ate orthographic projection in the plane and grid G ate
Separate, that is, source-drain electrode SD grid G ate orthographic projection in the plane not with this
Grid G ate is overlapping.Active area IGZO is oppositely arranged with grid G ate, grid G ate
Dimension D 1 on source-drain electrode SD connecting line is not less than active area IGZO at this connecting line
On dimension D 2；Auxiliary connection layer 10 connects active area IGZO and source-drain electrode SD.
Please comparison diagram 1 and Fig. 3, the embodiment of the present invention provide thin film transistor (TFT) with existing
Thin film transistor (TFT) compare, in order to realize source-drain electrode SD grid G ate institute in the plane
Orthographic projection separate with grid G ate, reduce the size of grid G ate, now, grid
Gate is the most relative with source-drain electrode SD, therefore, will not produce electric capacity Cp。
But, in the case of reducing grid G ate size, in order to ensure thin film transistor (TFT)
Can normally work, need grid G ate dimension D 1 on source-drain electrode SD connecting line
Not less than active area IGZO dimension D 2 on this connecting line, so, it is ensured that at grid
When Gate loads useful signal, active area IGZO can be formed as turning on district, and by auxiliary
Help articulamentum 10 to realize source-drain electrode SD connection, thus realize ensureing the normal work of TFT.
Preferably, active area IGZO grid G ate orthographic projection in the plane and grid
Pole Gate is completely overlapped, i.e., in Fig. 4, D1=D2, L1=L2, as such, it is possible to enter one
Step ensures that thin film transistor (TFT) normally works.
As it is shown on figure 3, gate insulation layer GI is formed in grid G ate；Active area IGZO
It is formed on gate insulation layer GI and is positioned at the surface of grid G ate；Auxiliary connection layer 10
It is formed on gate insulation layer GI；Source-drain electrode SD is formed on auxiliary connection layer 10.
Preferably, etching barrier layer ESL is formed on active layer and auxiliary connection layer 10,
And it is provided with via；Source-drain electrode SD is formed on etching barrier layer ESL, and logical
Cross this via to be connected with described auxiliary connection layer 10.
It is further preferred that passivation layer PVX is formed at source-drain electrode SD and not by source-drain electrode SD
On the etching barrier layer ESL covered.
Needing described herein, the thin film transistor (TFT) that the present embodiment provides is for comprising etching
The thin film transistor (TFT) of barrier layer ESL, but, the invention is not limited in this, if energy
Enough meet that " source-drain electrode SD is in the orthographic projection in the plane of grid G ate institute and grid G ate
Separating, active area IGZO is oppositely arranged with grid G ate, and grid G ate is at source-drain electrode
Dimension D 1 on SD connecting line is not less than active area IGZO dimension D 2 on this connecting line；
Auxiliary connection layer 10 connects active area IGZO and source-drain electrode SD " thin film transistor (TFT) equal
Belong to protection scope of the present invention.
Embodiment 2:
The embodiment of the present invention provides a kind of array base palte, and including thin film transistor (TFT), thin film is brilliant
Body pipe uses the thin film transistor (TFT) that the present invention provides.
The array base palte that the embodiment of the present invention provides, owing to it uses the above-mentioned enforcement of the present invention
The thin film transistor (TFT) that example provides, it is thus possible to improve the quality of array base palte.
Embodiment 3:
The embodiment of the present invention also provides for a kind of display floater, including array base palte, array base
Plate uses the array base palte that the present invention provides.
Specifically, display floater includes display panels, oled panel etc..
The display floater that the embodiment of the present invention provides, owing to it uses the above-mentioned enforcement of the present invention
The array base palte that example provides, it is thus possible to improve the quality of display floater.
Embodiment 3:
The embodiment of the present invention additionally provides the preparation method of a kind of thin film transistor (TFT), including:
S1, forms grid G ate, gate insulation layer GI, source-drain electrode SD, active area Active
(can be but be not limited to IGZO) and auxiliary connection layer 10, and make source-drain electrode SD in institute
State grid G ate orthographic projection in the plane separate with described grid G ate, active area
IGZO is oppositely arranged with grid G ate, and grid G ate is on source-drain electrode SD connecting line
Size is not less than active area IGZO size on this connecting line, described auxiliary connection layer
10 connect described active area IGZO and described source-drain electrode SD.
Preferably, this step S1, also include: make active area IGZO in grid G ate
Orthographic projection in the plane completely overlapped with grid G ate.
The thin film crystalline substance that the embodiment of the present invention provides is described in detail below in conjunction with Fig. 5 a and Fig. 5 h
The preparation method of body pipe.Specifically, above-mentioned steps S1 includes:
S11, forms grid G ate, as shown in Figure 5 a.
S12, forms gate insulation layer GI, as shown in Figure 5 b in grid G ate.
S13, is formed with source region IGZO on gate insulation layer GI.
S14, forms auxiliary connection layer 10 on gate insulation layer GI.
Step S13 and step S14, particularly as follows: first deposit one layer on gate insulation layer GI
Active layer, as shown in Figure 5 c；Mask plate based on grid G ate is in grid G ate just again
Top forms a photoresist PR, then uses the means such as such as plasma hydrogenation to not by light
The active layer that photoresist PR covers processes, as fig 5d；Result after process
As depicted in fig. 5e, the active layer not being photo-etched glue PR covering is treated to auxiliary connection layer
10。
S15, forms source-drain electrode SD on auxiliary connection layer 10.
Preferably, step S15 includes: at auxiliary connection layer 10 and active area IGZO
Top forms etching barrier layer ESL, and the etching barrier layer on auxiliary connection layer 10
Via is formed, as shown in figure 5f on ESL；Etching barrier layer ESL is formed source-drain electrode
SD, and make source-drain electrode SD electrically connect with auxiliary connection layer 10 through via, such as Fig. 5 g
Shown in.
It is further preferred that the most also include: at source-drain electrode SD and not
Passivation layer PVX is formed, such as Fig. 5 h on the etching barrier layer ESL covered by source-drain electrode SD
Shown in.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present
And the illustrative embodiments used, but the invention is not limited in this.For ability
For those of ordinary skill in territory, in the situation without departing from spirit and substance of the present invention
Under, various modification and improvement can be made, these modification and improvement are also considered as the present invention's
Protection domain.
Claims (10)
1. a thin film transistor (TFT), including grid, gate insulation layer, source-drain electrode and active area；
It is characterized in that, also include auxiliary connection layer；
Described source-drain electrode described grid orthographic projection in the plane divide with described grid
From；
Described active area is oppositely arranged with described grid, and described grid is at described source-drain electrode
Size on connecting line is not less than described active area size on this connecting line；
Described auxiliary connection layer connects described active area and described source-drain electrode.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described in have
Source region described grid orthographic projection in the plane completely overlapped with described grid.
Thin film transistor (TFT) the most according to claim 1 and 2, it is characterised in that institute
State gate insulation layer to be formed on described grid；
Described active area is formed on described gate insulation layer；
Described auxiliary connection layer is formed on described gate insulation layer；
Described source-drain electrode is formed on described auxiliary connection layer.
Thin film transistor (TFT) the most according to claim 3, it is characterised in that described thin
Film transistor also includes etching barrier layer；
Described etching barrier layer is formed on described active layer and described auxiliary connection layer, and
It is provided with via；
Described source-drain electrode is formed on etching barrier layer, and auxiliary with described by described via
Articulamentum is helped to be connected.
Thin film transistor (TFT) the most according to claim 4, it is characterised in that described thin
Film transistor also includes passivation layer；
Described passivation layer is formed at described source-drain electrode and described in not covered by described source-drain electrode
On etching barrier layer.
6. an array base palte, including thin film transistor (TFT), it is characterised in that described thin film
Transistor uses the thin film transistor (TFT) described in claim 1-5 any one.
7. a display floater, including array base palte, it is characterised in that described array base
Plate uses the array base palte described in claim 6.
8. the preparation method of a thin film transistor (TFT), it is characterised in that including:
S1, forms grid, gate insulation layer, source-drain electrode, active area and auxiliary connection layer,
And make source-drain electrode described grid orthographic projection in the plane separate with described grid, institute
State active area and described grid is oppositely arranged, and described grid is at described source-drain electrode connecting line
On size not less than described active area size on this connecting line, described auxiliary connects
Layer connects described active area and described source-drain electrode.
The preparation method of thin film transistor (TFT) the most according to claim 8, its feature exists
In, described step S1, also include: described active area at described grid in the plane
Orthographic projection is completely overlapped with described grid.
The preparation method of thin film transistor (TFT) the most according to claim 8 or claim 9, its
It is characterised by, described step S1, including:
Form described grid；
Described grid is formed described gate insulation layer；
Described gate insulation layer is formed described active area；
Described gate insulation layer is formed described auxiliary connection layer；
Described auxiliary connection layer is formed described source-drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610439706.7A CN105977305A (en) | 2016-06-17 | 2016-06-17 | Thin-film transistor and preparation method thereof, array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610439706.7A CN105977305A (en) | 2016-06-17 | 2016-06-17 | Thin-film transistor and preparation method thereof, array substrate and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105977305A true CN105977305A (en) | 2016-09-28 |
Family
ID=57021904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610439706.7A Pending CN105977305A (en) | 2016-06-17 | 2016-06-17 | Thin-film transistor and preparation method thereof, array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105977305A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430380A (en) * | 2020-04-14 | 2020-07-17 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090242895A1 (en) * | 2008-03-27 | 2009-10-01 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same |
| CN103489881A (en) * | 2011-12-31 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method of thin film transistor array substrate as well as display device |
| CN103715267A (en) * | 2013-12-30 | 2014-04-09 | 京东方科技集团股份有限公司 | TFT, TFT array substrate, manufacturing method of TFT array substrate and display device |
| EP2869329A1 (en) * | 2012-06-29 | 2015-05-06 | Boe Technology Group Co. Ltd. | Thin-film transistor, array substrate and manufacturing method therefor |
-
2016
- 2016-06-17 CN CN201610439706.7A patent/CN105977305A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090242895A1 (en) * | 2008-03-27 | 2009-10-01 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same |
| CN103489881A (en) * | 2011-12-31 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method of thin film transistor array substrate as well as display device |
| EP2869329A1 (en) * | 2012-06-29 | 2015-05-06 | Boe Technology Group Co. Ltd. | Thin-film transistor, array substrate and manufacturing method therefor |
| CN103715267A (en) * | 2013-12-30 | 2014-04-09 | 京东方科技集团股份有限公司 | TFT, TFT array substrate, manufacturing method of TFT array substrate and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430380A (en) * | 2020-04-14 | 2020-07-17 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10672849B2 (en) | Organic light emitting display device comprising multi-type thin film transistor | |
| CN104681567B (en) | Thin film transistor base plate and its manufacture method with metal-oxide semiconductor (MOS) | |
| CN102096259B (en) | Active matrix substrate, liquid crystal panel, display, television receiver | |
| US9470946B2 (en) | TFT-LCD array substrate pixel electrode connected to first and second capacitors | |
| US9653484B2 (en) | Array substrate and manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof | |
| CN105161503B (en) | Amorphous silicon semiconductor TFT backplate structure | |
| EP3174098B1 (en) | Thin film transistor substrate for organic light emitting diode display | |
| CN104600030B (en) | Array base palte and preparation method thereof, display device | |
| CN106206430B (en) | Manufacturing method of thin film transistor structure | |
| US20240282863A1 (en) | Thin-film transistor and display device including the same | |
| US10338446B2 (en) | Semiconductor device having low resistance source and drain regions | |
| CN104393000A (en) | Array substrate, manufacturing method thereof and display device | |
| CN107068694B (en) | Semiconductor device structure and preparation method thereof, array substrate and display device | |
| US9825058B2 (en) | Oxide semiconductor transistor used as pixel element of display device and manufacturing method therefor | |
| CN109459894A (en) | Pixel electrode structure and preparation method thereof | |
| CN108231595A (en) | Thin film transistor (TFT) and preparation method thereof, array substrate, display device | |
| CN106020545A (en) | Array substrate, preparation method thereof, and touch screen | |
| US20160155736A1 (en) | Liquid crystal display device and manufacturing method thereof | |
| CN106020544B (en) | A kind of touch-control display panel and preparation method thereof, touch control display apparatus | |
| WO2017156885A1 (en) | Thin film transistor, array substrate and manufacturing and driving method thereof, and display device | |
| CN106019735A (en) | Display panel, display device and control method of display panel | |
| JP6541803B2 (en) | Thin film transistor and method of manufacturing the same | |
| WO2016188062A1 (en) | Array substrate, liquid crystal display panel and liquid crystal display device | |
| CN105977305A (en) | Thin-film transistor and preparation method thereof, array substrate and display panel | |
| CN107623008A (en) | Display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160928 |
|
| RJ01 | Rejection of invention patent application after publication |