CN105977200B - Forming method with small line spacing and small end-end interval semiconductor device structure - Google Patents

Forming method with small line spacing and small end-end interval semiconductor device structure Download PDF

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Publication number
CN105977200B
CN105977200B CN201510824222.XA CN201510824222A CN105977200B CN 105977200 B CN105977200 B CN 105977200B CN 201510824222 A CN201510824222 A CN 201510824222A CN 105977200 B CN105977200 B CN 105977200B
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layer
patterned
middle layer
top layer
semiconductor device
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CN105977200A (en
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陈宏豪
陈玉树
刘又诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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Abstract

The embodiment of the present invention provides a kind of method for being used to form semiconductor device structure.Method includes providing substrate and bottom, middle layer and top layer being formed on the substrate.Method further include: patterned top layer, to form patterned top layer, and by the Patternized technique including plasma process come patterned intermediate layer, to form patterned middle layer.By using including hydrogen (H2) mixed gas execute plasma process.Method further include: control hydrogen (H2) flow, to improve middle layer for the etching selectivity of top layer, and patterned middle layer includes first part and the second part parallel with first part, and the spacing between first part and second part.The embodiment of the present invention further relates to the forming method with small line spacing and small end-end interval semiconductor device structure.

Description

Forming method with small line spacing and small end-end interval semiconductor device structure
The cross reference of related application
This application claims entitled " the Method for forming submitted on March 12nd, 2015 Semiconductor device structure with fine line pitch and fine end-to-end The priority of the 62/132nd, No. 128 U.S. Provisional Application of space ", entire contents are hereby expressly incorporated by reference.
Technical field
The present invention relates to the forming methods with small line spacing and small end-end interval semiconductor device structure.
Background technique
Semiconductor devices is used for a variety of electronic applications, and such as personal computer, mobile phone, digital camera and other electronics are set It is standby.Usually by following steps come manufacturing semiconductor devices: square sequential deposition insulation or dielectric layer, conduction on a semiconductor substrate Layer and semiconductor material layer；And multiple material layer is patterned using photoetching, to form circuit in multiple material layer Component and element.Many integrated circuits are usually manufactured on single semiconductor crystal wafer, and by integrating electricity along scribing line The individual tube core on wafer is divided in sawing between road.For example, usually being incited somebody to action with multi-chip module or with other encapsulated types Individual tube core encapsulates respectively.
In order to increase device density, constantly reduce the size of semiconductor devices in a manufacturing process.It thus provides multilayer Interconnection structure.Interconnection structure may include one or more conducting wires and via layer.
Although existing interconnection structure and manufacture interconnection structure method generally for they expected purpose it is enough, But they are not all to fully meet requirement in all respects.
Summary of the invention
In order to solve the problems in the prior art, according to some embodiments of the present invention, it provides one kind and is used to form half The method of conductor device structure, comprising: receive substrate；Bottom, middle layer and top layer are formed over the substrate；Described in patterning Top layer, to form patterned top layer；The middle layer is patterned by including the Patternized technique of plasma process, with Form patterned middle layer, wherein by using including hydrogen (H2) mixed gas execute the plasma process； And control hydrogen (H2) flow, to improve the middle layer for the etching selectivity of the top layer, wherein the pattern The middle layer of change includes first part and the second part parallel with the first part, and between the first part with it is described Spacing between second part.
Other embodiments according to the present invention provide a kind of method for being used to form semiconductor device structure, comprising: Receive substrate；Dielectric layer is formed over the substrate；Hard mask layer is formed on the dielectric layer；The shape on the hard mask layer At bottom, middle layer and top layer；The top layer is patterned, to form patterned top layer；By including plasma process Patternized technique patterns the middle layer, to form patterned middle layer, wherein by using including hydrogen (H2) Mixed gas executes the plasma process；The bottom is patterned, to form patterned bottom；And by using The patterned top layer, the patterned middle layer and the patterned bottom are patterned as mask described to be covered firmly Mold layer, to form patterned hard mask layer.
Other embodiment according to the present invention provides a kind of method for being used to form semiconductor device structure, comprising: Receive substrate；Dielectric layer is formed over the substrate；Hard mask layer is formed on the dielectric layer；The shape on the hard mask layer At bottom, middle layer and top layer, wherein the middle layer is made of silicon-containing compound；The top layer is patterned, to form pattern The top layer of change；Plasma process is executed to the top layer, to improve the line width roughness (LWR) of the top layer, wherein described Plasma process includes using including hydrogen (H2) mixed gas；The plasma work is continuously performed to the middle layer Skill, to form protective film on the side wall of the top layer and the side wall of the middle layer；The middle layer is continuously performed described Plasma process, to remove a part of the middle layer, to form patterned middle layer；The bottom is patterned, To form patterned bottom；By using the patterned top layer, the patterned middle layer and described patterned Bottom patterns the hard mask layer as mask, to form patterned hard mask layer.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, each side that the present invention may be better understood according to the following detailed description Face.It should be noted that according to the standard practices in industry, various parts are not drawn to scale.In fact, in order to clearly beg for By the size of various parts can be arbitrarily increased or reduce.
Figure 1A to Fig. 1 L shows the semiconductor devices that formation according to some embodiments of the present invention has interconnection structure The sectional view in each stage of structure.
Figure 1B ' shows the diagram of the amplification of the region A of Figure 1B according to some embodiments of the present invention.
Fig. 1 D' shows the diagram of the amplification of the region B of Fig. 1 D according to some embodiments of the present invention.
Fig. 1 L' shows the perspective view of semiconductor device structure according to some embodiments of the present invention.
Fig. 2 shows the diagrams of the relationship of the flow of the second spacing and hydrogen according to some embodiments of the present invention.
Specific embodiment
Following disclosure provides many different embodiments or examples, for realizing the different characteristic of provided theme. The particular instance of component explained below and arrangement is to simplify the present invention.Certainly, these are only examples and are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that part directly contacts also may include that the additional component being formed between the first component and second component makes first The embodiment that part and second component are not directly contacted with.In addition, the present invention can in multiple examples repeat reference numerals and/or word Symbol.This repetition is for purposes of simplicity and clarity, and itself not indicate each embodiment discussed and/or configuration Between relationship.
Describe some variations of embodiment.In multiple diagrams in the whole text and the embodiment shown, similar reference number Word is for indicating similar element.It should be understood that can before the process per se, during and after additional operation is provided, and For other embodiments of this method, described some operations can be replaced or removed.
A kind of embodiment being used to form the semiconductor structure with interconnection structure is provided.Interconnection structure includes being formed in Jie Several metalization layers (such as metal intermetallic dielectric layer, IMD) in electric layer.A kind of technique for being used to form interconnection structure is bed setter Skill.Figure 1A to Fig. 1 L shows the semiconductor device structure that formation according to some embodiments of the present invention has interconnection structure The sectional view in 100 each stage.Figure 1A to Fig. 1 L shows the first groove (trench- for being used to form dual-damascene structure First) technique.
A referring to Fig.1, semiconductor device structure 100 include substrate 102.Substrate 102 can be by silicon or other semiconductor materials It is made.Alternatively, or in addition, substrate 102 may include the other elements semiconductor material of such as germanium.In some embodiments, Substrate 102 is made of the compound semiconductor of such as silicon carbide, GaAs, indium arsenide or indium phosphide.In some embodiments, it serves as a contrast Bottom 102 is made of the alloy semiconductor of such as SiGe, silicon germanium carbide, gallium arsenide phosphide or phosphorus indium gallium.In some embodiments, it serves as a contrast Bottom 102 includes epitaxial layer.For example, substrate 102 has the epitaxial layer being located above bulk semiconductor.
Some components (not shown) are formed in substrate 102.The components include transistor (for example, metal oxygen Compound semiconductor field effect transistor (MOSFET), complementary metal oxide semiconductor (CMOS) transistor, bipolar junction transistor Manage (BJT), high voltage transistor, high frequency transistor, p-channel and/or n-channel field effect transistor (PFET/NFET) etc.), two poles Pipe, and/or other applicable elements.Multiple techniques are executed to form the components, such as deposition, etching, injection, photoetching, Annealing and/or other applicable techniques.In some embodiments, it is formed in substrate 102 in front-end process (FEOL) technique Components.
Substrate 102 may include multiple doped regions, such as p-type trap or N-shaped trap.Doped region can be mixed doped with p-type Miscellaneous dose of (such as boron or BF2) and/or n-type dopant (such as phosphorus (P) or arsenic (As)).It can be directly on substrate 102, in p-well In structure, doped region is formed in N well structure or in Dual Well Structure.
Substrate 102 can also include isolated part (not shown), such as local oxygen of shallow trench isolation (STI) component or silicon Change (LOCOS) component.Isolated part can limit and be isolated multiple components.
As shown in figure 1A, the first dielectric layer 106 (such as metal intermetallic dielectric layer, IMD) is formed on substrate 102, And the first conductive component 104 is embedded in the first dielectric layer 106.The first dielectric layer is formed in back-end process (BEOL) technique 106 and first conductive component 104.
First dielectric layer 106 can be single-layer or multi-layer.First dielectric layer 106 is by silica (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON) or the dielectric material with low-k (low k) are made.In some embodiments, first Dielectric layer 106 is by having extremely low k (ELK) dielectric material of the dielectric constant (k) lower than 2.5 to be made.In some embodiments, ELK dielectric material includes silica, noncrystal carbon fluoride, Parylene, the benzocyclobutene (BCB), polytetrafluoro of doped carbon Ethylene (PTFE) (Teflon) or silicon oxide carbide polymer (SiOC).In some embodiments, ELK dielectric material includes porous The existing dielectric material of formula, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK or porous silica (SiO2).In some embodiments, pass through the chemical vapor deposition of plasma enhancing Product (PECVD) technique passes through spin coating proceeding dielectric layer 106.
In some embodiments, the first conductive component 104 is by copper (Cu), copper alloy, aluminium (Al), aluminium alloy, tungsten (W), tungsten Alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy are made.In some embodiments, the first conduction is formed by method for plating Component 104.
The first etching stopping layer 110 is formed on the first dielectric layer 106.Etching stopping layer 110 can be single-layer or multi-layer. First etching stopping layer 110 is by silica (SiOx), silicon carbide (SiC), silicon nitride (SixNy), carbonitride of silicium (SiCN), carbon oxygen SiClx (SiOC), silicon oxide carbide nitride (SiOCN) or other applicable materials are made.In some embodiments, the first etching Stop-layer 110 has double-layer structure, and including forming silica (SiOx) layer on the sic layer, and silicon oxide layer is by orthosilicic acid Tetra-ethyl ester (TEOS) formation.SiC layer is used as glue-line to improve the bonding between following layer and silicon oxide layer.
The second dielectric layer 112 is formed on the first etching stopping layer 110.Second dielectric layer 112 can be single-layer or multi-layer.The Two dielectric layers 112 are by silica (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON) or have low-k (low k) Dielectric material is made.In some embodiments, the second dielectric layer 112 is by having the extremely low k of the dielectric constant (k) below about 2.5 (ELK) dielectric material is made.
Second etching stopping layer 114 and hard mask layer 116 are successively formed on the second dielectric layer 112.In some embodiments In, the second etching stopping layer 114 is made of no nitrogen material, such as silicon oxide carbide (SiOC).In some embodiments, hard mask layer 116 are made of metal material, such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN).It will be made of a metallic material Hard mask layer 116 is configured to provide the high etch-selectivity relative to the second dielectric layer 112 during plasma process.
Three layer photoresist structures 120 are formed on hard mask layer 116.Three layer photoresist structures 120 include bottom 124, in Interbed 126 and top layer 128.In some embodiments, bottom 124 is the bottom anti-reflective for reducing reflection during photoetching process Penetrate painting (BARC) layer.In some embodiments, bottom 124 is by such as silicon oxynitride (SiON), the oxide rich in silicon or carbon oxygen The unazotized material of SiClx (SiOC) is made.In some embodiments, middle layer 126 by such as silicon nitride, silicon oxynitride or The silica-base material of silica is made.
Top layer 128 can be positive photoresist layer or negative photo glue-line.In some embodiments, top layer 128 is by poly- (first Base methyl acrylate) (PMMA), poly- (polydimethyl glutarimide) (PMGI), phenolic resin (DNQ/ ester urea formaldehyde) or SU-8 system At.
In some embodiments, the thickness of bottom 124 is in the range of from about 80nm to about 120nm.In some embodiments In, the thickness of middle layer 126 is in the range of from about 25nm to about 45nm.In some embodiments, the thickness of top layer 128 from In the range of about 80nm to about 120nm.
Later, patterned top layer 128 is to form patterned top layer 128.Patterned top layer 128 includes first part 128a, second part 128b, Part III 128c.
Figure 1B ' shows putting for the region A of Figure 1B after patterned top layer 128 according to some embodiments of the present invention Big diagram.
First part 128a is parallel with second part 128b, and second part 128b is parallel with Part III 128c.It is logical It crosses Part IV (not shown) and second part 128b is connected to Part III 128c.Specifically, first part 128a, second 128b and Part III 128c is divided to extend along Y-axis, but Part IV (not shown) extends along X-axis.
With the development of the manufacturing technology for semiconductor devices, the pattern dimension of semiconductor devices is reduced.However, figure Case size is limited by the resolution limit of used photoetching process.In some embodiments, during photoetching process, X-direction On spatial resolution it is different from the spatial resolution in Y-direction.Therefore, because the resolution limit of photoetching process, so phase Interval between adjacent vertical pattern (or horizontal pattern) can be greater than scheduled interval.
In addition, because of the resolution limit of photoetching process, it, can be close to photoresist layer when patterning photoresist layer Turning point or angle some positions at generate some defects (" hot spot (hot spots) " such as shrinks or deform).Some In embodiment, as shown in Figure 1B ', some defects are shown in region a.Once being generated in patterned top layer 128 Defect, then when patterning following layer (such as middle layer 126 or bottom as mask by using patterned top layer 128 Layer 124) when, layer below can also have defect.As a result, patterned top layer 128 and following layer can be deformed or even be broken It is bad.
As shown in Figure 1B, first part 128a with ideal pattern and has well-balanced side wall.Due to photoetching process Resolution limit, so second part 128b with unexpected pattern and have zigzag and/or non-well-balanced side wall. First part 128a has the first width W1, second part 128b is with the second width W2, and the second width W2It is wide less than first Spend W1.Part III 128c also includes the unexpected pattern with zigzag and/or non-well-balanced side wall.Opening 135 is formed Between first part 128a and second part 128b and there is third width W3。
The measurement result of the smoothness of the side wall of line style component when " line width roughness (LWR) " is viewed from above.Such as Shown in Figure 1B ', because second part 128b has non-well-balanced side wall, the LWR of first part 128a is less than second part The LWB of 128b.
" spacing " is defined as the distance from a component to adjacent component.As shown in Figure 1B, the first spacing P1It is defined For from first part 128a to the distance of second part 128b.In some embodiments, the first spacing P1From about 35nm to about In the range of 120nm.
According to some embodiments of the present invention, as shown in Fig. 1 C and Fig. 1 D, after patterned top layer 128, pass through pattern Chemical industry skill carrys out patterned intermediate layer 126.Patternized technique includes photoetching process and etch process.By using the first plasma Technique 15 executes etch process.Photoetching process includes baking, lithographic glue, punching after soft baking, mask registration, exposure, exposure Wash and dry (for example, hard dry).
First plasma process 15 includes using including hydrogen (H2) mixed gas.In addition to hydrogen (H2) except, mixing Gas can also include fluoro-gas, inert gas, nitrogen (N2) or other applicable gases.In some embodiments, fluorine-containing Gas includes Nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), perfluoroethane (C2F6), tetrafluoromethane (CF4), fluoroform (CHF3), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8) or octafluoroisobutene (C4F8), fluorine gas (F2).In some other embodiments, inert gas includes argon gas (Ar) or helium (He).
During the first plasma process 15, hydrogen is supplied to top layer 128 and middle layer 126.Hydrogen is for adjusting top The pattern of layer 128 and middle layer 126.Therefore, patterned top layer is improved using hydrogen by the first plasma process 15 128 line width roughness (LWR).In some embodiments, if not over the first plasma process 15 using hydrogen come The top layer 128 of preprocessed pattern, then LWR is in the range of from about 5nm to about 9nm.In some embodiments, the is being executed After one plasma process 15, the LWR of patterned top layer 128 is in the range of from about 2nm to about 4nm.
Hydrogen has with the other function of gas of making an amendment, in the side wall of patterned top layer 128 and middle layer 126 and Protective film 140 is formed on top surface.In some embodiments, when using fluoro-gas and hydrogen, there is chemical reaction (I).Cause This, obtains protective film 140 made of the polymer containing CxHyFz.
CaFb+H2→CxHyFz (I)
If fluoro-gas can be main etching gas without using hydrogen in the first plasma process, With etching silicon-containing compound.Since middle layer 126 is made of silicon-containing compound, so middle layer 126 will be etched.In however, The etch-rate of interbed 126 can be very high.Therefore, in some embodiments, hydrogen is used in the first plasma process 15 Adjust etch-rate.When hydrogen is added to the first plasma process 15, hydrogen will be reacted with fluoro-gas (referring to chemistry React (I)), and therefore etch-rate is reduced compared with without using the first plasma process of hydrogen.On the other hand, If the amount of hydrogen used in the first plasma process 15 is too many, hydrogen is also used as etching gas, in etching Interbed 126.Therefore, it should the amount of hydrogen is controlled, to obtain desired pattern.
The flow of hydrogen is controlled according to scheduled etched width.When by the flow control of hydrogen in different ranges When, it may appear that different reactions.Occur including reaction (a), (b) and (c) in the reaction chamber of the first plasma process 15 Three reactions.In reaction (a), there is the fluorine etching reaction indicated by chemical reaction (II) and (III).
e-+CF4→CF3+F+e- (II)
Si+4F→SiF4 (III)
In reaction (b), occur forming reaction by the polymer that chemical reaction (IV) and (V) indicates.
H+F→HF (IV)
CF4+H2→CxHyFz (V)
In reaction (c), occur forming reaction by the fluorine that chemical reaction (VI) and (VII) indicates.
HF+e-→H+F+e- (VI)
H+HF→H2+F (VII)
In some embodiments, by the flow control of hydrogen from about 0.1 sccm (sccm) to about In the range of 300sccm.It is three phases, including stage I (about 0.1sccm to about 100sccm), rank by the traffic partition of hydrogen Section II (about 101sccm to about 200sccm) and stage III (about 201sccm to about 300sccm).Fig. 2 shows according to the present invention Some embodiments the second spacing P2With hydrogen (H2) flow relationship diagram.Second spacing P is shown in Fig. 1 D2。
In some embodiments, in stage I, reaction (b) is main reaction, and reacting (a) and (c) is side reaction.Therefore, Protective layer 140 is formed on the top surface and side wall of top layer 128.Improve the line width roughness (LWR) of patterned top layer 128. In other words, the pattern of the top layer 128 made of photoresist layer has been repaired.It should be noted that if the flow of hydrogen is less than 0.1sccm, then protective layer 140 is too thin and cannot repair the pattern of top layer 128.As shown in Fig. 2, in stage I, the second spacing P2It is gradually reduced with the increase of the flow of hydrogen.
In some embodiments, in stage II, reaction (b) and (c) are main reactions, and they reach balance, and anti- Answering (a) is side reaction.Therefore, while occurring being used to form the deposition reaction of protective layer 140 and the erosion for etching middle layer 126 Carve reaction.It should be noted that hydrogen (H) consumes a greater amount of fluorine (F) in stage II compared with stage I.Therefore, in stage II The ratio of carbon and fluorine (C/F) is than big in stage I.As shown in Fig. 2, in stage II, the second spacing P2With the flow of hydrogen Increase and be gradually increased.For example, in stage II, critical dimension (the second spacing P2) there is ideal range.
In some embodiments, in stage III, reaction (c) is main reaction, and reacting (a) and (b) is side reaction.Cause This, is mainly used for etching the etch process of middle layer 126.If should be noted that the flow of hydrogen is greater than 300sccm, Top layer 128 can undesirably be etched.As shown in Fig. 2, in stage III, the second spacing P2With the flow of hydrogen Increase and is gradually increased.Slope in stage III is greater than the slope in stage II.
In some embodiments, the plot ratio of the hydrogen in plasma process 15 and mixed gas is from about 3vol.% To about 60vol.%.If the flow or plot ratio of hydrogen are too small, protective film 140 can be too thick.Therefore, it obtains The wide line width of the ratio predetermined value of middle layer 126.If the flow or plot ratio of hydrogen are too big, then can remove in too many Interbed 126.Therefore, the narrow line width of the ratio predetermined value of middle layer 126 has been obtained.
In some embodiments, the first plasma process 15 is dry etching process and from about 5mT to the model of about 20mT It encloses and is operated under interior pressure.In some embodiments, first is operated by the power in the range of from about 400W to about 1000W Plasma process 15.In some embodiments, first is operated by the grid bias power supply in the range of from about 50V to about 500V Plasma process 15.In some embodiments, in the range of from about 20 DEG C to about 80 DEG C at a temperature of operation first it is equal from Plasma process 15.
Since hydrogen being controlled to be maintained within the scope of one, so hydrogen also provides in the first plasma process 15 Improve another advantage of the etching selectivity of middle layer 126.In some embodiments, relative to top layer 128, middle layer 126 With etching selectivity in the range of from about 1.2 to about 100.
In the above description, there are a variety of advantages using hydrogen in the first plasma process 15.First, improve figure The line width roughness (LWR) of the top layer 128 of case.Second, protective film is formed on top layer 128 and the side wall of middle layer 126 140, to adjust the shape of top layer 128 and middle layer 126.Third, by during the first plasma process 15 by hydrogen Flow control has obtained scheduled distance values in a range.4th, improve etching of the middle layer 126 for top layer 128 Selectivity.
According to some embodiments of the present invention, it after the first plasma process 15, as shown in figure iD, is patterned Middle layer 126.It should be noted that because the shape of top layer 128, institute are adjusted using hydrogen by the first plasma process 15 There is well-balanced pattern with patterned middle layer 126.Patterned middle layer 126 includes first part 126a, second part 126b and Part III 126c.Second part 126b is connected to Part III 126c by Part IV (not shown).
Fig. 1 D' shows the region B's of Fig. 1 D after patterned intermediate layer 126 according to some embodiments of the present invention The diagram of amplification.
As shown in figure iD, patterned middle layer 126 includes first part 126a, second part 126b and Part III 126c.Second part 126b and Part III 126c have well-balanced pattern.Do not have during apparent defect (hot spot) is formed in On the side wall of the second part 126b and Part III 126c of interbed 126.First part 126a is parallel with second part 126b simultaneously And extend along Y direction.Part III 126c is parallel with second part 126b and extends along Y direction.Part IV (not shown) is vertical with Part III 126c and extends along X-direction.By Part IV (not shown) by second part 126b is connected to Part III 126c.In some embodiments, between second between first part 126a and second part 126b Away from P2In the range of from about 35nm to about 120nm.
According to some embodiments of the present invention, as referring to figure 1E, after patterned intermediate layer 126, by using pattern The middle layer 126 of change patterns bottom 124 as mask.In some embodiments, bottom is removed by etch process 17 124 a part.
According to some embodiments of the present invention, as shown in fig. 1F, after patterning bottom 124, by using patterning Top layer 128, patterned middle layer 126 and patterned bottom 124 as mask carry out patterning hard mask layer 116.As a result, Patterned hard mask layer 116 is obtained.Patterned hard mask layer 116 includes having the 4th width W4First part 116a And have the 5th width W5Second part 116b.4th width W4With the first width W1(shown in Figure 1B) is essentially identical, and the Five width W5With the second width W2(shown in Figure 1B) is essentially identical.
Later, if removed by the dry etching process of such as wet etching process or dry etching process including top layer 128, in First photoresist structure 120 of interbed 126 and bottom 124.
According to some embodiments of the present invention, as shown in Figure 1 G, after removing the first photoresist structure 120, in pattern The second photoresist structure 220 is formed on the hard mask layer 116 of change.Second photoresist structure 220 includes bottom 224, middle layer 226 With top layer 228.Patterned top layer 228 is first to form patterned top layer 228.Patterned top layer 228 includes having than the Three width W3The 6th small width W of (as shown in Figure 1B)6First opening 240.
According to some embodiments of the present invention, as shown in fig. 1H, after patterned top layer 228, by including second etc. The Patternized technique of ionomer technology 25 carrys out patterned intermediate layer 226.It is similar with the first plasma process 15, by using packet The mixed gas of hydrogen is included to execute the second plasma process 25.In addition to hydrogen, mixed gas further include fluoro-gas, Inert gas, nitrogen (N2) or their combination.
As described above, there are a variety of advantages using hydrogen in the second plasma process 25.First, improve patterning Top layer 228 line width roughness (LWR).Second, protective film, which is formed, on top layer 228 and the side wall of middle layer 226 (does not show Out), to adjust the shape of top layer 228 and middle layer 226.Third, by controlling hydrogen during the second plasma process 25 Flow obtained scheduled distance values.4th, middle layer 226 is improved for the etching selectivity of top layer 228.
According to some embodiments of the present invention, as shown in Figure 1 I, after patterned intermediate layer 226, bottom is removed in succession 224, the second etching stopping layer 114 and the second dielectric layer 112.First through hole 251a and second is formed in the second dielectric layer 112 Through-hole 251b.
According to some embodiments of the present invention, as shown in figure iJ, after patterning the second dielectric layer 112, removal second Photoresist structure 220.
Later, according to some embodiments of the present invention, as shown in figure iK, mask is used as by using hard mask layer 116 Remove one of a part of the second etching stopping layer 114, a part of the second dielectric layer 112 and the first etching stopping layer 110 Point.As a result, the first conductive component 104 of exposure.
As shown in figure iK, first through hole 251a and first groove hole 255a collectively constitute the first ditch as dual damascene cavity Slot-through-hole structure 280a.Second through-hole 251b and second groove hole 255b collectively constitute the second groove-as dual damascene cavity Through-hole structure 280b.
Later, the second etching stopping layer 114 and hard mask layer 116 are removed.In some embodiments, it is thrown by chemical machinery Light (CMP) technique removes the second etching stopping layer 114 and hard mask layer 116.
Later, according to some embodiments of the present invention, as can be seen in 1L, in first groove-through-hole structure 280a and second Diffusion barrier 140 is formed in groove-through-hole structure 280b, and the second conductive component is formed on Diffusion barrier 140 142.In other words, the second conductive component 142 is formed in the second dielectric layer 112, and is surrounded by Diffusion barrier 140.It is logical It crosses and fills diffusion barrier layer 140 and the second conductive component 142 in first groove-through-hole structure 280a to form the first conductive knot Structure 145a, and by filled in second groove-through-hole structure 280b diffusion barrier layer 140 and the second conductive component 142 come Form the second conductive structure 145b.Second conductive component 142 is electrically connected to the first conductive component 104.It is embedded in the first dielectric layer The first conductive component 104 in 106 forms interconnection structure with the second conductive component 142 being embedded in the second dielectric layer 112 230。
In some embodiments, Diffusion barrier 140 can be by titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or aluminium nitride (AlN) is made.In some embodiments, the second conductive component 142 is made of copper, and Diffusion barrier 140 include TaN/Ta double-deck.
Fig. 1 L' shows the perspective view of semiconductor device structure 100 according to some embodiments of the present invention.Fig. 1 L is shown Along the sectional view of the line III-III' of Fig. 1 L'.
As shown in Fig. 1 L', third conductive structure 145c is formed in the second dielectric layer 112.First conductive structure 145a with Second conductive structure 145b is parallel, and the first conductive structure 145a is parallel with third conductive structure 145c.It is formed along a y-direction Second conductive structure 145b and third conductive structure 145c.Second conductive structure 145b has first end 147, third conductive structure 145c has second end 149, and first end 147 and second end 149 are located on the opposite side of the second dielectric layer 112.Between end-end Every S1It is defined as the distance between first end 147 and second end 149.Third spacing P3It is defined as from the first conductive structure The distance of 145a to third conductive structure 145c.In some embodiments, third spacing P3From about 70nm to the model of about 90nm In enclosing.
It obtains the pattern of the second dielectric layer 112 indirectly as mask by using patterned hard mask layer 116, and leads to It crosses and uses top layer 128 as mask and obtain patterned hard mask layer 116 indirectly.If do not made in the first plasma process 15 With hydrogen, then due to some defects (as shown in Figure 1B) in the region A of top layer 128, the first conductive structure 145a and second The pattern of the second dielectric layer 112 between conductive structure 145b can be damaged or even be destroyed.If do not modified in top layer 128 Defect, then can the therefore region that form some defects in the second dielectric layer 112 or be destroyed.Therefore, because can pass through The second dielectric layer 112 being destroyed contacts with each other the first conductive structure 145a and the second conductive structure 145b, so will appear Undesirable bridge joint problem.
It should be noted that the pattern of top layer 128 is modified using hydrogen by using plasma process, therefore by middle layer 126 is patterned with scheduled pattern.In addition, by the flow control of hydrogen in a range, to obtain scheduled spacing P3With end-end interval S3.In addition, improving LWR and the etching choosing of middle layer 126 using hydrogen by using plasma process Selecting property.
Later, the processing step of Figure 1A to Fig. 1 L can be repeated, (is not shown with constructing multilayer dual damascene metal interconnection structure Out).In some other embodiments, using the disclosed plasma process using hydrogen, to form single inlay structure.
It provides and is used to form embodiment of semiconductor device structure and forming method thereof.By several Patternized techniques come Form interconnection structure.Patternized technique includes using the three layer photoresist structures for including top layer, middle layer and bottom.Pattern first Change top layer, to form patterned top layer.By plasma process using hydrogen come patterned intermediate layer.Pass through plasma Technique forms protective layer on top layer and the side wall of middle layer to adjust the defects of patterned top layer, to compensate top The shape of layer.Improve the line width roughness (LWR) of top layer by plasma process.In being improved by plasma process Etching selectivity of the interbed for top layer.In addition, the flow of hydrogen is maintained within the scope of one, with obtain scheduled spacing and End-end interval.Therefore, it has obtained with smaller spacing and end-end interval interconnection structure.
In some embodiments, a kind of method for being used to form semiconductor device structure is provided.Method includes providing lining Bottom and bottom, middle layer and top layer is formed on the substrate.Method further include: patterned top layer, to form patterned top layer, And the Patternized technique by including plasma process is come patterned intermediate layer, to form patterned middle layer.Pass through Using including hydrogen (H2) mixed gas execute plasma process.Method further include: control hydrogen (H2) flow, with Improve middle layer for the etching selectivity of top layer, wherein patterned middle layer includes first part and parallel with first part Second part, and the spacing between first part and second part.
In some embodiments, a kind of method for being used to form semiconductor device structure is provided.Method includes providing lining Bottom and dielectric layer is formed on the substrate.Method further include: form hard mask layer and the shape on hard mask layer on the dielectric layer At bottom, middle layer and top layer.Method further include: patterned top layer, to form patterned top layer, and by include etc. from The Patternized technique of plasma process carrys out patterned intermediate layer, to form patterned middle layer.By using including hydrogen (H2) Mixed gas execute plasma process.Method includes: patterning bottom, to form patterned bottom, and is passed through Patterned top layer, patterned middle layer and patterned bottom are used as mask and carrys out patterning hard mask layer, to be formed Patterned hard mask layer.
In some embodiments, a kind of method for being used to form semiconductor device structure is provided.Method includes providing lining Bottom and dielectric layer is formed on the substrate.Method further include: form hard mask layer and the shape on hard mask layer on the dielectric layer At bottom, middle layer and top layer, and middle layer is made of silicon-containing compound.Method includes: patterned top layer, to form pattern The top layer of change, and plasma process is executed on top layer, to improve the line width roughness (LWR) of top layer.Plasma work Skill includes using including hydrogen (H2) mixed gas.Method includes continuously performing plasma process to middle layer, to push up Protective film is formed on the side wall of layer and the side wall of middle layer, and plasma process is continuously performed to middle layer, in removal A part of interbed, to form patterned middle layer.Method includes: patterning bottom, to form patterned bottom, and And patterning hard mask layer is come as mask by using patterned top layer, patterned middle layer and patterned bottom, To form patterned hard mask layer.
The component of several embodiments is discussed above, so that the present invention may be better understood in those of ordinary skill in the art Various aspects.It will be understood by those skilled in the art that can easily using based on the present invention designing or Other are changed for reaching purpose identical with embodiment described herein and/or realizing the processing and structure of same advantage.This Field those of ordinary skill it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and not In the case where the spirit and scope of the present invention, a variety of variations can be carried out, replaced and changed.
In order to solve the problems in the prior art, according to some embodiments of the present invention, it provides one kind and is used to form half The method of conductor device structure, comprising: receive substrate；Bottom, middle layer and top layer are formed over the substrate；Described in patterning Top layer, to form patterned top layer；The middle layer is patterned by including the Patternized technique of plasma process, with Form patterned middle layer, wherein by using including hydrogen (H2) mixed gas execute the plasma process； And control hydrogen (H2) flow, to improve the middle layer for the etching selectivity of the top layer, wherein the pattern The middle layer of change includes first part and the second part parallel with the first part, and between the first part with it is described Spacing between second part.
In the above-mentioned method for being used to form the semiconductor device structure, relative to the top layer, the middle layer tool There is etching selectivity in the range of from about 1.2 to about 100.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the hydrogen (H2) flow from In the range of 0.1sccm to about 300sccm.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the mixed gas further include: fluorine-containing Gas, inert gas or their combination.
In the above-mentioned method for being used to form the semiconductor device structure, wherein pattern the middle layer further include: Protective layer is formed on the side wall of the middle layer.
Other embodiments according to the present invention provide a kind of method for being used to form semiconductor device structure, comprising: Receive substrate；Dielectric layer is formed over the substrate；Hard mask layer is formed on the dielectric layer；The shape on the hard mask layer At bottom, middle layer and top layer；The top layer is patterned, to form patterned top layer；By including plasma process Patternized technique patterns the middle layer, to form patterned middle layer, wherein by using including hydrogen (H2) Mixed gas executes the plasma process；The bottom is patterned, to form patterned bottom；And by using The patterned top layer, the patterned middle layer and the patterned bottom are patterned as mask described to be covered firmly Mold layer, to form patterned hard mask layer.
In the above-mentioned method for being used to form the semiconductor device structure, wherein relative to the top layer, the centre Layer has etching selectivity in the range of from about 1.2 to about 100.
In the above-mentioned method for being used to form the semiconductor device structure, wherein hydrogen (H2) and the mixed gas Plot ratio in the range of from about 3vol% to about 60vol%.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the plasma process is for changing It is apt to the line width roughness (LWR) of the middle layer.
In the above-mentioned method for being used to form the semiconductor device structure, wherein pattern the middle layer further include: Protective layer is formed on the side wall of the middle layer.
In the above-mentioned method for being used to form the semiconductor device structure, further includes: the removal patterned top layer, The patterned middle layer and the patterned bottom；The second bottom, are formed on the patterned hard mask layer Two middle layers and the second top layer；Second top layer is patterned, to form patterned second top layer；Pass through the second plasma Technique patterns second middle layer, to form patterned second middle layer, wherein second middle layer is by siliceous Compound is made, and second plasma process includes using including hydrogen (H2) mixed gas.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the hydrogen in the plasma process Gas (H2) flow in the range of from 0.1sccm to about 300sccm.
In the above-mentioned method for being used to form the semiconductor device structure, the mixed gas further include: fluoro-gas, Inert gas or their combination.
In the above-mentioned method for being used to form the semiconductor device structure, the mixed gas further include: fluoro-gas, Inert gas or their combination；Wherein, the fluorochemical includes Nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hexafluoro second Alkane (C2F6), tetrafluoromethane (CF4), fluoroform (CHF3), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8) or octafluoroisobutene (C4F8) or fluorine gas (F2)。
Other embodiment according to the present invention provides a kind of method for being used to form semiconductor device structure, comprising: Receive substrate；Dielectric layer is formed over the substrate；Hard mask layer is formed on the dielectric layer；The shape on the hard mask layer At bottom, middle layer and top layer, wherein the middle layer is made of silicon-containing compound；The top layer is patterned, to form pattern The top layer of change；Plasma process is executed to the top layer, to improve the line width roughness (LWR) of the top layer, wherein described Plasma process includes using including hydrogen (H2) mixed gas；The plasma work is continuously performed to the middle layer Skill, to form protective film on the side wall of the top layer and the side wall of the middle layer；The middle layer is continuously performed described Plasma process, to remove a part of the middle layer, to form patterned middle layer；The bottom is patterned, To form patterned bottom；By using the patterned top layer, the patterned middle layer and described patterned Bottom patterns the hard mask layer as mask, to form patterned hard mask layer.
In the above-mentioned method for being used to form the semiconductor device structure, wherein relative to the top layer, the centre Layer has etching selectivity in the range of from about 1.2 to about 100.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the hydrogen in the plasma process Gas (H2) flow in the range of from 0.1sccm to about 300sccm.
In the above-mentioned method for being used to form the semiconductor device structure, wherein hydrogen (H2) and the mixed gas Plot ratio in the range of from about 3vol% to about 60vol%.
In the above-mentioned method for being used to form the semiconductor device structure, wherein the mixed gas further include: fluorine-containing Gas, inert gas or their combination.
In the above-mentioned method for being used to form the semiconductor device structure, wherein from about 5mT to the range of about 20mT First plasma process is executed under interior pressure.

Claims (19)

1. a kind of method for being used to form semiconductor device structure, comprising:
Receive substrate；
Hard mask layer is formed over the substrate；
Bottom, middle layer and top layer are formed on the hard mask layer；
The top layer is patterned, to form patterned top layer；
The middle layer is patterned by including the Patternized technique of plasma process, to form patterned middle layer, Wherein, by using including hydrogen (H2) mixed gas execute the plasma process；
The bottom is patterned, to form patterned bottom；
Figure is come as mask by using the patterned top layer, the patterned middle layer and the patterned bottom Hard mask layer described in case, to form patterned hard mask layer；And
Control hydrogen (H2) flow, to improve the middle layer for the etching selectivity of the top layer, wherein the pattern The middle layer of change includes first part and the second part parallel with the first part, and between the first part with it is described Spacing between second part；
Remove the patterned top layer, the patterned middle layer and the patterned bottom；
The second bottom, the second middle layer and the second top layer are formed on the patterned hard mask layer；
Second top layer is patterned, to form patterned second top layer；
Second middle layer is patterned by the second plasma process, to form patterned second middle layer, and Second plasma process includes using including hydrogen (H2) another mixed gas.
2. the method according to claim 1 for being used to form the semiconductor device structure, described relative to the top layer Middle layer has etching selectivity in the range of from 1.2 to 100.
3. the method according to claim 1 for being used to form the semiconductor device structure, wherein the hydrogen (H2) Flow is in the range of from 0.1sccm to 300sccm.
4. the method according to claim 1 for being used to form the semiconductor device structure, wherein the mixed gas is also It include: fluoro-gas, inert gas or their combination.
5. the method according to claim 1 for being used to form the semiconductor device structure, wherein pattern the centre Layer further include: form protective layer on the side wall of the middle layer.
6. a kind of method for being used to form semiconductor device structure, comprising:
Receive substrate；
Dielectric layer is formed over the substrate；
Hard mask layer is formed on the dielectric layer；
Bottom, middle layer and top layer are formed on the hard mask layer；
The top layer is patterned, to form patterned top layer；
The middle layer is patterned by including the Patternized technique of plasma process, to form patterned middle layer, Wherein, by using including hydrogen (H2) mixed gas execute the plasma process；
The bottom is patterned, to form patterned bottom；And
Figure is come as mask by using the patterned top layer, the patterned middle layer and the patterned bottom Hard mask layer described in case, to form patterned hard mask layer；
Remove the patterned top layer, the patterned middle layer and the patterned bottom；
The second bottom, the second middle layer and the second top layer are formed on the patterned hard mask layer；
Second top layer is patterned, to form patterned second top layer；
Second middle layer is patterned, by the second plasma process to form patterned second middle layer, wherein Second middle layer is made of silicon-containing compound, and second plasma process includes using including hydrogen (H2) Another mixed gas.
7. the method according to claim 6 for being used to form the semiconductor device structure, wherein relative to the top Layer, the middle layer have etching selectivity in the range of from 1.2 to 100.
8. the method according to claim 6 for being used to form the semiconductor device structure, wherein hydrogen (H2) with it is described The plot ratio of mixed gas is in the range of from 3vol% to 60vol%.
9. the method according to claim 6 for being used to form the semiconductor device structure, wherein the plasma work Skill is used to improve the line width roughness (LWR) of the middle layer.
10. the method according to claim 6 for being used to form the semiconductor device structure, wherein during patterning is described Interbed further include: form protective layer on the side wall of the middle layer.
11. the method according to claim 6 for being used to form the semiconductor device structure, wherein the plasma Hydrogen (H in technique2) flow in the range of from 0.1sccm to 300sccm.
12. the method according to claim 6 for being used to form the semiconductor device structure, the mixed gas are also wrapped It includes: fluoro-gas, inert gas or their combination.
13. the method according to claim 12 for being used to form the semiconductor device structure, wherein the fluoro-gas Including Nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), perfluoroethane (C2F6), tetrafluoromethane (CF4), fluoroform (CHF3), two Fluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8) or octafluoroisobutene (C4F8) or fluorine gas (F2)。
14. a kind of method for being used to form semiconductor device structure, comprising:
Receive substrate；
Dielectric layer is formed over the substrate；
Hard mask layer is formed on the dielectric layer；
Bottom, middle layer and top layer are formed on the hard mask layer, wherein the middle layer is made of silicon-containing compound；
The top layer is patterned, to form patterned top layer；
Plasma process is executed to the top layer, to improve the line width roughness (LWR) of the top layer, wherein it is described it is equal from Plasma process includes using including hydrogen (H2) mixed gas；
The plasma process is continuously performed to the middle layer, in the side wall of the side wall of the top layer and the middle layer Upper formation protective film；
The plasma process is continuously performed to the middle layer, to remove a part of the middle layer, to form figure The middle layer of case；
The bottom is patterned, to form patterned bottom；
Figure is come as mask by using the patterned top layer, the patterned middle layer and the patterned bottom Hard mask layer described in case, to form patterned hard mask layer；
Remove the patterned top layer, the patterned middle layer and the patterned bottom；
The second bottom, the second middle layer and the second top layer are formed on the patterned hard mask layer；
Second top layer is patterned, to form patterned second top layer；
Second middle layer is patterned by the second plasma process, to form patterned second middle layer, and Second plasma process includes using including hydrogen (H2) another mixed gas.
15. the method according to claim 14 for being used to form the semiconductor device structure, wherein relative to the top Layer, the middle layer have etching selectivity in the range of from 1.2 to 100.
16. the method according to claim 14 for being used to form the semiconductor device structure, wherein the plasma Hydrogen (H in technique2) flow in the range of from 0.1sccm to 300sccm.
17. the method according to claim 14 for being used to form the semiconductor device structure, wherein hydrogen (H2) and institute The plot ratio of mixed gas is stated in the range of from 3vol% to 60vol%.
18. the method according to claim 14 for being used to form the semiconductor device structure, wherein the mixed gas Further include: fluoro-gas, inert gas or their combination.
19. the method according to claim 14 for being used to form the semiconductor device structure, wherein from 5mT to The plasma process is executed under pressure in the range of 20mT.
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