CN105957873B - The anti-latch system of cmos image sensor based on space application - Google Patents
The anti-latch system of cmos image sensor based on space application Download PDFInfo
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- CN105957873B CN105957873B CN201610389103.0A CN201610389103A CN105957873B CN 105957873 B CN105957873 B CN 105957873B CN 201610389103 A CN201610389103 A CN 201610389103A CN 105957873 B CN105957873 B CN 105957873B
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- 230000001681 protective effect Effects 0.000 claims abstract description 11
- 230000006641 stabilisation Effects 0.000 claims abstract description 7
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Abstract
The anti-latch system of cmos image sensor based on space application, it is related to a kind of anti-latch system of cmos image sensor, easily there is latch in the cmos image sensor solved in existing space application, the problem of causing device failure even to burn, including external input power, process part and focal plane part, external input power is powered to process part and focal plane part simultaneously；Process part includes controller, current detection module, comparator, controller kernel power supply module, controller IO power supply modules, controller peripheral circuit power supply module, electrical level transferring chip group and differential interface chipset；Focal plane part includes n groups protective resistance, n group voltage transformation chips and reference source circuit；Each section time-sharing power after external input power output voltage stabilization reduces the surge current of DC/DC module for power supply systems；The last peripheral parts of IO, avoid each section while powering on and output voltage occur and decline in uphill process after controller elder generation kernel, and it is reliable and stable to ensure that controller powers on.
Description
Technical field
The present invention relates to a kind of anti-latch systems of cmos image sensor, and in particular to a kind of CMOS based on space application
The anti-latch system of imaging sensor.
Background technology
Currently, cmos image sensor is compared with ccd image sensor, has and do not need external drive, analog-to-digital conversion electricity
Road, it is small low in energy consumption the advantages that, but its space environment application in easily there is latch, cause device failure even burn
It ruins.Low voltage difference power supply chip such as MAX883 has current-limiting protection function, is more than the feelings that 0.7V output voltages are more than 0.8V in pressure difference
Maximum output current is 430mA under condition；In the case where output voltage is less than 0.8V, maximum output current is 170mA.But device
Heat protection function at 160 DEG C, the principle reduced with temperature raising using the conducting voltage of the PN junction of transistor, Zhi Nengying
Thermal shock to moment is inoperative in the case where whole junction temperature is excessively high.Therefore is there is serious latch (power supply in CMOS
The near short circuit between ground) in the case of, the Wen Sheng of MAX883 increases sharply, if not taking appropriate measures, is just deposited in 1min
Burning risk.
Invention content
The present invention is that the cmos image sensor solved in existing space application latch easily occurs, leads to device failure
The problem of even burning, provides a kind of anti-latch system of the cmos image sensor based on space application.
The anti-latch system of cmos image sensor based on space application, including external input power, process part and coke
Face part, the external input power are powered to process part and focal plane part simultaneously；It is characterized in that the process part includes
Controller, current detection module, comparator, controller kernel power supply module, controller IO power supply modules, controller peripheral circuit
Power supply module, electrical level transferring chip group and differential interface chipset；Focal plane part includes n groups protective resistance, n group voltage transformation cores
Piece and reference source circuit；
The controller kernel power supply module and controller IO power supply modules are respectively to the kernel of controller and controller IO
Mouth is powered, and the controller peripheral circuit power supply module is to comparator, electrical level transferring chip group and differential interface chipset
Power supply；The current detection module is connected with comparator, and comparator is connect with controller, the controller while and level conversion
Chipset, differential interface chipset are connected with n group voltage transformation chips；
The current detection module is connect by n groups protective resistance with n group voltage transformation chips, and the n-1 groups voltage becomes
It changes chip to connect with cmos image sensor respectively, n-th group voltage transformation chip is by reference to source circuit and the cmos image
Sensor connects；The cmos image sensor is connect with electrical level transferring chip group and differential interface chipset；
The external input power successively to controller kernel power supply module, controller IO power supply modules and controller outside
It encloses circuit power supply module to power on, after the voltage stabilization of controller peripheral circuit power supply module output, the n groups voltage becomes
Chip Enable Pin output voltage is changed, after the voltage of n groups voltage transformation chip output reaches rated voltage, the level turns
It changes chipset and differential interface chipset is switched to enabled output state by high-impedance state；And signal control CMOS figures are generated respectively
As working sensor；
It is in line that the power detection module detects the current value I outputs exported on focal plane part and the current value I in real time
The voltage value KI of sexual intercourse is to comparator, in the voltage value KI and comparator that the comparator detects the power detection module
Threshold voltage VthCompare, and comparison result is sent to controller；
If the controller receives high level, and is all high level in three master clock cycles of controller, then recognize
It makes and has showed latch；If receiving low level, do not occur latch.
Beneficial effects of the present invention：The present invention provides the anti-latch system of cmos image sensor based on space application, soon
Speed is detected latch phenomenon, cut off the power or supply voltage is reduced to be not enough to maintain parasitic circuit regeneration and door bolt
Lock status protects cmos image sensor and interlock circuit.There are the above advantages：
1, external input power of the present invention uses DC/DC modules, each portion after DC/DC module output voltage stabilizations
Divide time-sharing power, the surge current of DC/DC module for power supply systems can be reduced；The last peripheral parts of IO, keep away after controller elder generation kernel
Exempt from each section while powering on and output voltage occur and decline in uphill process, ensures that controller power up is reliable and stable；On
Controller IO is powered on prior to peripheral part in electric process, and it is latent logical to avoid occurring in power up IO, occurs to reduce controller
The probability of latch；After the supply voltage of cmos image sensor reaches voltage, electrical level transferring chip group and differential interface chip
The input and output port side of group is switched to enabled input/output state by high-impedance state, avoids occurring diving in power up logical,
Cmos image sensor damages；
2, the present invention ensures cmos image sensor AEROSPACE APPLICATION by quick detection and protection to CMOS latch processes
Reliability and safety, it is ensured that the success of AEROSPACE APPLICATION.
Description of the drawings
Fig. 1 is the structure diagram of the anti-latch system of the cmos image sensor of the present invention based on space application；
What Fig. 2 was an externally input power supply DC/DC modules powers on flow chart.
Specific implementation mode
Specific implementation mode one illustrates present embodiment in conjunction with Fig. 1 and Fig. 2, the cmos image sensing based on space application
The anti-latch system of device, the system can quickly be detected latch phenomenon, cut off the power or are reduced to supply voltage not
It is enough to maintain the regeneration of parasitic circuit and latch mode.
It is specific to be input from the outside power supply, process part and focal plane part composition.Process part is mainly examined by controller, electric current
Survey module, comparator, controller kernel power supply module, controller IO power supply modules, controller peripheral circuit power supply module, level
Conversion chip group and differential interface chipset composition；Controller kernel power supply module and controller IO power supply modules are respectively to control
The kernel and IO of device are powered, and controller peripheral circuit power supply module is to comparator, electrical level transferring chip group and differential interface
Chipset is powered；
Focal plane part includes n groups protective resistance, n group voltage transformations chip, reference source circuit and cmos image sensor；
The external input power uses DC/DC modules, is proposed based on the steady of DC/DC module for power supply in present embodiment
Electric control system on fixed reliable FPGA, controller kernel power supply module, controller IO power supply modules and controller peripheral circuit
Power supply module is non-concurrent to be powered on, and the not enabled output in the output voltage uphill process of DC/DC modules.DC/DC modules
Output voltage reach rated voltage after, electric sequence is that controller kernel power supply module powers on, and waits for that kernel power supply module is defeated
Controller IO power supply modules start power up after going out voltage stabilization, after device IO power supply module output voltage stabilizations to be controlled outside controller
It encloses circuit power supply module to start power up, device peripheral circuit module power supply output voltage stabilization back focal plane portion voltage transformation to be controlled
The enabled output of chip, after focal plane portion voltage transformation chip output voltage reaches rated voltage, electrical level transferring chip group and difference
Tap mouth chipset is switched to enabled output by high-impedance state, generates cmos image sensor related work sequential.
In present embodiment, before external input power is sent into focal plane part, the electric current that resistance value is milliohm grade is sealed in and has examined
Module is surveyed, the current value I of out-put supply on focal plane part, output and electric current voltage value KI in a linear relationship can be detected in real time；
The voltage value KI and threshold voltage V of outputthCompare in comparator, there is latch in the representative of the high level of output, output it is low
Level representative does not occur latch.
Chip has EN enable pins in electrical level transferring chip group and differential interface chipset described in present embodiment, when
Allow input or output signal when EN is effective, high-impedance state is presented in its I/O port when EN invalidating signals.The n groups voltage transformation
Chip contains OFF enable pins, the not output voltage when OFF is effective, the normal output voltage when OFF is invalid；Wherein preceding n-1
Group voltage transformation chip is directly that cmos image sensor is powered, and n-th group voltage transformation chip is powered for reference source circuit, described
Reference source circuit provides reference voltage to cmos image sensor.
In present embodiment, the external input power uses DC/DC modules, while being supplied to process part and focal plane part
Electricity seals in protective resistance in voltage transformation chip input terminal, latch-up current can be limited when latch occurs in cmos image sensor,
Prior purpose is to reduce the pressure drop of voltage transformation, delays the time burnt.
The controller of the process part receives the level value of comparator output, if continuous three master clock weeks in controller
There is latch in phase judgement, then
One, the Enable Pin EN for the electrical level transferring chip group being connected with cmos image sensor is set as allowing all level
Conversion chip is high-impedance state, avoid single-ended signal end from existing latent logical；
Two, the Enable Pin EN for the differential interface chipset being connected with cmos image sensor is set as allowing all difference
Chip is high-impedance state, avoids differential ends from existing latent logical；
Three, the Enable Pin OFF of all power supply chips such as MAX883 of cmos image sensor is set low, is made all for battery core
Piece not output voltage, power supply chip is protected, avoids burning risk.Cmos image sensor has released latch mode,
It can be powered back up operation with focusing plane part.
Four, focusing plane part is powered back up operation, if focusing plane part is powered back up operation in vain, cuts off external input
Power supply.
In present embodiment, the selection principle of the protective resistance resistance valueV in formulaINFor
External input power voltage, VOUTiRated output voltage, V are organized for i-th (1 < i < n)droupoutiFor i-th group of voltage transformation chip
In peak operation current IpixiWhen pressure difference；Power consumption selection principle Pi> 9I2 pixiRi。
In present embodiment, threshold voltage VthSelection principle beIn formulaFor n
The sum of the peak point current of group voltage transformation；IpixminFor cmos image sensor IO power supplies and differential input and output power supply electricity
Minimum value in ource electric current.
In present embodiment, controller uses the device XC6VLX240T-2FFG1156C of Xilinx companies；Described
Cmos image sensor uses the CMV300 of the global shutter of CMOSIS companies；Voltage transformation chip uses MAX883 chips,
Its power supply module uses the power supply chip of MSK companies；Electrical level transferring chip group uses multi-disc SN74AVC20T245ZQLR；Difference
Interface chip group uses LVDS31 and LVDS32；Current detection module uses the special electric current detection chip of Maxim；Compare
Device uses LM339；Reference power source circuit is mainly made of AD584.
Claims (4)
1. the anti-latch system of cmos image sensor based on space application, including external input power, process part and focal plane
Part, the external input power are powered to process part and focal plane part simultaneously；It is characterized in that the process part includes control
Device processed, current detection module, comparator, controller kernel power supply module, controller IO power supply modules, controller peripheral circuit supply
Electric module, electrical level transferring chip group and differential interface chipset；Focal plane part includes n groups protective resistance, n group voltage transformation chips
And reference source circuit；
The controller kernel power supply module and controller IO power supply modules respectively to the kernel of controller and controller I/O port into
Row power supply, the controller peripheral circuit power supply module power to comparator, electrical level transferring chip group and differential interface chipset；
The current detection module is connected with comparator, and comparator is connect with controller, the controller while and level conversion
Chipset, differential interface chipset are connected with n group voltage transformation chips,
The current detection module is connect by n groups protective resistance with n group voltage transformation chips, n-1 group voltage transformation chips point
It is not connect with cmos image sensor, n-th group voltage transformation chip is connected by reference to source circuit and the cmos image sensor
It connects；The cmos image sensor is connect with electrical level transferring chip group and differential interface chipset；
The external input power is successively to controller kernel power supply module, controller IO power supply modules and controller periphery electricity
Road power supply module powers on, after the voltage stabilization of controller peripheral circuit power supply module output, the n groups voltage transformation core
Piece Enable Pin output voltage, after the voltage of n groups voltage transformation chip output reaches rated voltage, the level conversion core
Piece group and differential interface chipset are switched to enabled output state by high-impedance state；And signal control cmos image is generated respectively and is passed
Sense device working；
The power detection module detects the current value I outputs exported on focal plane part and is linearly closed with the current value I in real time
The voltage value KI of system is to comparator, voltage value KI and the threshold in comparator that the comparator detects the power detection module
Threshold voltage VthCompare, and comparison result is sent to controller；
If the controller receives high level, and is all high level in three master clock cycles of controller, then assert
Latch is showed；If receiving low level, do not occur latch；
Chip is both provided with EN enable pins in the electrical level transferring chip group and differential interface chipset, when EN signals are effective
Allow input or output signal, when EN invalidating signals, the I/O port of the electrical level transferring chip group and differential interface chipset
High-impedance state is presented；
The n groups voltage transformation chip contains OFF enable pins, the not output voltage when OFF is effective, just when OFF is invalid
Normal output voltage；The n-1 groups voltage transformation chip is directly that cmos image sensor is powered, and n-th group voltage transformation chip is
Reference source circuit is powered, and the reference source circuit provides reference voltage to cmos image sensor；
After latch occurs in the controller judgement, the Enable Pin EN of electrical level transferring chip group is disposed as high resistant by the controller
State sets the Enable Pin EN of differential interface chipset to high-impedance state, and n group voltage transformation chip Enable Pins OFF is set low,
Make n group voltage transformations chip not output voltage；Controller focusing plane part is powered back up operation, if focusing plane part is powered back up
Operation is invalid, then cuts off external input power.
2. the anti-latch system of the cmos image sensor according to claim 1 based on space application, which is characterized in that institute
It is DC/DC modules to state external input power.
3. the anti-latch system of the cmos image sensor according to claim 1 based on space application, which is characterized in that institute
The selection principle for the protective resistance resistance value stated is：
V in formulaINIt is an externally input the voltage of power supply, VOUTiFor i-th group of protective resistance rated output voltage, VdroupoutiIt is i-th group
Voltage transformation chip is in peak operation current IpixiWhen pressure difference；Protective resistance power consumption selection principle Pi> 9I2 pixiRi；The i's
Ranging from：1 < i < n.
4. the anti-latch system of the cmos image sensor according to claim 1 based on space application, which is characterized in that institute
State threshold voltage VthSelection principle be：
In formulaFor the sum of the peak point current of n group voltage transformation chips；IpixminFor cmos image sensor IO power supplies
With the minimum value in differential input and output power supply electric current.
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| CN107134758B (en) * | 2017-05-08 | 2019-02-22 | 哈尔滨工业大学 | Cmos device single event latch-up effect protective device under a kind of space environment |
| CN108811243A (en) * | 2018-06-06 | 2018-11-13 | 无锡华兆泓光电科技有限公司 | A kind of intelligent Anti-surging LED lamp driver of farm |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103777135A (en) * | 2012-10-18 | 2014-05-07 | 北京圣涛平试验工程技术研究院有限责任公司 | Single particle latch monitoring method and apparatus of FPGA |
| CN104375549A (en) * | 2014-10-30 | 2015-02-25 | 中国电子科技集团公司第三十六研究所 | Latching-preventing circuit of CMOS device |
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| CA1287103C (en) * | 1986-04-22 | 1991-07-30 | Jim Pinard | Cmos latch-up recovery circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103777135A (en) * | 2012-10-18 | 2014-05-07 | 北京圣涛平试验工程技术研究院有限责任公司 | Single particle latch monitoring method and apparatus of FPGA |
| CN104375549A (en) * | 2014-10-30 | 2015-02-25 | 中国电子科技集团公司第三十六研究所 | Latching-preventing circuit of CMOS device |
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