CN105957815A - Semiconductor structure forming method - Google Patents
Semiconductor structure forming method Download PDFInfo
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- CN105957815A CN105957815A CN201610300833.9A CN201610300833A CN105957815A CN 105957815 A CN105957815 A CN 105957815A CN 201610300833 A CN201610300833 A CN 201610300833A CN 105957815 A CN105957815 A CN 105957815A
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- Prior art keywords
- wafer
- forming method
- semiconductor structure
- metal
- described wafer
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 239000002184 metal Substances 0.000 claims abstract description 91
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000003153 chemical reaction reagent Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 14
- 238000001704 evaporation Methods 0.000 claims description 10
- 230000008020 evaporation Effects 0.000 claims description 10
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a semiconductor structure forming method comprising the following steps: providing a wafer, wherein the wafer includes a first side and a second side which face each other; forming a semiconductor device on the first side of the wafer; coarsely processing the second side of the wafer; and after coarse processing, forming a metal structure on the second side of the wafer. There is no need for high-temperature baking in the process of coarse processing, so damage to the semiconductor device due to high-temperature baking is avoided, and the influence of high-temperature baking on the semiconductor device is reduced. Therefore, through the semiconductor structure forming method, the performance of semiconductor structures is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor structure
Forming method.
Background technology
Along with the continuous progress of semiconductor technology, the application of semiconductor device is more and more extensive.Semiconductor device
The extensively application of part not only improvement to performance of semiconductor device proposes high requirement, semiconductor device
Outward appearance the most gradually attracts much attention.
The extensively application of semiconductor device requires that semiconductor device the most all can normally work.
But, semiconductor device be difficult to avoid that in application process heat to be produced, thus cause semiconductor device
The rising of part temperature, this just requires that described semiconductor device can the most normally work.In order to
Ensureing that semiconductor device can the most normally work, semiconductor device needs to carry out before dispatching from the factory
High temperature test.
In order to realize described semiconductor device and outside electrical connection, the described semiconductor device back side is often plated
There is metal structure.But, during described high temperature test, described metal structure surface is easily formed scarce
Fall into.In order to eliminate described defect, semiconductor technology is it is generally required to carry out high temperature baking to described semiconductor device
Roasting, but, described high-temperature baking easily affects the performance of described semiconductor device.
As can be seen here, the forming method of described semiconductor structure is partly led in easily affecting described semiconductor structure
The performance of body device.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, it is possible to improve quasiconductor
Structural behaviour.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: provide
Wafer, described wafer includes relative first and second；Quasiconductor is formed described wafer first
Device；Described wafer the second face is carried out crude process；After described crude process, at described wafer
Metal structure is formed on two.
Optionally, before described second face being carried out crude process by chemical reagent, also include: in institute
State wafer first and form protecting film；The step that described second face is carried out crude process includes: by institute
State chemical reagent and soak described wafer.
Optionally, the material of described wafer is silicon；The solvent of described chemical reagent includes: HNO3, H2SO4
And HF.
Optionally, HNO in described chemical reagent3Mass percent concentration be 5%～10%；H2SO4
Mass percent concentration be 75～85%；The mass percent concentration of HF is 1～5%.
Optionally, before described second face being carried out crude process by chemical reagent, also include: in institute
State wafer first and form protecting film.
Optionally, the material of described protecting film is blue film, and described second face carries out the step of crude process
Including: on described wafer second, paste described protecting film.
Optionally, being soaked by described chemical reagent in the step of described wafer, soak time is 15s～30s.
Optionally, after forming metal structure, described forming method also includes: carry out high temperature test, uses
In detection described semiconductor device performance at high operating temperatures；Carry out in the step of high temperature test, described
The temperature of wafer is 110 DEG C～140 DEG C.
Optionally, described metal structure includes the first metal layer；The material of described the first metal layer is silver；
The thickness of described the first metal layer is 9000 angstroms～11000 angstroms.
Optionally, the technique forming described metal structure includes: evaporation process.
Compared with prior art, technical scheme has the advantage that
In the forming method of the semiconductor structure of the present invention, before forming described metal structure, to described
Wafer the second face carries out crude process, by increasing capacitance it is possible to increase the roughness of described wafer second, so that being formed
Layer on surface of metal be hair side, it is possible to cover the defect of layer on surface of metal, improve layer on surface of metal pattern.
Additionally, described crude processing procedure need not high-temperature baking, it is possible to avoid high-temperature baking to make described partly to lead
Body device is damaged such that it is able to reduce the high-temperature baking impact on described semiconductor device.Therefore,
The forming method of described semiconductor structure can improve the performance of semiconductor structure.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of method for forming semiconductor structure one embodiment of the present invention；
Fig. 2 to Fig. 6 is the structural representation of the forming method one each step of embodiment of the semiconductor structure of the present invention
Figure.
Detailed description of the invention
There are problems in the forming method of the semiconductor structure of prior art, such as: described forming method
Easily affect the performance of semiconductor structure.
In conjunction with the forming method of a kind of semiconductor structure, analyzing described forming method easily affects quasiconductor
The reason of structural behaviour:
In the forming method of described semiconductor structure, in order to ensure that semiconductor device can be in high temperature environments
Normal work, semiconductor device needs to carry out high temperature test before dispatching from the factory.But, in the mistake of high temperature test
Cheng Zhong, easily makes portion crystal in second metal structure of wafer grow up, so that metal structure surface shape
Looks are uneven.
In order to reduce the inhomogeneities of second pattern of wafer.A kind of method is to form gold wafer second
After belonging to structure, the crystal grain of described metal structure is made to grow up by described metal structure carries out high-temperature baking
And reach stable, so that the size of metal grain is more uniform in described metal structure, and then increase described
The uniformity of metal structure surface pattern.
But, during described metal structure is carried out high-temperature baking, the temperature of described wafer is
150 DEG C～200 DEG C.The temperature of described wafer is higher, easily makes the semiconductor device of wafer first easily be subject to
The damage of high-temperature baking, so that performance of semiconductor device is affected.
For solving described technical problem, the invention provides the forming method of a kind of semiconductor structure.Please join
Examine the schematic flow sheet that Fig. 1, Fig. 1 are method for forming semiconductor structure one embodiments of the present invention, including:
Step S1, it is provided that wafer, described wafer includes relative first and second；
Step S2, forms semiconductor device described wafer first；
Step S3, carries out crude process to described wafer the second face；
Step S4, after described crude process, forms metal structure on described wafer second.
Wherein, before forming described metal structure, by chemical reagent, described wafer the second face is carried out
Crude process, described chemical reagent can react generation gas with described wafer, thus increase described wafer
The roughness of second, and then after making the described metal structure of formation, described metal structure surface is hair side,
The defect of described metal structure surface can be covered, thus improve metal structure surface pattern.Described crude
Processing procedure need not high-temperature baking, it is possible to avoid high-temperature baking to make described semiconductor device be damaged,
It is thus possible to reduce the high-temperature baking impact on described semiconductor device.Therefore, described semiconductor structure
Forming method can improve the performance of semiconductor structure.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The structural representation of the forming method one each step of embodiment of Fig. 2 to Fig. 6 semiconductor structure of the present invention.
Refer to Fig. 2, it is provided that wafer 100, described wafer 100 includes: the first relative face 101 and
Two faces 102.
Described wafer 100 first face 101 is used for forming semiconductor device；Described wafer 100 second face 102
For forming metal structure, described metal structure is for realizing the electrical connection with external circuit.
In the present embodiment, the material of described wafer 100 is silicon.In other embodiments, described wafer
Material can also be the semi-conducting materials such as germanium, SiGe, silicon-on-insulator or germanium on insulator.
Refer to Fig. 3, form semiconductor device in described wafer 100 first face 101.
In the present embodiment, described semiconductor device includes: MOS transistor, diode, triode, fin
Formula field-effect transistor or memory element etc..
Refer to Fig. 4, described wafer 100 second face 102 is carried out crude process.
Described crude process can increase the roughness in wafer 100 second face 102, so that being subsequently formed
Metal structure surface be hair side, described hair side can cover the defect of described metal structure surface, thus
Improve metal structure surface pattern, improve semiconductor structure performance.
In the present embodiment, by chemical reagent 120, described wafer 100 second face 102 is carried out crude place
Reason, described chemical reagent 120 can react with described wafer 100, and produce gas.Implement at other
In example, it is also possible to by ion sputtering, described wafer the second face is carried out described crude process.
Described chemical reagent 120 can react with described wafer 100, produces gas, and gas is easy
Make crystal column surface produce hole, so that described wafer 100 second face 102 is roughening, and then make follow-up
The metal structure surface formed forms hair side.Described hair side can cover described metal structure surface defect,
Thus reduce the inhomogeneities of the metal grain shadow to metal structure 121 outward appearance in subsequent high temperature test process
Ring.When described wafer 100 second face 102 being carried out crude process by chemical reagent, it is not necessary to high temperature
Heating such that it is able to avoid the high temperature impact on described performance of semiconductor device, and then can improve and partly lead
The performance of body structure.
In the present embodiment, the solvent of described chemical reagent 120 includes: HNO3, H2SO4And HF.Wherein,
HNO3Can react with wafer, form NO2Gas and SiO2, HF can be with SiO2Reaction is formed
SiF4And steam, thus remove SiO2, H2SO4The acid-base value of described chemical reagent can be regulated, control
Response speed.
In the present embodiment, HNO in described chemical reagent3Content be 5%～10%；H2SO4Content be
75%～85%；The content of HF is 1%～5%.
In the present embodiment, before described second face 102 being carried out crude process by chemical reagent 120,
Described forming method also includes: at described wafer 100 first face 101 bonding protective film 111.
The step that described wafer 100 second face 102 is carried out crude process includes: by described chemistry examination
Described wafer 100 is soaked in agent.
Described protecting film 111 is used for protecting described semiconductor device, reduces described chemical reagent 120 to half
The damage of conductor device.
In the present embodiment, the material of described protecting film 111 is blue film.
It should be noted that soaked in the step of described wafer 100 by described chemical reagent 120, as
Really long soaking time easily damages described semiconductor device；If soak time is too short, it is difficult to make wafer
100 second faces 102 are roughening.Concrete, in the present embodiment, described soak time is 15s～30s.
It should be noted that after the step of crude process, described forming method also includes: remove described
Protecting film 111.
In the present embodiment, the step removing described protecting film 111 includes: by protecting described in ultra violet lamp
Cuticula 111, makes described protecting film 111 depart from wafer.
In the present embodiment, described protecting film 111 is pasted onto on wafer first by glue.Described viscous
Rubberizing is the most aging under the irradiation of ultraviolet light, loses viscosity, thus easily makes protecting film and described wafer
Separate.
Refer to Fig. 5, after described crude process, described wafer 100 second face 102 forms metal
Structure 121.
Described metal structure 121 is for realizing being electrically connected of described wafer 100 second face 102 and external circuit
Connect.
It should be noted that described wafer 100 second face 102 is after described crude process, described
Two faces 102 are roughening.After being subsequently formed metal structure 121, described metal structure 121 surface is hair
Face.Crystal grain in high temperature test makes metal structure 121 is grown up, and the inhomogeneities of metal grain is not easy
Affect the outward appearance of described hair side.
In the present embodiment, described metal structure 121 includes: be positioned at the first metal layer on surface, described first
The material of metal level is silver.
Concrete, described metal structure 121 includes: be positioned at the 3rd metal in described wafer 100 second face 102
Layer；It is positioned at the second metal level of described 3rd layer on surface of metal；It is positioned at the of described second layer on surface of metal
One metal level.
Described 3rd metal level can react formation metal silicide with described wafer 100, thus increases
Bonding between metal structure 121 and wafer 100；Described second metal level and the first metal layer can increase
The electric conductivity of described metal structure 121, the resistance of reduction metal structure.
In the present embodiment, the material of described the first metal layer is silver, and the thickness of described the first metal layer is 9000
Angstrom～11000 angstroms.
In the present embodiment, the material of described second metal level is nickel, and the thickness of described second metal level is 3100
Angstrom～3900 angstroms.
In the present embodiment, the material of described 3rd metal level is titanium, and the thickness of described 3rd metal level is 900
Angstrom～1100 angstroms.
In the present embodiment, form described metal structure 121 by evaporation process.Evaporation is by thing to be filmed
Matter is placed in vacuum and is evaporated or distils, and is allowed to the process separated out at workpiece or substrate surface.At other
In embodiment, it is also possible to form described metal structure by electrochemical filming.
Concrete, in the present embodiment, on described wafer 100 second face 102, form the 3rd gold medal by evaporation
Belong to layer；The second metal level is formed at described 3rd layer on surface of metal by evaporation；By evaporation described the
Two layer on surface of metal form the first metal layer.
In the present embodiment, the technological parameter being formed the 3rd metal level by evaporation process is included: titanium atom
Sedimentation rate is 9 angstroms per second～11 angstroms per second；Wafer temperature is less than 100 DEG C.
In the present embodiment, the technological parameter being formed the second metal level by evaporation process is included: nickle atom
Sedimentation rate is 10 angstroms per second～14 angstroms per second；Wafer temperature is less than 100 DEG C.
In the present embodiment, the technological parameter being formed the first metal layer by evaporation process is included: silver atoms
Sedimentation rate is 20 angstroms per second～30 angstroms per second；Wafer temperature is less than 100 DEG C.
Refer to Fig. 6, after described formation metal structure 121, described forming method also includes: carry out height
Temperature test.
Whether described high temperature test is used for detecting described semiconductor device can at relatively high temperatures, normal work
Make.
It should be noted that the part gold during carrying out high temperature test, in described metal structure 121
Belonging to crystal grain can grow up, the size making metal grain is uneven.Owing to described metal structure 121 surface is hair side,
The inhomogeneities of metal grain size is not easy to cause the outward appearance of described metal structure 121.
In the present embodiment, the step carrying out high temperature test includes: heat described wafer 100；Test
The performance of described semiconductor device.
In the present embodiment, carrying out in the step of high temperature test, the temperature of described wafer 100 exists
110 DEG C～140 DEG C.
In the present embodiment, the time heating described wafer 100 is 1.8h～2.2h.
To sum up, in the forming method of the semiconductor structure of the present invention, before forming described metal structure,
Described wafer the second face is carried out crude process, by increasing capacitance it is possible to increase the roughness that wafer is second, so that shape
The layer on surface of metal become is hair side, it is possible to covers the defect of layer on surface of metal, improves layer on surface of metal pattern.
Additionally, described crude processing procedure need not high-temperature baking, it is possible to avoid high-temperature baking to make described partly to lead
Body device is damaged such that it is able to reduce the high-temperature baking impact on described semiconductor device.Therefore,
The forming method of described semiconductor structure can improve the performance of semiconductor structure.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (10)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided wafer, described wafer includes relative first and second；
Semiconductor device is formed described wafer first；
Described wafer the second face is carried out crude process；
After described crude process, described wafer second forms metal structure.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that to described wafer the
Two faces carry out the step of crude process and include: carry out crude by chemical reagent to described wafer the second face
Processing, described chemical reagent is for reacting with described wafer, and produces gas.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that the material of described wafer
Material is silicon；The solvent of described chemical reagent includes: HNO3, H2SO4And HF.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that described chemical reagent
Middle HNO3Mass percent concentration be 5%～10%；H2SO4Mass percent concentration be
75～85%；The mass percent concentration of HF is 1～5%.
5. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that pass through chemical reagent
Before described wafer the second face is carried out crude process, also include: formed described wafer first and protect
Cuticula；
The step that described wafer the second face is carried out crude process includes: soaked described by described chemical reagent
Wafer.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described protecting film
Material is blue film；
Before described second face is carried out crude process, also include: paste described on described wafer second
Protecting film.
7. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that by described chemistry
Reagent soaks in the step of described wafer, and soak time is 15s～30s.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form metal structure
Afterwards, described forming method also includes: carry out high temperature test, is used for detecting described semiconductor device and exists
Performance under the condition of high temperature；
Carrying out in the step of high temperature test, the temperature of described wafer is 110 DEG C～140 DEG C.
9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described metal structure
Including the first metal layer；
The material of described the first metal layer is silver；The thickness of described the first metal layer is 9000 angstroms～11000 angstroms.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form described metal
The technique of structure includes: evaporation process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610300833.9A CN105957815A (en) | 2016-05-09 | 2016-05-09 | Semiconductor structure forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610300833.9A CN105957815A (en) | 2016-05-09 | 2016-05-09 | Semiconductor structure forming method |
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| CN105957815A true CN105957815A (en) | 2016-09-21 |
Family
ID=56914102
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399196A (en) * | 2007-09-29 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Coarsening processing method for backing side of wafer |
| CN101882577A (en) * | 2009-05-06 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Roughing method of wafer backside |
| CN103451715A (en) * | 2013-01-05 | 2013-12-18 | 深圳信息职业技术学院 | Surface coarsening method of polycrystalline silicon plate |
-
2016
- 2016-05-09 CN CN201610300833.9A patent/CN105957815A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399196A (en) * | 2007-09-29 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Coarsening processing method for backing side of wafer |
| CN101882577A (en) * | 2009-05-06 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Roughing method of wafer backside |
| CN103451715A (en) * | 2013-01-05 | 2013-12-18 | 深圳信息职业技术学院 | Surface coarsening method of polycrystalline silicon plate |
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Application publication date: 20160921 |