CN105933001A - Device and method for reducing electromagnetic interference in circuit - Google Patents

Device and method for reducing electromagnetic interference in circuit Download PDF

Info

Publication number
CN105933001A
CN105933001A CN201610244194.9A CN201610244194A CN105933001A CN 105933001 A CN105933001 A CN 105933001A CN 201610244194 A CN201610244194 A CN 201610244194A CN 105933001 A CN105933001 A CN 105933001A
Authority
CN
China
Prior art keywords
random number
unit
spread spectrum
configuration
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610244194.9A
Other languages
Chinese (zh)
Other versions
CN105933001B (en
Inventor
廖裕民
顾家其
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rockchip Electronics Co Ltd
Original Assignee
Fuzhou Rockchip Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuzhou Rockchip Electronics Co Ltd filed Critical Fuzhou Rockchip Electronics Co Ltd
Priority to CN201610244194.9A priority Critical patent/CN105933001B/en
Publication of CN105933001A publication Critical patent/CN105933001A/en
Application granted granted Critical
Publication of CN105933001B publication Critical patent/CN105933001B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

The present invention provides a device and method for reducing electromagnetic interference in a circuit. The device comprises a crystal oscillator, a jitter clock generation unit, a PLL circuit, a spectrum spreading direction and scope configuration unit, a clock random number generation unit, a configuration random number generation unit, a configuration information control unit, a random seed generation unit, a high precision temperature ADC sensor, a change period configuration storage unit, a random number switch unit, a configuration information storage unit, a PLL configuration storage unit, a PLL frequency calculation unit, a frequency judgment unit, and a storage unit of frequency points with unqualified EMI. According to the invention, a configurable PLL circuit is automatically adjusted through jitter, the frequency point can be automatically detected, then the upper jitter, lower jitter, or left and right jitter of the frequency is carried out on spectrum according to the configuration to adjust a clock jitter value, an EMI problem is avoided, and thus the EMC examination is passed.

Description

A kind of reduce the device and method of electromagnetic interference in circuit
Technical field
The present invention relates to chip design field, reduce the dress of electromagnetic interference in circuit particularly to a kind of chip Put and method.
Background technology
When the clock circuit on chip works, the extreme value (spike) of pulse can produce EMI, and (electromagnetism is done Disturb), EMI (Electromagnetic Interference, electromagnetic interference), refer to pass through conducting medium Signal on one electric network is coupled (interference) and arrives another electric network, affect other system or this is The normal work of other subsystems in system.IC chip and circuit board all easily occur this feelings Condition.And EMC is exactly emc testing, target is whether the EMI that test electronic system produces exists Within certain safety range, otherwise it is assumed that the electromagnetic radiation of this electronic system exceeds standard.
PLL is the source of chip medium-high frequency clock, can produce stable clock signal for chip circuit Use.But the clock signal frequency that generally high-performance PLL produces is highly stable, so easily causes work As circuit, EMI problem occurs.Current technology cannot solve PLL and stablize the contradiction of frequency and EMI, So the present invention proposes and a kind of reduces the device and method of electromagnetic interference in circuit, by jitter (clock Shake) automatically adjust configurable PLL circuit, can automatically detect Frequency point, then according to being arranged in On frequency spectrum, frequency is upwards shaken or shakes downwards or left and right shake adjusts clock jitter value, To avoid EMI problem, thus checked by EMC.
PLL circuit is generally made up of phase discriminator, low pass filter and voltage controlled oscillator, and its signal moves towards It is: input signal → phase discriminator → low pass filter → voltage controlled oscillator → output signal.Phase discriminator has two Individual input, is the output signal of input signal and voltage controlled oscillator, at the two phase contrast and difference on the frequency respectively Be not very big in the case of, the output of phase discriminator is directly proportional to the difference of two input signals, the output of phase discriminator For analogue signal, it is considered except high frequency spurs by low pass filter, enters voltage controlled oscillator afterwards, voltage-controlled shakes The output frequency swinging device changes with the change of its input voltage.Therefore to be actually one negative for PLL circuit Feedback system, simply enters signal within normal range, and output signal can be caught up with in " in certain time ". After input signal changes, output signal follows the tracks of the process referred to as capture of input signal;Output signal Referred to as locking when following the tracks of complete;Input signal change too fast being referred to as when causing output signal to follow the tracks of, loses Lock.N frequency multiplication can be conveniently realized by PLL.
Summary of the invention
The technical problem to be solved in the present invention, be to provide a kind of device reducing electromagnetic interference in circuit and Method, is automatically adjusted configurable PLL circuit, can automatically detect frequency by jitter (clock jitter) Rate point, then according to be arranged on frequency spectrum frequency is upwards shaken or downwards shake or left and right tremble Move and adjust clock jitter value, to avoid EMI problem, thus checked by EMC.
Assembly of the invention is achieved in that and a kind of reduces the device of electromagnetic interference in circuit, including crystalline substance Oscillation body device, jitter clock generating unit, PLL circuit, spread spectrum direction and scope dispensing unit, time Clock random number generation unit, configuration random number generation unit, configuration information control unit, random seed produce Raw unit, high-precision temperature ADC sensor, period of change configuration memory cell, random number switch are single Unit, configuration information memory element, PLL configuration memory cell, PLL frequency computing unit, frequency judge Unit and EMI underproof Frequency point memory element;
Described crystal oscillator, jitter clock generating unit, PLL circuit are sequentially connected with;
Described spread spectrum direction and scope dispensing unit connect described jitter clock generating unit, configuration respectively Information control unit and frequency judging unit;
Described random seed generation unit connects described clock random number generation unit respectively and configuration is random Number generation unit;
Described period of change configuration memory cell, random number switch element, clock random number generation unit depend on Secondary it is connected to described jitter clock generating unit;
Described configuration information memory element, configuration information control unit are sequentially connected to described PLL circuit, And configuration information control unit is also connected with described configuration random number generation unit;
Described PLL configuration memory cell, PLL frequency computing unit, frequency judging unit and EMI Underproof Frequency point memory element.
Further, described PLL circuit is by phase discriminator, low pass filter, voltage controlled oscillator and feedback Loop frequency divider is sequentially connected with composition one loop, and described jitter clock generating unit connects low pass filter, Described feedback circuit frequency divider is also connected with described configuration information control unit.
The inventive method is achieved in that and a kind of reduces the method for electromagnetic interference in circuit, it is provided that this The device of electromagnetic interference in bright described minimizing circuit, and comprise the steps:
(1) after described high-precision temperature ADC sensor carries out real-time sampling and will sample chip temperature Current accurate temperature data be sent to described random seed generation unit;
After described random seed generation unit receives current accurate temperature data, through a high position block obtain with Several sons of machine are also sent to described clock random number generation unit and described configuration random number generation unit;
(2) described period of change configuration memory cell according to configuration the random number Efficient Cycle cycle to institute Stating random number switch element to be controlled, often after the reference clock cycle number of configuration, random number switchs It is effective that unit arranges random number;
(3) described clock random number generation unit having according to the random number seed received and random number Effect signal, produces clock extension compression random number, and the compression random number that extended by the clock of generation is sent to institute State jitter clock generating unit;
(4) described PLL frequency computing unit configures according to the PLL of described PLL configuration memory cell Value carries out PLL output frequency calculating, and result of calculation is sent to described frequency judging unit;By described frequency Rate judging unit according in EMI defective Frequency point memory element storage the defective Frequency point of EMI and Current PLL configuration frequency compares, when PLL configuration frequency Frequency point defective with EMI is consistent, Start described spread spectrum direction and scope dispensing unit;
Described spread spectrum direction and scope dispensing unit control jitter clock and feedback circuit divide ratio time Clock spread spectrum direction and scope, spread spectrum direction and scope are provided by EMI defective Frequency point memory element;
(5) described jitter clock generating unit is according to described clock extension compression random number and described clock Spread spectrum direction and scope, produce with jitter shake reference clock after and be sent to PLL circuit;
Described configuration information memory element is responsible for storing the feedback circuit divide ratio of original PLL circuit, And it is sent to configuration information control unit;
Described configuration information control unit according to the configuration configuration random number sent here of random number generation unit and The control of described spread spectrum direction and scope dispensing unit carries out feedback circuit divide ratio control;
Wherein, described step (1), (2) do not limit precedence relationship and before step (3), described Precedence relationship is not the most limited between step (4) and step (1), (2) or (3).
Further, described jitter clock generating unit produces the mistake of the reference clock with jitter shake Journey is as follows:
First, the random value that original reference clock is sent here according to clock random number generation unit is carried out the cycle Extending or squeeze operation, wherein, the clock cycle extends or compression depends on that described spread spectrum direction and scope are joined Put the spread spectrum direction controlling information that unit is sent here:
If spread spectrum direction controlling information is to high frequency spread spectrum, then only reference clock is done cycle compression operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, then only reference clock is done cycle extension operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, then judge according to the lowest order of random number Do cycle compression operation or cycle extension operation, owing to the lowest order of random number is random, i.e. realize Spread spectrum direction random;
Then, the cycle compression of jitter clock or the time span scope of extension also depend on described spread spectrum side To the scope control information sent here with scope dispensing unit.
Further, described configuration information control unit carries out the concrete mistake of feedback circuit divide ratio control Cheng Wei:
First, original PLL feedback circuit divide ratio is sent here according to described configuration random number generation unit Random value carries out divide ratio increase or reduces operation, and divide ratio increases or spread spectrum is depended in minimizing The spread spectrum direction controlling information that direction and scope dispensing unit are sent here:
If spread spectrum direction controlling information is to high frequency spread spectrum, only divide ratio is done increase operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, only divide ratio is done minimizing operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, according to the lowest order judgement of random number it is Do divide ratio increase and still reduce operation, owing to the lowest order of random number is random, i.e. achieve spread spectrum Direction random;
Then, the scope that divide ratio increases or reduces also depends on spread spectrum direction and scope configuration is single The scope control information that unit sends here, when the value of random number is more than range control value, only takes the scope of configuration The value that controlling value increases as divide ratio or reduces.
Present invention have the advantage that
(1) use random offset to produce circuit and produce random offset configuration, frequency upwards can be shaken Or shaking downwards or shake up and down, wherein random seed can configure, and downward shift can also be configured;
(2) Frequency point testing circuit can detect current expected frequency automatically, if Frequency point is served as reasons During the frequency of emi problem, then automatically open up jitter and produce circuit to produce spread spectrum;
(3) random offset produces circuit is to configure in decimal mode, can skew be controlled positive and negative 5% Within random value.
Accompanying drawing explanation
The present invention is further illustrated the most in conjunction with the embodiments.
Fig. 1 is that the present invention reduces the device of electromagnetic interference in circuit.
Detailed description of the invention
Referring to shown in Fig. 1, the device of electromagnetic interference in circuit that reduces of the present invention includes crystal oscillator 101, jitter clock generating unit 102, PLL circuit 103, spread spectrum direction and scope dispensing unit 104, Clock random number generation unit 105, configuration random number generation unit 106, configuration information control unit 107, The configuration storage of random seed generation unit 108, high-precision temperature ADC sensor 109, period of change Unit 110, random number switch element 111, configuration information memory element 112, PLL configuration storage is single Unit 113, PLL frequency computing unit 114, the underproof frequency of frequency judging unit 115 and EMI Point memory element 116;
Described crystal oscillator 101, jitter clock generating unit 102, PLL circuit 103 are sequentially connected with;
Described spread spectrum direction and scope dispensing unit 104 connect described jitter clock generating unit respectively 102, configuration information control unit 107 and frequency judging unit;
Described random seed generation unit 108 connects described clock random number generation unit 105 respectively and joins Put random number generation unit 106;
Described period of change configuration memory cell 110, random number switch element 111, clock random number produce Raw unit 105 is sequentially connected to described jitter clock generating unit 102;
Described configuration information memory element 112, configuration information control unit 107 are sequentially connected to described PLL circuit 103, and configuration information control unit 107 is also connected with described configuration random number generation unit 106;
Described PLL configuration memory cell 113, PLL frequency computing unit 114, frequency judging unit 115 And EMI underproof Frequency point memory element 116.
Wherein, described crystal oscillator 101 is responsible for producing the reference clock of PLL;
Described jitter clock generating unit 102 is responsible for producing according to described clock random number counting unit 105 Clock random number and the control of described spread spectrum direction and scope dispensing unit 104 carry out jitter clock product Raw, after producing the reference clock with jitter shake and be sent to the phase discriminator unit of PLL circuit 103;
Described PLL circuit 103 is by phase discriminator 1031, low pass filter 1032, voltage controlled oscillator 1033 It is sequentially connected with composition one loop, wherein feedback circuit frequency divider 1034 with feedback circuit frequency divider 1034 The frequency dividing configuration accepting configuration information control unit 107 carries out feedback division process;Described jitter clock Generation unit 102 connects low pass filter, and described feedback circuit frequency divider is also connected with described configuration information control Unit 107 processed.
Described clock random number generation unit 105 be responsible for according to described random seed generation unit 108 with Sub and the described period of change configuration memory cell 110 of machine period of change configuration control described at random Number switch element 111 carries out the generation of clock extension compression random number and random number is sent to described jitter Clock generating unit 102;Wherein, when the random switching signal of described random number switch element 111 is effective, Producing random number, during invalidating signal, random number is 0, and reference clock is not the most cycle extension compression behaviour Make;
Described period of change configuration memory cell 110 is responsible for the random number Efficient Cycle cycle according to configuration Described random number switch element 111 is controlled, often after the reference clock cycle number of configuration, with Machine number is effective, and in the reference clock cycle number of next configuration, random number is the most effective;
Described configuration random number generation unit 106 be responsible for according to described random seed generation unit 108 with Machine carries out configuring the generation of random number and random number being sent to described configuration information control unit 107;
Described high-precision temperature ADC sensor 109 is responsible for chip temperature carrying out real-time sampling and adopting Data after sample are sent to described random seed generation unit 108;
Described configuration information control unit 107 is responsible for sending here according to described configuration random number generation unit 106 Configuration random number and the control of described spread spectrum direction and scope dispensing unit 104 carry out feedback circuit and divide Frequently coefficient controls;
Described configuration information memory element 112 is responsible for the PLL feedback circuit divide ratio that storage is original, And it is sent to described configuration information control unit 107;
Described spread spectrum direction and scope dispensing unit 104 are responsible for controlling jitter clock and feedback circuit frequency dividing The clock spread spectrum direction of coefficient and scope;
Described PLL configuration memory cell 113 is responsible for storage PLL and is produced all configurations of high frequency clock;
Described PLL frequency computing unit 114 is responsible for the PLL Configuration Values according to PLL configuration memory cell Carry out PLL output frequency calculating, and result of calculation is sent to frequency judging unit;
Described frequency judging unit 115 is according to storage in EMI defective Frequency point memory element 116 The defective Frequency point of EMI and current PLL configuration frequency compare;As PLL configuration frequency and EMI When defective Frequency point is consistent, start spread spectrum direction and scope dispensing unit 104, spread spectrum direction and scope Thered is provided by EMI defective Frequency point memory element 116;
Described EMI defective Frequency point memory element 116 stores the defective Frequency point of EMI and this frequency Spread spectrum direction and scope that corresponding EMI Resolving probiems needs configure.
It addition, before the described device work reducing electromagnetic interference in circuit, need based on reducing circuit The device of middle electromagnetic interference does great many of experiments and obtains the Frequency point that EMI does not passes through, and tests the most again To make this Frequency point by EMC detect corresponding to spread spectrum direction and scope, by defective for EMI frequency Spread spectrum direction and scope configuration that the EMI Resolving probiems that point is corresponding with this frequency needs are stored in EMI and do not conform to Lattice Frequency point memory element, and random number period of change value is stored in random number period of change memory element, Then circuit work can be started.
After in the minimizing circuit of the present invention, the device of electromagnetic interference is started working, system CPU can be to PLL Circuit 103 carries out configuration makes its work, by the computing of PLL frequency computing unit 114, sentences in frequency Whether the PLL frequency that disconnected unit 115 judges configuration is the Frequency point having EMI problem, if it is not, Then PLL circuit 103 normally works, and all reference clocks and configuration are operated according to original configuration. If problem frequency, then control spread spectrum direction and scope dispensing unit 104 opened, to reference clock and Feedback circuit divide ratio carries out spread spectrum control, to reach to solve the target of EMI.
The device of electromagnetic interference in minimizing circuit based on the present invention, in the minimizing circuit of the present invention, electromagnetism is done The method disturbed, comprises the steps:
(1) described high-precision temperature ADC sensor 109 carries out real-time sampling and will adopt chip temperature Current accurate temperature data after sample are sent to described random seed generation unit 108;
After described random seed generation unit 108 receives current accurate temperature data, block through a high position To random number seed and be sent to described clock random number generation unit 105 and described configuration random number and produce Unit 106;
(2) described period of change configuration memory cell 110 is according to the random number Efficient Cycle cycle of configuration Described random number switch element 111 is controlled, often after the reference clock cycle number of configuration, with It is effective that machine number switch element 111 arranges random number;
(3) described clock random number generation unit 105 is according to the random number seed received and random number Useful signal, produce clock and extend compression random number, and the compression random number that the clock of generation extended send Toward described jitter clock generating unit 102;
(4) described PLL frequency computing unit configures according to the PLL of described PLL configuration memory cell Value carries out PLL output frequency calculating, and result of calculation is sent to described frequency judging unit;By described frequency Rate judging unit according in EMI defective Frequency point memory element storage the defective Frequency point of EMI and Current PLL configuration frequency compares, when PLL configuration frequency Frequency point defective with EMI is consistent, Start described spread spectrum direction and scope dispensing unit;
Described spread spectrum direction and scope dispensing unit control jitter clock and feedback circuit divide ratio time Clock spread spectrum direction and scope, spread spectrum direction and scope are provided by EMI defective Frequency point memory element;
(5) described jitter clock generating unit 102 extends compression random number and described according to described clock Clock spread spectrum direction and scope, produce with jitter shake reference clock after and be sent to PLL circuit 103;
Described configuration information memory element 112 is responsible for the feedback circuit of the original PLL circuit 103 of storage Divide ratio, and it is sent to configuration information control unit 107;
Described configuration information control unit 107 according to the configuration configuration sent here of random number generation unit 106 with The control of machine number and described spread spectrum direction and scope dispensing unit 104 carries out feedback circuit divide ratio control System;
Wherein, described step (1), (2) do not limit precedence relationship and before step (3), i.e. Produce to described clock random number through random number switch element 111 from period of change configuration memory cell 110 The process of unit 105 and described high-precision temperature ADC sensor 109 are through random seed generation unit 108 Extremely the process of described clock random number generation unit 105 is in no particular order, but all collects to described clock random Number generation unit 105.Elder generation is not the most limited between described step (4) and step (1), (2) or (3) Rear relation, the most described EMI monitoring unit 113 is by described spread spectrum direction and scope dispensing unit 104 Arrive the process of described jitter clock generating unit 102 with during via described after step (1) (2) Clock random number generation unit 105 arrives the process of described jitter clock generating unit 102 in no particular order.
Wherein, described jitter clock generating unit 102 produces the mistake of the reference clock with jitter shake Journey is as follows:
First, the original reference clock produced by crystal oscillator 101 is according to clock random number generation unit 105 random values sent here carry out cycle extension or squeeze operation, and wherein, the clock cycle extends or compression is depended on The spread spectrum direction controlling information sent here in described spread spectrum direction and scope dispensing unit 102:
If spread spectrum direction controlling information is to high frequency spread spectrum, then only reference clock is done cycle compression operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, then only reference clock is done cycle extension operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, then judge according to the lowest order of random number Do cycle compression operation or cycle extension operation, owing to the lowest order of random number is random, i.e. realize Spread spectrum direction random;
Then, the cycle compression of jitter clock or the time span scope of extension also depend on described spread spectrum side To the scope control information sent here with scope dispensing unit 104.
Wherein, described configuration information control unit 107 carries out the detailed process of feedback circuit divide ratio control For:
First, original PLL feedback circuit divide ratio is sent according to described configuration random number generation unit 106 The random value come carries out divide ratio increase or reduces operation, and divide ratio increase still reduces to be depended on The spread spectrum direction controlling information that spread spectrum direction and scope dispensing unit 104 are sent here:
If spread spectrum direction controlling information is to high frequency spread spectrum, only divide ratio is done increase operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, only divide ratio is done minimizing operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, according to the lowest order judgement of random number it is Do divide ratio increase and still reduce operation, owing to the lowest order of random number is random, i.e. achieve spread spectrum Direction random;
Then, the scope that divide ratio increases or reduces also depends on spread spectrum direction and scope configuration is single The scope control information that unit sends here, when the value of random number is more than range control value, only takes the scope of configuration The value that controlling value increases as divide ratio or reduces.
Although the foregoing describing the detailed description of the invention of the present invention, but it is familiar with the technology people of the art Member should be appreciated that our described specific embodiment is merely exemplary rather than for this The restriction of bright scope, those of ordinary skill in the art are in the equivalence made according to the spirit of the present invention Modify and change, all should contain in the scope of the claimed protection of the present invention.

Claims (5)

1. one kind is reduced the device of electromagnetic interference in circuit, it is characterised in that: include crystal oscillator, Jitter clock generating unit, PLL circuit, spread spectrum direction and scope dispensing unit, clock random number produce Raw unit, configuration random number generation unit, configuration information control unit, random seed generation unit, height Accurate temperature ADC sensor, period of change configuration memory cell, random number switch element, configuration letter Breath memory element, PLL configuration memory cell, PLL frequency computing unit, frequency judging unit and EMI underproof Frequency point memory element;
Described crystal oscillator, jitter clock generating unit, PLL circuit are sequentially connected with;
Described spread spectrum direction and scope dispensing unit connect described jitter clock generating unit, configuration respectively Information control unit and frequency judging unit;
Described random seed generation unit connects described clock random number generation unit respectively and configuration is random Number generation unit;
Described period of change configuration memory cell, random number switch element, clock random number generation unit depend on Secondary it is connected to described jitter clock generating unit;
Described configuration information memory element, configuration information control unit are sequentially connected to described PLL circuit, And configuration information control unit is also connected with described configuration random number generation unit;
Described PLL configuration memory cell, PLL frequency computing unit, frequency judging unit and EMI Underproof Frequency point memory element.
The most according to claim 1 a kind of reducing the device of electromagnetic interference in circuit, its feature exists In: described PLL circuit is by phase discriminator, low pass filter, voltage controlled oscillator and feedback circuit frequency divider Being sequentially connected with composition one loop, described jitter clock generating unit connects low pass filter, described feedback Loop frequency divider is also connected with described configuration information control unit.
3. one kind is reduced the method for electromagnetic interference in circuit, it is characterised in that: provide such as claim 1 Described EMI automatic regulating apparatus, and comprise the steps:
(1) after described high-precision temperature ADC sensor carries out real-time sampling and will sample chip temperature Current accurate temperature data be sent to described random seed generation unit;
After described random seed generation unit receives current accurate temperature data, through a high position block obtain with Several sons of machine are also sent to described clock random number generation unit and described configuration random number generation unit;
(2) described period of change configuration memory cell according to configuration the random number Efficient Cycle cycle to institute Stating random number switch element to be controlled, often after the reference clock cycle number of configuration, random number switchs It is effective that unit arranges random number;
(3) described clock random number generation unit having according to the random number seed received and random number Effect signal, produces clock extension compression random number, and the compression random number that extended by the clock of generation is sent to institute State jitter clock generating unit;
(4) described PLL frequency computing unit configures according to the PLL of described PLL configuration memory cell Value carries out PLL output frequency calculating, and result of calculation is sent to described frequency judging unit;By described frequency Rate judging unit according in EMI defective Frequency point memory element storage the defective Frequency point of EMI and Current PLL configuration frequency compares, when PLL configuration frequency Frequency point defective with EMI is consistent, Start described spread spectrum direction and scope dispensing unit;
Described spread spectrum direction and scope dispensing unit control jitter clock and feedback circuit divide ratio time Clock spread spectrum direction and scope, spread spectrum direction and scope are provided by EMI defective Frequency point memory element;
(5) described jitter clock generating unit is according to described clock extension compression random number and described clock Spread spectrum direction and scope, produce with jitter shake reference clock after and be sent to PLL circuit;
Described configuration information memory element is responsible for storing the feedback circuit divide ratio of original PLL circuit, And it is sent to configuration information control unit;
Described configuration information control unit according to the configuration configuration random number sent here of random number generation unit and The control of described spread spectrum direction and scope dispensing unit carries out feedback circuit divide ratio control;
Wherein, described step (1), (2) do not limit precedence relationship and before step (3), described Precedence relationship is not the most limited between step (4) and step (1), (2) or (3).
The most as claimed in claim 3 a kind of reduce the method for electromagnetic interference in circuit, it is characterised in that: The process that described jitter clock generating unit produces the reference clock with jitter shake is as follows:
First, the random value that original reference clock is sent here according to clock random number generation unit is carried out the cycle Extending or squeeze operation, wherein, the clock cycle extends or compression depends on that described spread spectrum direction and scope are joined Put the spread spectrum direction controlling information that unit is sent here:
If spread spectrum direction controlling information is to high frequency spread spectrum, then only reference clock is done cycle compression operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, then only reference clock is done cycle extension operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, then judge according to the lowest order of random number Do cycle compression operation or cycle extension operation, owing to the lowest order of random number is random, i.e. realize Spread spectrum direction random;
Then, the cycle compression of jitter clock or the time span scope of extension also depend on described spread spectrum side To the scope control information sent here with scope dispensing unit.
The most as claimed in claim 3 a kind of reduce the method for electromagnetic interference in circuit, it is characterised in that: Described configuration information control unit carries out the detailed process of feedback circuit divide ratio control:
First, original PLL feedback circuit divide ratio is sent here according to described configuration random number generation unit Random value carries out divide ratio increase or reduces operation, and divide ratio increases or spread spectrum is depended in minimizing The spread spectrum direction controlling information that direction and scope dispensing unit are sent here:
If spread spectrum direction controlling information is to high frequency spread spectrum, only divide ratio is done increase operation;
If spread spectrum direction controlling information is to low frequency spread spectrum, only divide ratio is done minimizing operation;
If spread spectrum direction controlling information is the random spread spectrum of low-and high-frequency, according to the lowest order judgement of random number it is Do divide ratio increase and still reduce operation, owing to the lowest order of random number is random, i.e. achieve spread spectrum Direction random;
Then, the scope that divide ratio increases or reduces also depends on spread spectrum direction and scope configuration is single The scope control information that unit sends here, when the value of random number is more than range control value, only takes the scope of configuration The value that controlling value increases as divide ratio or reduces.
CN201610244194.9A 2016-04-19 2016-04-19 The device and method of electromagnetic interference in a kind of reduction circuit Active CN105933001B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610244194.9A CN105933001B (en) 2016-04-19 2016-04-19 The device and method of electromagnetic interference in a kind of reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610244194.9A CN105933001B (en) 2016-04-19 2016-04-19 The device and method of electromagnetic interference in a kind of reduction circuit

Publications (2)

Publication Number Publication Date
CN105933001A true CN105933001A (en) 2016-09-07
CN105933001B CN105933001B (en) 2018-11-20

Family

ID=56838464

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610244194.9A Active CN105933001B (en) 2016-04-19 2016-04-19 The device and method of electromagnetic interference in a kind of reduction circuit

Country Status (1)

Country Link
CN (1) CN105933001B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113254A1 (en) * 2016-12-22 2018-06-28 惠科股份有限公司 Spread-spectrum decoding method for transmitted signal and display apparatus
CN109462397A (en) * 2018-11-08 2019-03-12 苏州裕太车通电子科技有限公司 A kind of reduction electromagnetic interference method
CN110214418A (en) * 2019-04-23 2019-09-06 京东方科技集团股份有限公司 Parameter determination method and device, the clock spread spectrum method and device of spread spectrum circuit
CN115065232A (en) * 2022-05-17 2022-09-16 致瞻科技(上海)有限公司 Frequency invariant spread spectrum method and spread spectrum system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404569A (en) * 2007-11-23 2009-04-08 硅谷数模半导体(北京)有限公司 Apparatus and method for frequency expansion of reference clock signal
US8433024B2 (en) * 2009-07-27 2013-04-30 National Taiwan University Spread spectrum clock generator and method for adjusting spread amount
WO2015172372A1 (en) * 2014-05-16 2015-11-19 Lattice Semiconductor Corporation Fractional-n phase locked loop circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404569A (en) * 2007-11-23 2009-04-08 硅谷数模半导体(北京)有限公司 Apparatus and method for frequency expansion of reference clock signal
US8433024B2 (en) * 2009-07-27 2013-04-30 National Taiwan University Spread spectrum clock generator and method for adjusting spread amount
WO2015172372A1 (en) * 2014-05-16 2015-11-19 Lattice Semiconductor Corporation Fractional-n phase locked loop circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113254A1 (en) * 2016-12-22 2018-06-28 惠科股份有限公司 Spread-spectrum decoding method for transmitted signal and display apparatus
CN109462397A (en) * 2018-11-08 2019-03-12 苏州裕太车通电子科技有限公司 A kind of reduction electromagnetic interference method
CN109462397B (en) * 2018-11-08 2023-01-24 裕太微电子股份有限公司 Method for reducing electromagnetic interference
CN110214418A (en) * 2019-04-23 2019-09-06 京东方科技集团股份有限公司 Parameter determination method and device, the clock spread spectrum method and device of spread spectrum circuit
CN110214418B (en) * 2019-04-23 2022-12-27 京东方科技集团股份有限公司 Parameter determination method and device of spread spectrum circuit and clock spread spectrum method and device
CN115065232A (en) * 2022-05-17 2022-09-16 致瞻科技(上海)有限公司 Frequency invariant spread spectrum method and spread spectrum system
CN115065232B (en) * 2022-05-17 2023-07-07 致瞻新能源(浙江)有限公司 Frequency-invariant spread spectrum method and spread spectrum system

Also Published As

Publication number Publication date
CN105933001B (en) 2018-11-20

Similar Documents

Publication Publication Date Title
US7737739B1 (en) Phase step clock generator
CN105933001A (en) Device and method for reducing electromagnetic interference in circuit
Mansuri et al. Jitter optimization based on phase-locked loop design parameters
US7750618B1 (en) System and method for testing a clock circuit
CN103684436B (en) Phase locked loop circuit and method of generating clock signals using the phase locked loop
CN107852133A (en) The circuit and method of clock frequency regulation are provided in response to mains voltage variations
CN104516397B (en) The method that electronic portable device carries out data processing according to the clock frequency extracted from host apparatus
CN107579723A (en) A kind of method and apparatus of calibrating clock frequency
US11853112B2 (en) Impedance measurement circuit and impedance measurement method thereof
CN101110590B (en) Method and device for phase adjustment in the course of detecting time sequence allowance
US7773667B2 (en) Pseudo asynchronous serializer deserializer (SERDES) testing
CN106253883A (en) Device and method for measuring jitter built in chip
US11888480B2 (en) Method and apparatus for synchronizing two systems
WO2020005439A1 (en) Apparatus for autonomous security and functional safety clock and voltages
EP3244224A1 (en) Integrated system and method for testing system timing margin
CN104426537A (en) Apparatus And Method For Evaluating The Performance Of System In Control Loop
CN105933000B (en) A kind of EMI automatic regulating apparatus and EMI automatic adjusting method
US6832173B1 (en) Testing circuit and method for phase-locked loop
CN103916121B (en) The circuit that frequency for controlling clock signal changes
Hsiao et al. Analog sensor based testing of phase-locked loop dynamic performance parameters
CN207399177U (en) Electronic equipment
US8040995B2 (en) Jitter detection circuit and jitter detection method
CN110198162A (en) Semiconductor devices including clock generating circuit
US20070254613A1 (en) Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)
US11329608B1 (en) Oscillator circuit with negative resistance margin testing

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China

Patentee after: Ruixin Microelectronics Co., Ltd

Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China

Patentee before: Fuzhou Rockchips Electronics Co.,Ltd.

CP01 Change in the name or title of a patent holder