CN105932045A - Superjunction structure for semiconductor element - Google Patents
Superjunction structure for semiconductor element Download PDFInfo
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- CN105932045A CN105932045A CN201610320079.5A CN201610320079A CN105932045A CN 105932045 A CN105932045 A CN 105932045A CN 201610320079 A CN201610320079 A CN 201610320079A CN 105932045 A CN105932045 A CN 105932045A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 31
- 238000000407 epitaxy Methods 0.000 claims description 7
- 150000003376 silicon Chemical class 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 25
- 239000007943 implant Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The invention relates to a superjunction structure for a semiconductor element, and the structure comprises a silicon substrate which is provided with a first conductive epitaxial layer; a plurality of high-density second conductive columns which are formed in the first conductive epitaxial layer; and a plurality of low-density second conductive side walls which are formed in the first conductive epitaxial layer and are located on the external side surfaces of the second conductive columns. The semiconductor element is a superjunction MOSFET, a superjunction MESFET, a superjunction Schottky transistor, a superjunction IGBT, a thyristor, or a superjunction diode. The invention improves the reverse withstand voltage of the superjunction structure, and is high in depth to width ratio.
Description
The application is divisional application, the Application No. of its female case: 201210568724.7, filing date: 2012
On December 25, application is artificial: energy saving component Pty Ltd, invention entitled: for quasiconductor
The super contact structure of element and processing procedure thereof.
Technical field
The present invention is a kind of semiconductor structure, the super contact structure of a kind of semiconductor element.
Background technology
In 1991 (see, for example, U.S. Patent No. 5,216,275), super connecing is proposed from doctor Chen Xingbi
After the concept in face (super junction), there are many research attempt development and promoted the super of foregoing invention
Junction effect.
Such as U.S. Patent No. 6,608,350 i.e. propose a kind of groove-shaped super junction devices, see Fig. 1, for
The schematic diagram of the groove-shaped super junction devices concept of this patent is described, this groove-shaped super junction mos device is main
Comprise substrate 81, N-type epitaxial layer 82, multiple parallel groove 83, position at parallel groove 83 sidewall
On P-type layer 84, position P substrate (base) 93 on N-type epitaxial layer 82, at two parallel grooves
Grid oxic horizon 87 between 83 and on N-type epitaxial layer 82 and grid 88, position are in P substrate 93
Source area 89 and source electrode 91, and the dielectric medium (not adding figure number) in P-type layer 84.Leading
During logical pattern, grid 88 applies a bias, and source electrode 89 is ground connection.Now in P substrate
A passage (channel) can be formed, when drain electrode applies little bias between 93 and grid oxic horizon 87
In this element, produce electric current, and the P-type layer 84 in groove 83 can provide low conducting resistance
RDSON.Among existing mos device, such as conducting resistance RDSON to be reduced, then must reduce
The resistance coefficient of N-type epitaxial layer 82, that is doping content to be increased.If but N-type epitaxial layer 82
Doping content increases, then can affect the pressure performance of this MOS element.
By above-mentioned super contact structure, high voltage endurance capability and low on-resistance can be had concurrently.But will be at N
Formed on type epitaxial layer 82 and there is the groove 83 of high-aspect-ratio be not easy to, if being therefore provided that a kind of new
Semiconductor element surpasses contact structure and processing procedure thereof, to improve prior art shortcoming, is i.e. very beneficial for super junction
The making of device.
Summary of the invention
In order to overcome prior art problem, a purpose of the present invention can further improve the most resistance to for providing one
Press and can make the super contact structure for semiconductor element of high-aspect-ratio.
In order to reach the object of the invention, the present invention provides a kind of super contact structure for semiconductor element, bag
Contain: a silicon substrate, this silicon substrate has one first conductivity type epitaxial layer；Multiple high concentration the second conductivity types
Post, is formed in this first conductivity type epitaxial layer；And multiple low concentration the second conductivity type sidewall, it is formed at this
First conductivity type epitaxial layer is interior and is positioned on the lateral surface of this second conductivity type post；Wherein first in this first conduction
On type epitaxial layer successively epitaxy grow up multiple low doping concentration the first conductivity type epitaxial layer cover layer, each low-mix
Miscellaneous concentration the first conductivity type epitaxial layer cover layer has multiple high concentration the second conduction type ion implantation area, and many
Individual respectively at low concentration the second conduction type ion cloth on side, each high concentration the second conduction type ion implantation area
Plant district；Step is driven in form aforesaid multiple high concentration the second conductivity type posts and multiple low concentration by ion
Second conductivity type sidewall.
Above-mentioned semiconductor element is super junction MOSFET, super junction MESFET, super junction Schottky
Transistor, super junction IGBT, thyristor (thyristor) or super junction rectifier.
Accompanying drawing explanation
This case must by following graphic and explanation, in order to one deeper into understanding:
Fig. 1 is the groove-shaped super junction devices side view of prior art；
Fig. 2 A to Fig. 2 D is the top view of explanation first embodiment of the invention；
Fig. 3 A to Fig. 3 F is the side view of explanation first embodiment of the invention；
Fig. 4 A to Fig. 4 D is the top view of explanation second embodiment of the invention；
Fig. 5 A to Fig. 5 F is the side view of explanation second embodiment of the invention；
Fig. 6 A to Fig. 6 D is the top view of explanation third embodiment of the invention；
Fig. 7 A to Fig. 7 F is the side view of explanation third embodiment of the invention.
Wherein, reference:
[existing]
Substrate 81
N-type epitaxial layer 82
Parallel groove 83
P-type layer 84
Grid oxic horizon 87
Grid 88
Source area 89
Source electrode 91
P substrate 93
[present invention]
Substrate 20
High-dopant concentration N-type silicon substrate 201
Low doping concentration N-type epitaxial layer 202
Low doping concentration p-type epitaxial layer 203
First photoresist layer 210
Outside photoresistance 211
Central point photoresistance 212
Mask layer 220
Outside mask layer 221
Central point mask layer 222
Breach 223
High concentration p-type ion implantation area 30
Low concentration p-type ion implantation area 32
High concentration p-type post 34
Low concentration p-type sidewall 36
High concentration N-type ion implantation area 40
Low concentration N-type ion implantation area 42
High concentration N-type post 44
Low concentration N-type sidewall 46
Field oxide 60
Detailed description of the invention
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as to the present invention's
Limit.
Referring to Fig. 2 A and Fig. 3 A, it is explanation this case for the of the super junction processing procedure of semiconductor element
One preferred embodiments step top view and side view.As shown in Figure 3A, first, it is provided that a substrate 20,
This substrate 20 is that a high-dopant concentration N-type silicon substrate 201 (N+ silicon substrate) is built with a low doping concentration N-type
Crystal layer 202 (N-epitaxial layer) is constituted.Low doping concentration N-type epitaxial layer 202 depicted in this figure with
Higher-doped concentration N-type silicon substrate 201 has approximate thickness, but this figure of notice is only schematically illustrate to be sent out
Bright instantiation, in actual element, low doping concentration N-type epitaxial layer 202 should compare actually
Higher-doped concentration N-type silicon substrate 201 thin.Subsequently by oxidation process shape on this substrate 20
Become a mask layer (non-label, such as one field oxide)；Then walk with photoresistance cloth shape on this first mask layer
Rapid formation one first photoresist layer 210.Seeing shown in Fig. 2 A and Fig. 3 A again, this first photoresist layer 210 wraps
Containing external side light resistance layer 211 and central point photoresist layer 212, with at external side light resistance layer 211 and central point photoresist layer
Ring-shaped groove (non-label) is defined between 212.At the groove shown in this notice Fig. 2 A and Fig. 3 A only
For example, effect of any close-shaped groove (such as tetragon and ellipse) all attainable cost cases.
Subsequently with this first photoresist layer 210 for mask to etch for this mask layer, to be formed as shown in Figure 3A
Mask layer 220 (comprising outside mask layer 221 and central point mask layer 222).Subsequently on resulting structures
High concentration p-type ion implant is carried out as mask with these photoresist layers 211,212, such as can be with implant concentration
It is 1013cm-3Boron ion on low doping concentration N-type epitaxial layer 202, i.e. formed as shown in Figure 3A
Structure, wherein this structure has high concentration p-type ion implantation area 30.
Subsequently as shown in Fig. 2 B and Fig. 3 B, utilize the first photoresist layer 210 as mask, under it
Mask layer 220 carries out isotropic etching (isotropic etching), such as, can use buffer oxide etch
Agent (buffered oxide etchant, BOE) carries out isotropic etching for the mask layer 220 for field oxide,
Form breach 223 inwardly to be pushed away by mask layer 220, that is remove the part mask under this photoresist layer 210
Layer 220 periphery part, makes portions of light resistance layer 210 unsettled.
The most as shown in Figure 3 C, after removing the first photoresist layer 210, i.e. available BOE again
Processing procedure, and control etch-rate, to be removed by central point mask layer 222.Now, as shown in Figure 2 C,
On the surface of resulting structures, the person of staying is mask layer 220 (it only comprises outside mask layer 221).
Subsequently as shown in Fig. 2 D and Fig. 3 D, resulting structures carry out low with this mask layer 220 for mask
The p-type ion implant of concentration, and control ion implant depth, with in high concentration p-type ion implantation area 30
Side form low concentration p-type ion implantation area 32, remove remaining mask layer 220 subsequently, and tie in gained
On structure, epitaxy is grown up low doping concentration N-type epitaxial layer cover layer (the most graphic) again.
The most as shown in FIGURE 3 E, (such as can carry out if Fig. 3 A is to figure after above-mentioned steps is repeated
Step 6 shown in 3D time), multilamellar high concentration p-type ion implantation area 30 as shown and low dense can be formed
Degree p-type ion implantation area 32 structure.
The most as illustrated in Figure 3 F, resulting structures forms a field oxide 60, and carry out ion and drive in step
Suddenly (drive in), so that the p-type ion implantation area 30 of levels and 32 points, low concentration p-type ion implantation area
It is not vertically connected with together, to form high concentration p-type post 34 as shown in this figure and low concentration p-type sidewall
36, i.e. can make follow-up semiconductor element based on this structure, such as super junction MOSFET, surpass
Junction MESFET, super junction Schottky transistor, super junction IGBT, thyristor (thyristor) and
Super junction rectifier.
Furthermore, as illustrated in Figure 3 F, owing to high concentration p-type post 34 can be by low concentration p-type sidewall 36 conduct
And the cushion between low doping concentration N-type epitaxial layer 202, therefore can improve made unit further
Part the most pressure.
As shown in Fig. 4 A and Fig. 5 A, for illustrating that this case is used for the second of the super junction processing procedure of semiconductor element
Preferred embodiments step top view and side view.As shown in Figure 5A, first, it is provided that a substrate 20, should
Substrate 20 is a high-dopant concentration N-type silicon substrate 201 (N+ silicon substrate) and a low doping concentration N-type epitaxy
Layer 202 (N-epitaxial layer) are constituted.On this substrate 20, a mask layer is formed (not subsequently by an oxidation process
Label, such as one field oxide)；Then on this first mask layer, one first is formed with photoresistance cloth shape step
Photoresist layer 210.Seeing shown in Fig. 4 A and Fig. 5 A again, it is circular empty that this first photoresist layer 210 defines one
Heart groove (non-label).
It is only example, any close-shaped groove (example at the groove shown in this notice Fig. 4 A and Fig. 5 A
Such as tetragon and ellipse) effect of all attainable cost cases.Subsequently with this first photoresist layer 210 as mask
To etch for this first mask layer, to form mask layer 220 as shown in Figure 5A.Tie at gained subsequently
Carry out high concentration p-type ion implant using this photoresist layer 210 as mask on structure, such as, can be with implant concentration
1013cm-3Boron ion on low doping concentration N-type epitaxial layer 202, i.e. formed as shown in Figure 5A
Structure, wherein this structure has high concentration p-type ion implantation area 30.
Subsequently as shown in Fig. 4 B and Fig. 5 B, utilize the first photoresist layer 210 as mask, under it
Mask layer 220 carries out isotropic etching (isotropic etching), such as, can use buffer oxide etch
Agent (buffered oxide etchant, BOE) carries out isotropic etching for the mask layer 220 for field oxide,
Form breach 223 inwardly to be pushed away by mask layer 220, that is remove the part mask under this photoresist layer 210
Layer 220 periphery part, makes portions of light resistance layer 210 unsettled.
Subsequently as shown in Fig. 4 C and Fig. 5 C, after removing the first photoresist layer 210, carry out the most again
BOE processing procedure, to remove mask layer 220 surface impurity, now the upper surface of resulting structures is mask layer 220.
The most as shown in Figure 5 D, resulting structures is carried out the p-type of low concentration with mask layer 220 for mask
Ion implant, and control ion implant depth, formed low with the side in high concentration p-type ion implantation area 30
Concentration of P type ion implantation area 32, removes remaining mask layer 220, and epitaxy again on resulting structures subsequently
Grow up low doping concentration N-type epitaxial layer cover layer (the most graphic).
The most as shown in fig. 5e, (such as can carry out if Fig. 5 A is to figure after above-mentioned steps is repeated
Step 6 shown in 5D time), multilamellar high concentration p-type ion implantation area 30 as shown and low dense can be formed
Degree p-type ion implantation area 32 structure.
The most as illustrated in figure 5f, resulting structures forms a field oxide 60, and carry out ion and drive in step
Suddenly (drive in), so that the p-type ion implantation area 30 of levels and 32 points, low concentration p-type ion implantation area
It is not vertically connected with together, to form high concentration p-type post 34 as shown in this figure and low concentration p-type sidewall
36, i.e. can make follow-up semiconductor element based on this structure, such as super junction MOSFET, surpass
Junction MESFET, super junction Schottky transistor, super junction IGBT, thyristor (thyristor) and
Super junction rectifier.
As shown in Fig. 6 A and Fig. 7 A, for illustrating that this case is used for the 3rd of the super junction processing procedure of semiconductor element
Preferred embodiments step top view and side view.As shown in Figure 7 A, first, it is provided that a substrate 20, should
Substrate 20 is a high-dopant concentration N-type silicon substrate 201 (N+ silicon substrate) and a low doping concentration N-type epitaxy
Layer 202 (N-epitaxial layer) are constituted.Carry out a low doping concentration p-type epitaxial layer processing procedure subsequently, with at low-mix
A low doping concentration p-type epitaxial layer 203 is formed on miscellaneous concentration N-type epitaxial layer 202.Subsequently by an oxidation
Processing procedure forms a mask layer (non-label, such as one oxidation on this low doping concentration p-type epitaxial layer 203
Layer)；Then on this mask layer, one first photoresist layer 210 is formed with photoresistance cloth shape step.See Fig. 6 A again
Shown in, this first photoresist layer 210 can be such as a circular pattern.At the first light shown in this notice Fig. 6 A
Resistance layer 210 is only example, and this first photoresist layer 210 is alternatively other closed pattern (such as tetragon and ellipse
Circular) effect of all attainable cost cases.Subsequently with this first photoresist layer 210 for mask with for this mask
Layer etching, to form mask layer 220 as shown in Figure 7 A.Subsequently with photoresist layer 210 on resulting structures
High concentration N-type ion implant is carried out for mask, such as can be with implant concentration for 1013cm-3Phosphonium ion in low
Doping content p-type epitaxial layer 203, i.e. forms structure as shown in Figure 7 A, and wherein this structure has highly concentrated
Degree N-type ion implantation area 40.
Subsequently as shown in Fig. 6 B and Fig. 7 B, utilize the first photoresist layer 210 as mask, under it
Mask layer 220 carries out isotropic etching (isotropic etching), such as, can use buffer oxide etch
Agent (buffered oxide etchant, BOE) carries out isotropic etching for the mask layer 220 for field oxide,
Form breach 223 inwardly to be pushed away by mask layer 220, that is remove the part mask under this photoresist layer 210
Layer 220 periphery part, makes portions of light resistance layer unsettled.
Subsequently as shown in Fig. 6 C and Fig. 7 C, after removing the first photoresist layer 210, carry out the most again
BOE processing procedure, to remove mask layer 220 surface impurity, now the upper surface of resulting structures is mask layer 220.
The most as illustrated in fig. 7d, resulting structures is carried out the N-type of low concentration with mask layer 220 for mask
Ion implant, and control ion implant depth, formed low with the side in high concentration N-type ion implantation area 40
Concentration N-type ion implantation area 42, removes remaining first mask layer 220 subsequently, and on resulting structures
Epitaxy is grown up low doping concentration p-type epitaxial layer cover layer (the most graphic) again.
The most as seen in figure 7e, (such as can carry out if Fig. 7 A is to figure after above-mentioned steps is repeated
Step 6 shown in 7D time), multilamellar high concentration N-type ion implantation area 40 as shown and low can be formed
Concentration N-type ion implantation area 42 structure.
The most as shown in Figure 7 F, resulting structures forms a field oxide 60, and carry out ion and drive in step
Suddenly (drive in), so that the N-type ion implantation area 40 of levels and low concentration N-type ion implantation area 42
It is vertically connected with together respectively, to form high concentration N-type post 44 as shown in this figure and low concentration N-type side
Wall 46, i.e. can make follow-up semiconductor element based on this structure, as super junction MOSFET,
Super junction MESFET, super junction Schottky transistor, super junction IGBT, thyristor (thyristor),
And super junction rectifier.
In sum, although the present invention is disclosed above with preferred embodiment, and so it is not limited to this
Bright, any be familiar with this those skilled in the art, without departing from the spirit and scope of the present invention, when can make various change with
Retouching, therefore protection scope of the present invention is when being as the criterion depending on the defined person of appended claims.
Claims (6)
1. the super contact structure for semiconductor element, it is characterised in that comprise:
One silicon substrate, this silicon substrate has one first conductivity type epitaxial layer；
Multiple high concentration the second conductivity type post, is formed in this first conductivity type epitaxial layer；And
Multiple low concentration the second conductivity type sidewall, be formed in this first conductivity type epitaxial layer and be positioned at this second
On the lateral surface of conductivity type post,
Wherein first on this first conductivity type epitaxial layer successively epitaxy multiple low doping concentrations first of growing up conduct electricity
Type epitaxial layer cover layer, each low doping concentration the first conductivity type epitaxial layer cover layer has multiple high concentration
Two conduction type ion implantation areas, and multiple respectively on side, each high concentration the second conduction type ion implantation area
Low concentration the second conduction type ion implantation area；
Step is driven in form aforesaid multiple high concentration the second conductivity type posts and multiple low concentration by ion
Second conductivity type sidewall.
Super contact structure for semiconductor element the most according to claim 1, it is characterised in that first
Conductivity type is N-type, and the second conductivity type is p-type.
Super contact structure for semiconductor element the most according to claim 1, it is characterised in that first
Conductivity type is p-type, and the second conductivity type is N-type.
Super contact structure for semiconductor element the most according to claim 1, it is characterised in that should be partly
Conductor element is super junction MOSFET, super junction MESFET, super junction Schottky transistor, surpasses
Junction IGBT, thyristor or super junction rectifier.
Super contact structure for semiconductor subassembly the most according to claim 1, it is characterised in that this height
The ion concentration of concentration the second conduction type ion implantation area is 1013cm-3。
Super contact structure for semiconductor subassembly the most according to claim 1, it is characterised in that multiple
High concentration the second conductivity type post has identical doping content along depth direction.
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| CN201610320079.5A CN105932045B (en) | 2012-12-25 | 2012-12-25 | Super contact structure for semiconductor element |
| CN201210568724.7A CN103903965B (en) | 2012-12-25 | 2012-12-25 | Super contact structure processing procedure for semiconductor element |
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| CN1436372A (en) * | 2001-02-21 | 2003-08-13 | 三菱电机株式会社 | Semiconductor device and method of mfg. same |
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| DE59711481D1 (en) * | 1996-02-05 | 2004-05-06 | Infineon Technologies Ag | Semiconductor component controllable by field effect |
| JP2001119022A (en) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
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| CN103903965A (en) | 2014-07-02 |
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