CN105931540A - FPGA-based on-line experiment system and on-line experiment method - Google Patents
FPGA-based on-line experiment system and on-line experiment method Download PDFInfo
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- CN105931540A CN105931540A CN201610268765.2A CN201610268765A CN105931540A CN 105931540 A CN105931540 A CN 105931540A CN 201610268765 A CN201610268765 A CN 201610268765A CN 105931540 A CN105931540 A CN 105931540A
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- G09B23/183—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits
- G09B23/186—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits for digital electronics; for computers, e.g. microprocessors
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Abstract
The invention provides an FPGA-based on-line experiment system and an on-line experiment method. The system comprises a client, an upper computer, a master board FPGA and a slave board FPGA. The upper computer is connected with the client and the master board FPGA; 110 pins of the master board FPGA are connected with 110 pins of the slave board FPGA through a connector respectively; and the master board FPGA leads out, through an I/O pin, 87 wires, which are connected to a bonding pad and are connected with 87 fly wires led out from the slave board FPGA. The experiment method is characterized in that a user submits a downloading request or an operating command to the upper computer; for the downloading request, the master board FPGA enables a downloading file to be burned into the slave board FPGA through the 110 pins, and thus remote downloading of a target file is realized; for the operating command, the master board FPGA simulates high/low level to drive the slave board FPGA through bonding pad fly wires, and thus online debugging and on-line operation of the slave board FPGA are realized; and finally, the master board FPGA continuously monitors an output device of the slave board FPGA, and feeds back experiment result to the client in real time through the upper computer. Hardware experiment development is not limited by equipment, site and time, and utilization rate of experiment equipment is improved.
Description
Technical field
The present invention relates to tele-control system field, a kind of online experiment system based on FPGA and online experiment method.
Background technology
At present, in teaching field, student is carried out with FPGA (Field-Programmable Gate Array) as main representative
Programming device exploitation experiment time, generally require everyone and be equipped with a programming device and related commissioning equipment, carry out this locality
Experiment, thus the number of devices causing needs to be bought is huge；Simultaneously as the debugging of hardware generally requires substantial amounts of experimental period,
Cause the experiment based on hardware development owing to being restricted with number of devices by class hour, it is impossible to carry out quick hardware at any time real
Test, eventually result in and be difficult to reach experiment expection；
To sum up reason, it would be highly desirable to develop a kind of online experiment system based on programming device, is possible not only to save hardware cost, and
And the demand that student uses whenever and wherever possible can be met, no longer it is limited only to the class period, the most also can reduce simultaneously
Equipment loss.
Summary of the invention
The present invention is directed to the problems referred to above, in order to realize remote download and the on-line debugging of file destination, more preferable observation experiment result,
Provide a kind of online experiment system based on FPGA and online experiment method.
Online experiment system of based on FPGA, including client, host computer, mainboard FPGA and from plate FPGA, wherein
Mainboard FPGA is as access controller, from plate FPGA as experimental facilities；Mainboard FPGA and all using from plate FPGA
The medium that UART serial ports exchanges as data；
Host computer passes through network-in-dialing client, is simultaneously connected with 2 UART serial interfaces of mainboard FPGA；Use connector
110 pins of mainboard FPGA are connected with the 110 pin pins from plate FPGA respectively by 36 lines, thus realize from plate
The download programming of FPGA and on-line operation；Meanwhile, mainboard FPGA draws 87 lines by I/O pin and is connected to pad, from
Plate FPGA draws 87 fly lines and is also connected to pad, will be connected with mainboard FPGA from the I/O equipment of plate FPGA by pad.
Comprise from the 110 pin pins of plate FPGA: 4 pins that 32 DATA pins, clock are relevant, VGA are relevant
33 pins, 4 relevant for PS2 pins, 6 pins of external key, 4 relevant for JTAG pins, FPGA programmings
Mode is correlated with the lines such as DONE, FPGA_DO, FPGA_DI 27 pins totally.
Include from 87 fly lines of plate FPGA: 32 lines that 32 toggle switch are corresponding and 6 lines one corresponding to 6 buttons
Rise as the input equipment from plate FPGA；16 lines corresponding to 16 LED, 33 line conducts that 9 charactrons are corresponding
Output equipment from plate FPGA；
Comprise 1 crystal oscillator on mainboard FPGA, the frequency dividing circuit of mainboard FPGA the clock provided crystal oscillator carries out accurate division,
It is connected with from plate FPGA by 4 different holding wires, provides 1Hz, 1KHz, 75KHz, 12MHz to from plate FPGA interface
Four kinds of standard clock signals.
Include from plate FPGA: 2 UART interface, 2 PS2 interfaces, 1 USB interface, buzzer and CF card；
Being connected with PC from 2 UART interface of plate FPGA, 2 PS2 interfaces connect keyboard and mouse respectively, and VGA connects
Mouth connects display, and the I/O interface provided from plate FPGA all does experiment use.
A kind of online experiment method based on FPGA, specifically comprises the following steps that
Step one, user use the time of online experiment system in client reservation；
User logs in individual's account in client, submits the reservation application of experimental facilities to, by the client software experiment arrangement time,
And reservation result is fed back to user.
Free time experimental facilities is distributed to user by step 2, host computer, user by client to host computer submit to download request or
Person's operational order；
What step 3, host computer judged that user sends is the request of downloading or operational order, if downloading request, uploads download
File also enters step 4, otherwise enters step 6；
Step 4, host computer according to download request to mainboard FPGA send download command, and by UART serial ports automatically will under
Published article part is transferred to mainboard FPGA.
After step 5, mainboard FPGA resolve download command, download file is stored in internal storage RAM, and passes through
110 pin pins will download burning file to from plate FPGA, it is achieved the remote download of file destination, enter step 8；
Operational order is transferred to mainboard FPGA by UART serial ports by step 6, host computer；
Step 7, mainboard FPGA resolve after operational order, simulation low and high level by pad fly line drive from plate FPGA defeated
Enter equipment, to realize the on-line debugging from plate FPGA and on-line operation；
Mainboard FPGA resolves host computer operational order simulation low and high level, and then produces different control excitations to from plate FPGA
Signal, by fly line pad driver from 32 toggle switch of plate FPGA and 6 buttons, it is achieved user's on-line operation switch and
Button.
Step 8, mainboard FPGA persistently monitor the output equipment from plate FPGA, and utilize internal register record output signal
Level change, signal intensity situation is fed back to host computer.
Step 9, host computer are by being sent to client process from the output result of plate FPGA by network, anti-to client in real time
Feedback experimental result.
Step 10, distribute to after the experimental period of user exhausts, send reset command to mainboard FPGA and drive from plate when host computer
FPGA resets, and is used the order of authority to client transmission this user of stopping by network.
It is an advantage of the current invention that:
1, a kind of online experiment system based on FPGA, the most any place can be carried out experimental teaching, and hardware is real
Test exploitation not limited by equipment, place and time, and be conducive to improving the utilization rate of experimental facilities, reduce experiment
The spoilage of equipment.
2, a kind of online experiment system based on FPGA, uses two pieces of FPGA of master-slave mode to work in coordination with and builds, wherein mainboard FPGA
Can constantly upgrade, constantly revise, by mainboard FPGA is programmed, control model of freely upgrading, reduce to a certain extent
Device upgrade and the cost of maintenance.
3, a kind of online experiment system based on FPGA, two pieces of FPGA for each master-slave mode are equipped with a host computer, and
Use UART and fly line to be transmitted, improve transfer rate to a certain extent, it is achieved that monitoring in real time is tested with on-line debugging
The mesh ground of equipment.
4, a kind of online experiment system based on FPGA, client software and the collaborative use of host computer so that user can have
There is abundant control model, and obtain real-time result feedback information.
5, a kind of online experiment method based on FPGA, student downloads and after operational order by sending to host computer, mainboard
FPGA simulation corresponding signal controls to drive, and encourages analog and digital signal to from plate FPGA, more convenient, more automatically control
From plate so that student can also carry out hardware development on the premise of not knowing about these physical characteristics.
Accompanying drawing explanation
Fig. 1 is a kind of online experiment system connection figure based on FPGA of the present invention；
Fig. 2 is mainboard FPGA of the present invention and the attachment structure schematic diagram from plate FPGA；
Fig. 3 is online experiment system connection figure in the specific embodiment of the invention；
Fig. 4 is mainboard FPGA of the present invention and the first width connection circuit diagram from plate FPGA；
Fig. 5 is mainboard FPGA of the present invention and the second width connection circuit diagram from plate FPGA；
Fig. 6 is mainboard FPGA of the present invention and the 3rd width connection circuit diagram from plate FPGA；
Fig. 7 is mainboard FPGA of the present invention and the 4th width connection circuit diagram from plate FPGA；
Fig. 8 is a kind of online experiment method flow diagram based on FPGA of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is described in further detail.
A kind of online experiment system based on FPGA of the present invention and online experiment method, online experiment system is double based on master-slave mode
The logical construction of FPGA, between host computer and mainboard FPGA by serial ports exchange data, resolved by mainboard FPGA, to from
Plate FPGA is downloaded, drives input, reset etc. to control, and experimental result is fed back to host computer；Lead between master/slave board FPGA
Cross fly line to connect, it is achieved the download of file destination, the driving of input equipment, the monitoring of output equipment.
Present invention online experiment based on FPGA system, as it is shown in figure 1, include: client, host computer, mainboard FPGA
With from plate FPGA.
Client is the software of independent development, by network connect host computer, have experiment reservation, download online, on-line debugging,
The functions such as data echo.
Host computer is the PC of any connected network, and major function is to send associative operation order by serial ports to mainboard FPGA.
Additionally, host computer is also equipped with timer, it is used for calculating the experimental period of user's reservation, after the time exhausts, to mainboard FPGA
Send reset command to drive from plate FPGA reset.
Mainboard FPGA, as access controller, uses as experimental facilities from plate FPGA；Mainboard and all use 2 UART from plate
The medium that serial ports exchanges as data；
As in figure 2 it is shown, the UART serial interface of mainboard FPGA is used for connecting host computer, the data sent from mainboard are passed through
After the conversion of UART-USB converter, by the data of USB interface feedback host computer command request.Mainboard FPGA comprises
The control system of complete serial ports controller, be used for resolve host computer request, debugging etc. order and feed back correct data to
Host computer；
Mainboard FPGA also comprises 1 crystal oscillator, mainboard FPGA the clock provided crystal oscillator divides, by 4 differences
Holding wire be connected with from plate FPGA, tetra-kinds of standard time clocks of 1Hz, 1KHz, 75KHz, 12MHz letter can be provided to from plate
Number.
Being connected with PC from the UART interface of plate FPGA, 2 PS2 interfaces connect keyboard and mouse respectively, and USB interface connects
Display, the I/O interface provided from plate FPGA all does experiment use, additionally, also include buzzer and CF card from plate FPGA；
Mainboard FPGA and as follows from the annexation of plate FPGA:
Mainboard FPGA uses 36 lines 110 pins of extraction to be connected by connector with 110 pins from plate FPGA respectively,
Realize downloading programming and the function of on-line debugging to from plate FPGA by these 110 pins.
Comprise from 110 pins of plate FPGA: 4 pins (SELECT0) that 32 DATA pins, clock are relevant,
33 pins (each 10 pins of RGB) relevant for VGA, 4 relevant for PS2 pins, 6 pins of external key,
Relevant for JTAG 4 pins, FPGA programming mode be correlated with the lines such as DONE, FPGA_DO, FPGA_DI totally 27 draw
Pin.
As shown in Figure 4, it is connected from the pin IO_L1P_HSWAPEN_0 of the pin C4 of plate FPGA and mainboard FPGA,
Be connected from the pin IO_L1N_VREF_0 of the pin A4 of plate FPGA and mainboard FPGA, from the pin B5 of plate FPGA with
The pin IO_L2P_0 of mainboard FPGA is connected, from the pin IO_L3P_0 phase of the pin D5 of plate FPGA and mainboard FPGA
Even, it is connected from the pin IO_L3N_0 of the pin C5 of plate FPGA and mainboard FPGA, from pin B6 and the master of plate FPGA
The pin IO_L4P_0 of plate FPGA is connected, and is connected from the pin IO_L4N_0 of the pin A6 of plate FPGA and mainboard FPGA,
From the pin IO_L5P_0 of the pin F7 of plate FPGA and mainboard FPGA even, from the pin E6 of plate FPGA and mainboard FPGA
Pin IO_L5N_0 be connected, be connected, from plate from the pin IO_L6P_0 of the pin C7 of plate FPGA and mainboard FPGA
The pin IO_L6N_0 of the pin A7 and mainboard FPGA of FPGA is connected, from the pin D6 of plate FPGA and mainboard FPGA
Pin IO_L7P_0 be connected, be connected, from plate from the pin IO_L7N_0 of the pin C6 of plate FPGA and mainboard FPGA
The pin IO_L33P_0 of the pin B8 and mainboard FPGA of FPGA is connected, from the pin A8 of plate FPGA and mainboard FPGA
Pin IO_L33N_0 be connected, from the pin IO_L34P_GCLK19_0 of the pin C9 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L34N_GCLK18_0 of the pin A9 of plate FPGA and mainboard FPGA, from plate FPGA's
The pin IO_L35P_GCLK17_0 of pin B10 and mainboard FPGA is connected, from the pin A10 of plate FPGA and mainboard FPGA
Pin IO_L35N_GCLK16_0 be connected, from the pin of the pin E7 of plate FPGA Yu mainboard FPGA
IO_L36P_GCLK15_0 is connected, from the pin IO_L36N_GCLK14_0 of the pin E8 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L37P_GCLK13_0 of the pin E10 of plate FPGA and mainboard FPGA, from plate FPGA
The pin IO_L37N_GCLK12_0 of pin C10 and mainboard FPGA be connected, from pin D8 and the mainboard of plate FPGA
The pin IO_L38P_0 of FPGA is connected, from the pin IO_L38N_VREF_0 of the pin C8 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L39P_0 of the pin C11 of plate FPGA and mainboard FPGA, from the pin A11 of plate FPGA
It is connected with the pin IO_L39N_0 of mainboard FPGA, from the pin IO_L40P_0 of the pin F9 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L40N_0 of the pin D9 of plate FPGA and mainboard FPGA, from the pin B12 of plate FPGA
It is connected with the pin IO_L62P_0 of mainboard FPGA, from the pin of the pin A12 of plate FPGA Yu mainboard FPGA
IO_L62N_VREF_0 is connected, and is connected from the pin IO_L63P_SCP7_0 of the pin C13 of plate FPGA and mainboard FPGA,
It is connected from the pin IO_L63N_SCP6_0 of the pin A13 of plate FPGA and mainboard FPGA, from the pin F10 of plate FPGA
It is connected with the pin IO_L64P_SCP5_0 of mainboard FPGA, from the pin of the pin E11 of plate FPGA Yu mainboard FPGA
IO_L64N_SCP4_0 is connected, and is connected from the pin IO_L64P_SCP3_0 of the pin B14 of plate FPGA and mainboard FPGA,
It is connected from the pin IO_L64N_SCP2_0 of the pin A14 of plate FPGA and mainboard FPGA, from the pin D11 of plate FPGA
It is connected with the pin IO_L64P_SCP1_0 of mainboard FPGA, from the pin of the pin D12 of plate FPGA Yu mainboard FPGA
IO_L64N_SCP0_0 is connected, and is connected from the pin TCK of the pin C14 of plate FPGA and mainboard FPGA, from plate FPGA
The pin TDI of pin C12 and mainboard FPGA be connected, from the pin TMS of the pin A15 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin TDO of the pin E14 of plate FPGA and mainboard FPGA；
As it is shown in figure 5, be connected from the pin IO_L1P_A25_1 of the pin E13 of plate FPGA and mainboard FPGA, from plate FPGA
The pin IO_L1N_A24_VREF_1 of pin E12 and mainboard FPGA be connected, from pin B15 and the mainboard of plate FPGA
The pin IO_L29P_A23_M1A13_1 of FPGA is connected, from the pin of the pin B16 of plate FPGA Yu mainboard FPGA
IO_L29N_A22_M1A14_1 is connected, from the pin of the pin F12 of plate FPGA Yu mainboard FPGA
IO_L30P_A21_M1RESET_1 is connected, from the pin of the pin G11 of plate FPGA Yu mainboard FPGA
IO_L30N_A20_M1A11_1 is connected, from the pin of the pin D14 of plate FPGA Yu mainboard FPGA
IO_L31P_A19_M1CKE_1 is connected, from the pin of the pin D16 of plate FPGA Yu mainboard FPGA
IO_L31N_A18_M1A12_1 is connected, from the pin of the pin F13 of plate FPGA Yu mainboard FPGA
IO_L32P_A17_M1A8_1 is connected, from the pin of the pin F14 of plate FPGA Yu mainboard FPGA
IO_L32N_A16_M1A9_1 is connected, from the pin of the pin C15 of plate FPGA Yu mainboard FPGA
IO_L33P_A15_M1A10_1 is connected, from the pin of the pin C16 of plate FPGA Yu mainboard FPGA
IO_L33N_A14_M1A4_1 is connected, from the pin of the pin E15 of plate FPGA Yu mainboard FPGA
IO_L34P_A13_M1WE_1 is connected, from the pin of the pin E16 of plate FPGA Yu mainboard FPGA
IO_L34N_A12_M1BA2_1 is connected, from the pin of the pin F15 of plate FPGA Yu mainboard FPGA
IO_L35P_A11_M1A7_1 is connected, from the pin of the pin F16 of plate FPGA Yu mainboard FPGA
IO_LE5N_A10_M1A2_1 is connected, from the pin of the pin G14 of plate FPGA Yu mainboard FPGA
IO_L36P_A9_M1BA0_1 is connected, from the pin of the pin G16 of plate FPGA Yu mainboard FPGA
IO_L36N_A8_M1BA1_1 is connected, from the pin of the pin H15 of plate FPGA Yu mainboard FPGA
IO_L37P_A7_M1A0_1 is connected, from the pin of the pin H16 of plate FPGA Yu mainboard FPGA
IO_L37N_A6_M1A1_1 is connected, from the pin of the pin G12 of plate FPGA Yu mainboard FPGA
IO_L38P_A5_M1CLK_1 is connected；
It is connected from the pin IO_L1P_CCLK_2 of the pin R11 of plate FPGA and mainboard FPGA；Pin from plate FPGA
The pin IO_L13P_M1_2 of N11 and mainboard FPGA is connected, from the pin of the pin R9 of plate FPGA Yu mainboard FPGA
IO_L23P_2 is connected；
It is connected from the pin IO_L41N_GCLK8_M1ACASN_1 of the pin K13 of plate FPGA and mainboard FPGA, from
The pin IO_L43N_GCLK4_M1DQ5_1 of the pin J16 and mainboard FPGA of plate FPGA is connected, from plate FPGA's
The pin IO_L44P_A3_M1DQ6_1 of pin K15 and mainboard FPGA is connected, from pin K16 and the mainboard of plate FPGA
The pin IO_L44N_A2_M1DQ7_1 of FPGA is connected, from the pin of the pin N16 of plate FPGA Yu mainboard FPGA
IO_L45N_A0_M1DQSN_1 is connected, from the pin of the pin M15 of plate FPGA Yu mainboard FPGA
IO_L46P_FCS_B_M1DQ2_1 is connected, from the pin of the pin M16 of plate FPGA Yu mainboard FPGA
IO_L46N_FOE_B_M1DQ3_1 is connected, from the pin of the pin L16 of plate FPGA Yu mainboard FPGA
IO_L47N_LDC_M1DQ1_1 is connected, from the pin of the pin P15 of plate FPGA Yu mainboard FPGA
IO_L48P_HDC_M1DQ8_1 is connected, from the pin of the pin P16 of plate FPGA Yu mainboard FPGA
IO_L48N_M1DQ9_1 is connected, from the pin IO_L49P_M1DQ10_1 of the pin R15 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L49N_M1DQ11_1 of the pin R16 of plate FPGA and mainboard FPGA, from plate FPGA
The pin IO_L50P_M1UDQS_1 of pin R14 and mainboard FPGA be connected, from pin T15 and the mainboard of plate FPGA
The pin IO_L50N_M1UDQSN_1 of FPGA is connected, from the pin of the pin T14 of plate FPGA Yu mainboard FPGA
IO_L51P_M1DQ12_1 is connected, from the pin IO_L51N_M1DQ13_1 of the pin T13 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L52P_M1DQ14_1 of the pin R12 of plate FPGA and mainboard FPGA, from plate FPGA
The pin IO_L52N_MQDQ15_1 of pin T12 and mainboard FPGA be connected, from pin P14 and the mainboard of plate FPGA
The pin SUSPEND of FPGA is connected；
As shown in Figure 6, it is connected from the pin CMPCS_B_2 of the pin L11 of plate FPGA and mainboard FPGA, from plate FPGA
The pin DONE_2 of pin P13 and mainboard FPGA be connected, from the pin of the pin T11 of plate FPGA Yu mainboard FPGA
IO_L1N_M0_CMPMISO_2 is connected, from the pin of the pin M12 of plate FPGA Yu mainboard FPGA
IO_L2P_CMPCLK_2 is connected, from the pin IO_L2N_CMPMOSI_2 of the pin M11 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L3P_D0_DIN_MISO_MISO1_2 of the pin P10 of plate FPGA and mainboard FPGA,
It is connected from the pin IO_L3N_MOSI_CSI_B_MISO0_2 of the pin T10 of plate FPGA and mainboard FPGA, from plate FPGA
The pin IO_L12P_D1_MISO2_2 of pin N12 and mainboard FPGA be connected, from pin P12 and the master of plate FPGA
The pin IO_L12N_D2_MISO3_2 of plate FPGA is connected, from the pin of the pin P7 of plate FPGA Yu mainboard FPGA
IO_L31P_GCLK31_D14_2 is connected, from the pin of the pin T7 of plate FPGA Yu mainboard FPGA
IO_L32N_GCLK28_2 is connected, and is connected from the pin IO_L62N_D6_2 of the pin L7 of plate FPGA and mainboard FPGA,
It is connected from the pin IO_L63N_2 of the pin T4 of plate FPGA and mainboard FPGA, from pin R3 and the mainboard of plate FPGA
The pin IO_L65P_INIT_B_2 of FPGA is connected, from the pin of the pin T3 of plate FPGA Yu mainboard FPGA
IO_L65N_CS0_B_2 is connected；It is connected from the pin PROGRAM_B_2 of the pin T2 of plate FPGA and mainboard FPGA；
As it is shown in fig. 7, from the pin IO_L43P_GCLK23_M3RASN_3 of the pin J6 of plate FPGA Yu mainboard FPGA
It is connected, is connected from the pin IO_L45N_M3ODT_3 of the pin L5 of plate FPGA and mainboard FPGA, from plate FPGA's
The pin IO_L47N_M3A1_3 of pin K6 and mainboard FPGA is connected, from the pin A2 of plate FPGA and mainboard FPGA
Pin IO_L52N_M3A9_3 be connected, be connected from the pin IO_L83P_3 of the pin B3 of plate FPGA and mainboard FPGA,
It is connected from the pin IO_L83N_VREF_3 of the pin A3 of plate FPGA and mainboard FPGA；From the pin F11 of plate FPGA
Connect the IO_L30N_A20_M1A11_3 of mainboard FPGA；Connect mainboard FPGA's from the pin D15 of plate FPGA
IO_L30N_A20_M1A12_3。
Additionally, be connected to pad from 87 fly lines of plate FPGA, mainboard FPGA draws 87 also by I/O pin simultaneously
Root line is connected to pad, is respectively connected with 87 fly lines from plate FPGA；From 32 toggle switch of plate FPGA totally 32
Root line, 6 button totally 6 lines, totally 38 lines are together as the input equipment from plate FPGA；16 LED totally 16
Line, 33 lines of 9 charactrons, totally 49 lines are as the output equipment from plate FPGA；
Wherein, 16 lines of LED connect as follows:
As it is shown in figure 5, connect the IO_L38N_A4_M1CLKN_1 of mainboard FPGA from the pin H11 of plate FPGA；From
The pin H13 of plate FPGA connects the IO_L39P_M1A3_1 of mainboard FPGA；Connect main from the pin H14 of plate FPGA
The IO_L39N_M1ODT_1 of plate FPGA；Connect mainboard FPGA's from the pin J11 of plate FPGA
IO_L40P_GCLK11_M1A5_1；Connect mainboard FPGA's from the pin J12 of plate FPGA
IO_L40N_GCLK10_M1A6_1；Connect mainboard FPGA's from the pin J13 of plate FPGA
IO_L41P_GCLK9_IRDY1_M1RASN_1；Connect mainboard FPGA's from the pin K14 of plate FPGA
IO_L41N_GCLK8_M1CASN_1；Connect mainboard FPGA's from the pin K12 of plate FPGA
IO_L42P_GCLK7_M1UDM_1；Connect mainboard FPGA's from the pin K11 of plate FPGA
IO_L42N_GCLK6_TRDY1_M1LDM_1；Connect mainboard FPGA's from the pin J14 of plate FPGA
IO_L43P_GCLK5_M1DQ4_1；Connect mainboard FPGA's from the pin N14 of plate FPGA
IO_L45N_A0_M1LDQSN_1；Connect mainboard FPGA's from the pin L14 of plate FPGA
IO_L47P_FWE_B_M1DQ0_1；The IO_L53P_1 of mainboard FPGA is connected from the pin L12 of plate FPGA；From plate
The pin L13 of FPGA connects the IO_L53N_VREF_1 of mainboard FPGA；Mainboard is connected from the pin M13 of plate FPGA
The IO_L74P_AWAKE_1 of FPGA；Connect mainboard FPGA's from the pin M14 of plate FPGA
IO_L74N_DOUT_BUSY_1。
33 lines of 9 charactrons connect as follows:
As shown in Figure 6, the IO_L13N_D10_2 of mainboard FPGA is connected from the pin P11 of plate FPGA；From plate FPGA's
Pin N9 connects the IO_L14P_D11_2 of mainboard FPGA；Connect mainboard FPGA's from the pin P9 of plate FPGA
IO_L14N_D12_2；The IO_L16P_2 of mainboard FPGA is connected from the pin L10 of plate FPGA；Pin from plate FPGA
M10 connects the IO_L16N_VREF_2 of mainboard FPGA；Connect mainboard FPGA's from the pin M9 of plate FPGA
IO_L29P_GCLK3_2；The IO_L29N_GCLK2_2 of mainboard FPGA is connected from the pin N8 of plate FPGA；From plate FPGA
Pin P8 connect mainboard FPGA IO_L30P_GCLK1_D13_2；Mainboard FPGA is connected from the pin M7 of plate FPGA
IO_L31N_GCLK30_D15_2；The IO_L47P_2 of mainboard FPGA is connected from the pin P6 of plate FPGA；From plate FPGA
Pin N5 connect mainboard FPGA IO_L49P_D3_2；Connect mainboard FPGA's from the pin P5 of plate FPGA
IO_L49N_D4_2；The IO_L62P_D5_2 of mainboard FPGA is connected from the pin L8 of plate FPGA；From drawing of plate FPGA
Pin P4 connects the IO_L63P_2 of mainboard FPGA；The IO_L64P_D8_2 of mainboard FPGA is connected from the pin M6 of plate FPGA；
The IO_L64N_D9_2 of mainboard FPGA is connected from the pin N6 of plate FPGA；
As it is shown in fig. 7, connect the IO_L1P_3 of mainboard FPGA from the pin M4 of plate FPGA；Pin from plate FPGA
M3 connects the IO_L1N_VREF_3 of mainboard FPGA；The IO_L2P_3 of mainboard FPGA is connected from the pin M5 of plate FPGA；
The IO_L2N_3 of mainboard FPGA is connected from the pin N4 of plate FPGA；Mainboard FPGA is connected from the pin N3 of plate FPGA
IO_L34P_M3UDQS_3；The IO_L36P_M3DQ8_3 of mainboard FPGA is connected from the pin L3 of plate FPGA；From
The pin J3 of plate FPGA connects the IO_L38P_M3DQ2_3 of mainboard FPGA；Mainboard is connected from the pin K3 of plate FPGA
The IO_L42P_GCLK25_TRDY2_M3UDM_3 of FPGA；Connect mainboard FPGA's from the pin J4 of plate FPGA
IO_L42N_GCLK24_M3LDM_3；Connect mainboard FPGA's from the pin H5 of plate FPGA
IO_L43N_GCLK22_IRDY2_M3CASN_3；Connect mainboard FPGA's from the pin H4 of plate FPGA
IO_L44P_GCLK21_M3A5_3；Connect mainboard FPGA's from the pin H3 of plate FPGA
IO_L44N_GCLK20_M3A6_3；The IO_L45P_M3A3_3 of mainboard FPGA is connected from the pin L4 of plate FPGA；
The IO_L47P_M3A0_3 of mainboard FPGA is connected from the pin K5 of plate FPGA；Connect main from the pin G6 of plate FPGA
The IO_L51P_M3A10_3 of plate FPGA；The IO_L51N_M3A4_3 of mainboard FPGA is connected from the pin G5 of plate FPGA；
The IO_L3N_3 of mainboard FPGA is connected from the pin A5 of plate FPGA.
32 lines of toggle switch connect as follows:
As it is shown in fig. 7, connect the IO_L32P_M3DQ14_3 of mainboard FPGA from the pin R2 of plate FPGA；From plate FPGA
Pin R1 connect mainboard FPGA IO_L32N_M3DQ15_3；Mainboard FPGA is connected from the pin P2 of plate FPGA
IO_L33P_M3DQ12_3；The IO_L33N_M3DQ13_3 of mainboard FPGA is connected from the pin P1 of plate FPGA；From
The pin N1 of plate FPGA connects the IO_L34N_M3UDQSN_3 of mainboard FPGA；Connect from the pin M2 of plate FPGA
The IO_L35P_M3DQ10_3 of mainboard FPGA；Connect mainboard FPGA's from the pin M1 of plate FPGA
IO_L35N_M3DQ11_3；The IO_L36N_M3DQ9_3 of mainboard FPGA is connected from the pin L1 of plate FPGA；From plate
The pin K2 of FPGA connects the IO_L37P_M3DQ0_3 of mainboard FPGA；Mainboard FPGA is connected from the pin K1 of plate FPGA
IO_L37N_M3DQ1_3；The IO_L38N_M3DQ3_3 of mainboard FPGA is connected from the pin J1 of plate FPGA；From plate
The pin H2 of FPGA connects the IO_L39P_M3LDQS_3 of mainboard FPGA；Mainboard is connected from the pin H1 of plate FPGA
The IO_L39N_M3LDQSN_3 of FPGA；Connect mainboard FPGA's from the pin G3 of plate FPGA
IO_L40P_M3DQ6_3；The IO_L40N_M3DQ7_3 of mainboard FPGA is connected from the pin G1 of plate FPGA；From plate
The pin F2 of FPGA connects the IO_L41P_GCLK27_M3DQ4_3 of mainboard FPGA；From the pin F1 of plate FPGA even
Meet the IO_L41N_GCLK26_M3DQ5_3 of mainboard FPGA；Connect mainboard FPGA's from the pin E2 of plate FPGA
IO_L46P_M3CLK_3；The IO_L46N_M3CLKN_3 of mainboard FPGA is connected from the pin E1 of plate FPGA；From plate
The pin C3 of FPGA connects the IO_L48P_M3BA0_3 of mainboard FPGA；Mainboard FPGA is connected from the pin C2 of plate FPGA
IO_L48N_M3BA1_3；The IO_L49P_M3A7_3 of mainboard FPGA is connected from the pin D3 of plate FPGA；From plate
The pin D1 of FPGA connects the IO_L49N_M3A2_3 of mainboard FPGA；Mainboard FPGA is connected from the pin C1 of plate FPGA
IO_L50P_M3WE_3；The IO_L50N_M3BA2_3 of mainboard FPGA is connected from the pin B1 of plate FPGA；From plate
The pin B2 of FPGA connects the IO_L52P_M3A8_3 of mainboard FPGA；Mainboard FPGA is connected from the pin F4 of plate FPGA
IO_L53P_M3CKE_3；The IO_L53N_M3A12_3 of mainboard FPGA is connected from the pin F3 of plate FPGA；From plate
The pin E4 of FPGA connects the IO_L54P_M3RESET_3 of mainboard FPGA；Mainboard is connected from the pin E3 of plate FPGA
The IO_L54N_M3A11_3 of FPGA；The IO_L55P_M3A13_3 of mainboard FPGA is connected from the pin F6 of plate FPGA；
The IO_L55N_M3A14_3 of mainboard FPGA is connected from the pin F5 of plate FPGA；
6 lines of button connect as follows:
As shown in Figure 6, the IO_L32P_GCLK29_2 of mainboard FPGA is connected from the pin R7 of plate FPGA；From plate FPGA
Pin T6 connect mainboard FPGA IO_L47N_2；Connect mainboard FPGA's from the pin R5 of plate FPGA
IO_L48P_D7_2；The IO_L48N_RDWR_B_VREF_2 of mainboard FPGA is connected from the pin T5 of plate FPGA；From
The pin T8 of plate FPGA connects the IO_L30N_GCLK0_USERCCLK_2 of mainboard FPGA；Pin from plate FPGA
T9 connects the IO_L23N_2 of mainboard FPGA.
So, mainboard FPGA first resolves the input operation order of the host computer from UART serial ports, according to different operating order
The different low and high level of simulation, by signal excitation by fly line pad driver from the toggle switch of plate FPGA and button, to reach to learn
The mesh ground of the raw on-line operation switch from plate FPGA and button, mainboard FPGA is captured from plate FPGA by fly line pad simultaneously
LED and the real-time output of charactron, and result is fed back to host computer by serial ports, host computer passes through network will be from plate FPGA
Data result be sent to client.
This example uses at present in BJ University of Aeronautics & Astronautics's computer architecture course: mainboard FPGA is Xilinx company
SPARTAN6 series, model is XC6SLX150-2FGG676C；It is SPARTAN6 system of Xilinx company from plate FPGA
Row, model is XC6SLX150-2FGG676C；Ensureing that pin line can use any other type on the premise of correct
FPGA or programmable part replace.As it is shown on figure 3, this equipment is divided into 2 regions, wherein SYS AREA represents mainboard
FPGA, USER AREA represents from plate FPGA.From plate FPGA region: 1 represents 2 UART interface；2 represent 1
Individual USB interface；3 represent 2 PS2 interfaces；6 represent the FPGA master chip from plate；7 represent CF card；10 expressions are pressed
Key；11 represent LED；12 represent charactron；13 represent toggle switch；5 represent the fly line pad that mainboard is connected with from plate；
In main board region: 4 represent 2 UART interface；The 8 FPGA master chips representing mainboard；9 represent button.
A kind of online experiment method based on FPGA, as shown in Figure 8, specifically comprises the following steps that
Step one, user use the time of online experiment system in client reservation；
Student, by logging in Mooc course center, enters the online experiment platform of this course, carries out the reservation application of equipment, by
The scheduling of client software complexity is total to equipment, use the information such as number of devices, free device number to carry out the experimental period of student
Arrange, and reservation result is fed back to user.
When upper computer software starts, host computer sends to server " Register Id="+" host computer identifier " instruction, server
After receiving instruction, send to host computer " Record " instruction, if host computer does not receives what server was sent " Record " instruction, then
Sent to server every 1 minute " Register Id="+" host computer identifier " instruction.
Free time experimental facilities is distributed to user by step 2, host computer, user by client to host computer submit to download request or
Person's operational order；
After free time experimental facilities is distributed to corresponding user by host computer, start timing by timer；
When client asks equipment, server sends " Start ", after host computer receives instruction, initially enters duty,
After host computer and FPGA plate all have been prepared for, send to server " Already ".
User is uploaded to downloading the file needed or operational order in the host computer of reservation by network in client；
What step 3, host computer judged that user sends is the request of downloading or operational order, if downloading request, uploads download
File also enters step 4；Otherwise enter step 6；
User specifies the path, place of the .bit file needing download, by client upload to the host computer of reservation；
Operational order refers to button or the toggle switch button of user click client, to realize the external interrupt mesh in specific experiment
Ground；
When server receives what host computer transmitted " Already " instruction after, just permission client upload code, client upload generation
After Ma, server sends " Load: "+" filename " instruction, retransmit code file, after host computer receives instruction and file,
First being made comparisons with the filename receiving file by the filename in instruction, if identical, then by code burning FPGA, burning is complete
Bi Hou, host computer sends to server end " Loaded " instruction；If differing, then send " Filename Mismatching ".
Step 4, host computer, according to the request of downloading, are sent download command to mainboard FPGA, and automatically will by UART serial ports
Download file and be transferred to mainboard FPGA.
After host computer receives the download request that user needs, send download command to mainboard FPGA, and Internet will be passed through
Its internal RAM is there is to mainboard FPGA, mainboard FPGA by the .bit file received in these data by UART Serial Port Transmission
In.
When server receives what host computer transmitted " Loaded " after instruction, client and host computer proceed by data exchange, press
Carry out according to data form before.
After step 5, mainboard FPGA resolve download command, the download file received is stored in internal storage RAM,
And burning file will be downloaded to from plate FPGA by 110 pin pins, it is achieved and the remote download of file destination, enter step 8；
After mainboard FPGA stores data in RAM completely, mainboard FPGA by download command and downloads data by fly line
It is transferred to from plate FPGA, completes the download from plate FPGA.
Operational order is transferred to mainboard FPGA by UART serial ports by step 6, host computer；
Host computer resolves the operation requests from network, and passes through UART serial ports to mainboard FPGA according to concrete operation equipment
Send corresponding operational order；The action message of user, by operating the input equipment of client software, is passed through net by student
Network feeds back to host computer, and host computer produces the drive command of this input equipment, is sent to mainboard FPGA by UART serial ports.
After step 7, mainboard FPGA resolve this order, simulate corresponding pumping signal and be sent to from plate by the fly line on pad
The input equipment of FPGA, to realize the on-line debugging of experimental facilities.
The mainboard FPGA design control system of complete serial ports controller, by resolving operational order, simulation needs to produce
Low and high level, is passed to this signal from plate FPGA by pad fly line, it is achieved thereby that on-line operation button or toggle switch
Function.
Step 8, mainboard FPGA persistently monitor the output from plate FPGA, and utilize the electricity of internal register record coherent signal
Flat change, and by UART serial ports, signal intensity situation fed back to host computer, and then reach the purpose of output monitoring.
When file destination is after having downloaded from plate FPGA, and mainboard FPGA persistently monitors the output equipment from plate FPGA, logical
Cross fly line capture LED and real-time output of charactron from plate FPGA, and utilize the level of internal register record coherent signal
Change, and by data after UART-USB converter is changed, by UART serial ports, signal intensity situation is fed back to upper
Machine.
Step 9, host computer will be sent to consumer process from the output result of plate FPGA by network, and client Real-time Feedback is real
Test result.
Host computer resolves the data of mainboard FPGA transmission and resolves, and obtains the real-time status of different output equipment, finally leads to
Crossing Internet and current state feeds back to client software, the change of output equipment is shown on use interface by client software.
Step 10, distribute to after the experimental period of user exhausts, send reset command to mainboard FPGA and drive from plate when host computer
FPGA resets, and is used the order of authority to client transmission this user of stopping by network.
When, after the connection that client disconnects with equipment, server sends " Shutdown " instruction to host computer, and host computer receives instruction
After, host computer and FPGA enter idle condition, and host computer sends to server afterwards " Down " instruction, but still keep and clothes
The connection of business device.Until receiving what server transmission came " Start " instruction, just it is again introduced into duty.
Claims (6)
1. an online experiment system based on FPGA, it is characterised in that include client, host computer, mainboard FPGA and
From plate FPGA, mainboard FPGA as access controller, from plate FPGA as experimental facilities；
Host computer passes through network-in-dialing client, is simultaneously connected with 2 UART serial interfaces of mainboard FPGA；Use connector
110 pins of mainboard FPGA are connected with the 110 pin pins from plate FPGA respectively by 36 lines, thus realize from plate
The download programming of FPGA and on-line operation；Meanwhile, mainboard FPGA draws 87 lines by I/O pin and is connected to pad, from
Plate FPGA draws 87 fly lines and is also connected to pad, will be connected with mainboard FPGA from the I/O equipment of plate FPGA by pad.
A kind of online experiment system based on FPGA, it is characterised in that described from plate FPGA
110 pin pins comprise: 4 pins that 32 DATA pins, clock are relevant, relevant for VGA 33 pins, PS2
Relevant 4 pins, 6 pins of external key, 4 relevant for JTAG pins, FPGA programming mode be correlated with DONE,
FPGA_DO and FPGA_DI line totally 27 pins；
Include from 87 fly lines of plate FPGA: 32 lines that 32 toggle switch are corresponding, 6 lines that 6 buttons are corresponding,
16 lines that 16 LED are corresponding and 33 lines corresponding to 9 charactrons.
A kind of online experiment system based on FPGA, it is characterised in that described mainboard FPGA
On comprise 1 crystal oscillator, the frequency dividing circuit of mainboard FPGA the clock provided crystal oscillator carries out accurate division, by 4 differences
Holding wire be connected with from plate FPGA, to from plate FPGA interface provide tetra-kinds of standards of 1Hz, 1KHz, 75KHz, 12MHz
Clock signal.
A kind of online experiment system based on FPGA, it is characterised in that include from plate FPGA:
2 UART interface, 2 PS2 interfaces, 1 USB interface, buzzer and CF card；2 UART interface are with PC even
Connecing, 2 PS2 interfaces connect keyboard and mouse respectively, and USB interface connects display, the I/O interface provided from plate FPGA
All do experiment to use.
5. the online experiment method of the application a kind of based on FPGA online experiment system described in claim 1, it is characterised in that
Specifically comprise the following steps that
Step one, user use the time of online experiment system in client reservation；
Free time experimental facilities is distributed to user by step 2, host computer, user by client to host computer submit to download request or
Person's operational order；
What step 3, host computer judged that user sends is the request of downloading or operational order, if downloading request, uploads download
File also enters step 4, otherwise enters step 6；
Step 4, host computer according to download request to mainboard FPGA send download command, and by UART serial ports automatically will under
Published article part is transferred to mainboard FPGA；
After step 5, mainboard FPGA resolve download command, download file is stored in internal storage RAM, and passes through
110 pin pins will download burning file to from plate FPGA, it is achieved the remote download of file destination, enter step 8；
Operational order is transferred to mainboard FPGA by UART serial ports by step 6, host computer；
Step 7, mainboard FPGA resolve after operational order, simulation low and high level by pad fly line drive from plate FPGA defeated
Enter equipment, to realize the on-line debugging from plate FPGA and on-line operation；
Step 8, mainboard FPGA persistently monitor the output equipment from plate FPGA, and utilize internal register record output signal
Level change, signal intensity situation is fed back to host computer；
Step 9, host computer are by being sent to client process from the output result of plate FPGA by network, anti-to client in real time
Feedback experimental result；
Step 10, distribute to after the experimental period of user exhausts, send reset command to mainboard FPGA and drive from plate when host computer
FPGA resets, and is used the order of authority to client transmission this user of stopping by network.
6. online experiment method based on FPGA as claimed in claim 5, it is characterised in that described step 7 particularly as follows:
Mainboard FPGA resolves the operational order simulation low and high level of host computer, and then produces different control excitation letters to from plate FPGA
Number, by fly line pad driver from 32 toggle switch of plate FPGA and 6 buttons, it is achieved user's on-line operation switch and pressing
Key.
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