CN105917303B - Controller, method for identifying stability of data block and storage system - Google Patents
Controller, method for identifying stability of data block and storage system Download PDFInfo
- Publication number
- CN105917303B CN105917303B CN201480035916.9A CN201480035916A CN105917303B CN 105917303 B CN105917303 B CN 105917303B CN 201480035916 A CN201480035916 A CN 201480035916A CN 105917303 B CN105917303 B CN 105917303B
- Authority
- CN
- China
- Prior art keywords
- target
- logical address
- count value
- data block
- stability level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The embodiment of the invention provides a controller, which comprises a processor and a cache, wherein the processor is used for calculating a target logical address in a plurality of logical addresses according to a preset hash function to obtain a target hash value; determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry; determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relation between the count value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address; and sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device. The flash memory device can be enabled to store data blocks of the same stability level in a centralized manner.
Description
Technical Field
The embodiment of the invention relates to the technical field of storage, in particular to a controller, a method for identifying stability of a data block and a storage system.
Background
A Flash Memory device is a non-volatile Memory, and its storage medium is NAND Flash, which has a characteristic that data does not disappear after power is turned off, and thus, it is widely used as an external and internal Memory. The Flash memory Device using NAND Flash as a storage medium may be a Solid State Drive (SSD), or other memory.
an SSD is typically composed of multiple flash memory chips, each of which contains several blocks (blocks). Since NAND Flash has an erasing characteristic, data stored in the block is not directly modified like a general mechanical hard disk. When data pointed by a certain logical address needs to be modified, an idle block needs to be searched, the modified data is written into the idle block, and then the logical address points to newly written data, so that the data in the original block becomes invalid data. For the SSD, valid data refers to data stored in a block and pointed to by a logical address, and the part of data may be read; invalid data refers to data stored in the block and not pointed to by a logical address, and the part of data cannot be read.
As more and more data is stored in SSDs, fewer and fewer free blocks are available, and it is therefore necessary to garbage collect SSDs in order to generate free blocks that are available for utilization. The garbage collection means that effective data in the block is moved to an idle block, then the old block is erased, and the erased block can be used as the idle block to write data again. Typically, when performing garbage collection, an SSD will look for blocks that contain more invalid data, because blocks that contain more invalid data contain less valid data, then less valid data needs to be moved to a free block. In the case where the life of the SSD is correlated with the number of times of erasing the NAND Flash, the less data is transferred in garbage collection, the smaller the write amplification of the SSD. However, in the existing storage system, the controller cannot know the possibility of modifying the data, so when the data is sent to the SSD, the SSD can only store the data according to the existing storage mode, and the possibility of modifying the data stored in each block is approximately equivalent, so that the amount of invalid data contained in each block is not obviously different.
disclosure of Invention
A first aspect of the embodiments of the present invention provides a controller, where the controller includes a processor and a cache, where the cache stores multiple logical addresses, and also stores a hash table, where the hash table includes multiple entries, each entry corresponds to one logical address, and each entry records a count value, where the count value is used to indicate a number of times of modifying a data block corresponding to the logical address. The processor is configured to calculate a target logical address in the plurality of logical addresses according to a preset hash function, and obtain a target hash value. And then, determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry. And determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relation between the count value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address. And finally, sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
In a first implementation manner of the first aspect, the correspondence between the count value and the stability level includes a correspondence between a count value interval and the stability level. The processor is specifically configured to determine a target count value interval according to the target count value, where the target count value is located in the target count value interval. And then, determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
In a second implementation manner of the first aspect, the processor is further configured to obtain a target logical address in the plurality of logical addresses before the calculation of the target logical address according to a preset hash function. And then, calculating according to the target logical address and the hash function to obtain the target hash value. And determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry, and increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
A second aspect of the present invention provides a method for identifying stability of a data block, where the method is applied to a controller, where the controller includes a processor and a cache, where multiple logical addresses are stored in the cache, and a hash table is also stored in the cache, where the hash table includes multiple entries, each entry corresponds to one logical address, and a count value is recorded in each entry, where the count value is used to indicate a number of times of modifying the data block corresponding to the logical address. The method is executed by the processor and comprises the following steps: and calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value. And then, determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry. And then sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
In a first implementation manner of the second aspect, the correspondence between the count value and the stability level includes a correspondence between a count value interval and the stability level. Determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relationship between the count value and the stability level includes: and determining a target counting value interval according to the target counting value, wherein the target counting value is positioned in the target counting value interval. And determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
in a second implementation manner of the second aspect, before the calculating a target logical address of the plurality of logical addresses according to a preset hash function, the method further includes: and acquiring the target logical address. And then, calculating according to the target logical address and the hash function to obtain the target hash value. And determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry, and increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
A third aspect of embodiments of the present invention provides a storage system, where the storage system includes the controller according to any one of the first to second implementation manners of the first aspect, and a flash memory device. The flash memory device comprises a main controller and a flash memory chip, wherein the flash memory chip comprises a plurality of blocks, and the main controller comprises a processor. The processor is configured to obtain a stability level corresponding to the target logical address, where the stability level is used to indicate stability of the data block. And then, writing the data block corresponding to the target logic address into the block corresponding to the stability level according to the stability level corresponding to the target logic address.
In a first implementation form of the third aspect, the method further comprises: and searching the block containing the most invalid data in the flash memory chip, wherein the block containing the most invalid data comprises the data block corresponding to the target logical address.
In a second embodiment of the third aspect, the method further comprises: and searching the unerased block in the longest time in the flash memory chip, wherein the unerased block in the longest time comprises the data block corresponding to the target logical address.
In a third implementation form of the third aspect, the master controller further includes a cache. The obtaining of the stability level corresponding to the target logical address includes: and when the number of the logic addresses stored in the cache is determined to reach a preset threshold value, obtaining a stability level corresponding to the target logic address, wherein the stability level corresponding to the logic address is the same as the stability level corresponding to the target logic address.
A fourth aspect of the embodiments of the present invention provides an apparatus for identifying stability of a data block, where the apparatus is located in a controller. The device comprises: the storage module is used for storing a plurality of logical addresses and a hash table, the hash table comprises a plurality of table entries, each table entry corresponds to one logical address, and a count value is recorded in each table entry and is used for indicating the number of times of modifying a data block corresponding to the logical address. The calculation module is used for calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value; and determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry. And the determining module is used for determining the stability level of the data block corresponding to the target logical address according to the target counting value and the corresponding relation between the counting value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address. And the sending module is used for sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
in a first implementation manner of the fourth aspect, the correspondence between the count value and the stability level includes a correspondence between a count value interval and the stability level. The determining module is specifically configured to determine a target count value interval according to the target count value, where the target count value is located in the target count value interval. And then, determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
A fifth aspect of embodiments of the present invention provides a computer program product, which includes a computer-readable storage medium storing program code including instructions for executing the method according to any one of the second to the second embodiments of the second aspect.
In this embodiment, the controller may calculate and obtain a hash value according to a logical address, where the hash value corresponds to an entry in a hash table, and a count value is recorded in the entry, where the count value is used to indicate a modification number of a data block corresponding to the logical address, so that a stability level of the data block corresponding to the logical address may be obtained according to the count value, where the stability level may reflect stability of the data block corresponding to the logical address, and the stability level and the logical address of the data block are sent to the flash memory device, so that the flash memory device may store the data blocks with the same stability level in a centralized manner, and thus move less valid data during subsequent garbage collection operation, and reduce write amplification.
Drawings
in order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed in the prior art or the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a block diagram of a storage system provided by an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a controller provided in an embodiment of the present invention;
FIG. 3A is a schematic structural diagram of a storage medium of a flash memory device according to an embodiment of the present invention;
FIG. 3B is a diagram illustrating a host controller of a flash memory device according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for identifying data block stability according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating a method for storing data in a flash memory device according to an embodiment of the present invention;
FIG. 6 is a diagram of a hash table provided by an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of an apparatus for identifying stability of a data block according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a controller, a method for identifying stability of a data block and a storage system, which are used for identifying the stability level of the data block corresponding to a logical address by the controller and sending the logical address and the stability level to a flash memory device, so that the flash memory device can intensively store the data blocks with the same stability level, and effective data contained in the selected block is as less as possible during subsequent garbage collection, thereby reducing write amplification of the flash memory device.
Before describing embodiments of the present invention, the following terms will first be described:
the data object refers to an object containing actual data, and may be block data, or may be a file or other form of data.
a data block refers to a unit of data divided by a data object. For convenience of management, one data object may be divided into several data blocks, each of which has the same size.
Metadata of a data block refers to information for describing the data block, such as a logical address of the data block, a physical address of the data block, a correspondence between the logical address and the physical address, a write time of the data block, and the like.
Stable data refers to data that is relatively less likely to be modified.
the Logical Block Address is also called a Logical Address (LBA), and refers to a storage Address of the data Block, where the storage Address is not an actual Address where the data Block is stored in the SSD, but an accessible Address presented externally.
the Physical Block Address is also called Physical Block Address (PBA), and refers to the actual Address of the data Block stored in the SSD.
Valid data in an SSD refers to a block of data that has a logical address pointing to it in the block of the SSD, i.e., its physical address has a corresponding logical address.
Invalid data in an SSD typically refers to a block of data held in a block of the SSD that has no logical address pointing to it, i.e., its physical address does not have a corresponding logical address.
Fig. 1 depicts a block diagram of a memory system provided by an embodiment of the present invention, and the memory system shown in fig. 1 includes a controller 11 and a plurality of flash memory devices 22. The Flash memory Device 22 is a storage Device using Flash particles as a storage medium, and may include a Solid State Drive (SSD), and possibly other memories. In the present embodiment, the flash memory device 22 is described by taking SSD as an example.
fig. 1 is an exemplary illustration only, and does not limit the specific networking manner, such as: cascaded tree networking and ring networking are all possible. As long as the controller 11 and the flash memory device 22 can communicate with each other.
The controller 11 may comprise any computing device known in the art, such as a server, desktop computer, etc. The controller 11 may receive a data object sent by a host (not shown in fig. 1) and send a write data request to the flash memory device 22, causing the flash memory device 22 to write the data object carried in the write data request into its flash memory chip.
referring to fig. 2, fig. 2 is a schematic structural diagram of a controller 11 according to an embodiment of the present invention. As shown in fig. 2, the controller 11 mainly includes a processor (processor)118, a cache (cache)120, a memory (memory)122, a Communication bus (bus) 126, and a Communication Interface (Communication Interface) 128. Processor 118, cache 120, memory 122, and communication interface 128 communicate with each other via a communication bus 126.
the processor 118 may be a central processing unit CPU, or an application Specific Integrated circuit ASIC, or one or more Integrated circuits configured to implement embodiments of the present invention. In the embodiment of the present invention, the processor 118 is configured to receive the data object from the host, and send the data object to the flash memory device 22 after a certain processing.
A communication interface 128 for communicating with a host or flash memory device 22.
Memory 122 is used to store program 124, and memory 122 may comprise a high-speed RAM memory and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. It is understood that the Memory 122 can be a Random-Access Memory (RAM), a magnetic Disk, a hard Disk, an optical Disk, a Solid State Disk (SSD), or a non-volatile Memory, which can store program codes.
The Cache 120(Cache) is used to temporarily store data objects received from the host or data objects read from the flash memory device 22. In addition, because the speed of reading and writing data by the Cache is high, some frequently used information can be stored in the Cache for convenience of reading, such as the logical address of the data block. The cache 120 may be a Non-transitory (Non-transitory) machine readable medium that can store data, such as a RAM, a Storage-Class Memory (SCM), a Non-Volatile Memory (NVM), a Flash Memory (Flash Memory), or a Solid State Disk (SSD), which is not limited herein.
The cache 120 and the memory 122 may be combined or separated, which is not limited by the embodiment of the present invention.
Program 124 may include program code comprising computer operating instructions. For example, the program code may include a stability determination module, by which the number of times the data block stored in each LBA is modified, that is, the stability of the data block corresponding to the LBA is determined.
The function of the stability determination module is briefly described below:
First, to accomplish this function, a hash table (another copy may be stored in the flash memory device 22 as a backup to prevent loss) is stored in the cache 120, and the hash table includes a plurality of entries, and each entry has a count value recorded therein. The number of entries of the hash table is related to the available capacity of the storage system shown in fig. 1, and assuming that the storage system stores N data blocks (N is a positive integer), and the size of each data block is 4KB, the number of entries of the hash table may be 2-8 times that of N.
Secondly, after the controller 11 receives the data object sent by the host, the data object can be divided into a plurality of data blocks with the same size. In addition, when receiving the data object, the controller 11 also receives address information of the data object, where the address information may include an ID of a Logical Unit Number (Logical Unit Number, LUN for short) and a start address offset of the LUN; or the ID of the file and the offset of the start address of the file, etc.; or when the storage system has a plurality of file systems, the address information may include an ID of the file system, an ID of the file, and a start address offset of the file, and the like. After dividing the data object into a plurality of data blocks with the same size, the logical address of each data block may be obtained according to the address information of the data object and the multi-level mapping table.
The stability judgment module comprises a hash function, and for one LBA, hash operation can be performed according to the hash function to obtain a hash value. The hash value is used to indicate a position of an entry in the hash table, so that the count value recorded in the entry can be found according to the hash value, and after the count value corresponding to the LBA is found, 1 is added to the count value (or other operation of incrementing the count value, which is not limited herein). And so on, if the subsequent controller 11 receives other data blocks to be written into the LBA, the count value corresponding to the LBA is incremented by 1. Thus, the count value may be used to indicate the number of modifications of the data block stored in the LBA corresponding thereto. The larger the count value is, the more the number of times of modification of the data block stored in the LBA is, the more unstable the data block is; conversely, the more stable.
when a task (here, the task is a task in which the controller 11 identifies the stability of the data block corresponding to each LBA) is triggered, the processor 118 may sequentially scan each LBA, perform hash calculation on the LBA according to the hash function described above to obtain a hash value, find an entry corresponding to the LBA according to the hash value, where the entry records a count value, and obtain a stability level of the LBA according to the count value. The stability level is a value reflecting the stability of the data block corresponding to the LBA, and the stability is lower when the value is larger, and vice versa. Alternatively, the stability level may be defined as the smaller the value the higher the stability and vice versa.
after obtaining the stability level of the data block corresponding to the LBA, the controller 11 may send the LBA and the stability level to the flash memory device 22, so that the flash memory device 22 collectively stores the data blocks of the same level in one or more blocks.
the structure and function of the flash memory device 22 will now be described.
Referring to fig. 3A, fig. 3A is a schematic structural diagram of a flash memory device 22 according to an embodiment of the invention. In the present embodiment, the flash memory device 22 is described by taking SSD as an example.
As shown in fig. 3A, the flash memory device 22 includes a main controller 220 and a storage medium 221. The main controller 220 is configured to receive an I/O request sent by the controller 11 to the flash memory device 22, or other information, such as a logical address and a stability level of a data block, and the main controller 220 is further configured to execute the received I/O request, such as writing the data block carried in the I/O request to the storage medium 221, or reading the data block from the storage medium 221 and returning the data block to the controller 11. The host controller 220 here is the host controller of the SSD.
the storage medium 221 is typically composed of several Flash memory (Flash) chips. Each flash memory chip includes a number of blocks. Each block includes a number of pages (pages), and the master controller 220 writes blocks of data in units of pages when writing them in the block.
Since NAND Flash has an erasing characteristic, data stored in the block is not directly modified like a general mechanical hard disk. When data in a certain block needs to be modified, an idle block needs to be searched to write the modified data into the idle block, and then the data in the original block becomes invalid data. As more and more data is stored in SSDs, fewer and fewer free blocks are available, and it is therefore necessary to garbage collect SSDs in order to generate free blocks that are available for utilization. In this embodiment, when garbage collection is performed, the blocks containing the most invalid data are generally selected in sequence for collection. The triggering condition for garbage collection is that the number of free blocks contained in the flash memory chip is lower than a first threshold, which may be an integer greater than 10 and less than 100.
in addition, regular polling is also required inside the flash memory device 22, and the polling refers to an operation of periodically moving data stored in the flash memory chip in order to prevent data loss caused by an excessively long erase time of some blocks in the flash memory chip. For NAND Flash, its ability to hold data can only be maintained for a certain time, so that the data stored therein needs to be moved again at regular intervals. In this embodiment, during polling, the blocks that have not been erased within the longest time are generally selected in sequence, valid data in the blocks are moved to the free blocks, and the original blocks are erased. And the polling trigger condition may be when a preset polling period arrives.
because the service life of the SSD is related to the erasing times of the NAND Flash, the data movement in the SSD is reduced as much as possible, which is beneficial to reducing the write amplification, thereby prolonging the service life of the SSD. In this embodiment, the data transfer inside the SSD mainly refers to the transfer of valid data in the block during garbage collection or polling. It will be appreciated that for a block to be reclaimed, the less data that needs to be moved if it contains less valid data. Therefore, the present invention is directed to a controller that recognizes the stability of a data block corresponding to a logical address and transmits a stability level reflecting the stability of the data block to an SSD, so that the data blocks in the SSD are collectively stored according to the stability level, and then valid data to be moved during a subsequent garbage collection operation is performed as little as possible.
Fig. 3B is a schematic structural diagram of the host controller 220 in the flash memory device 22 according to an embodiment of the present invention.
the host controller 220 mainly includes a processor (processor)218, a memory (cache)230, a Communication bus (bus) 226, and a Communication Interface (Communication Interface) 228. The processor 218, cache 230, and communication interface 228 communicate with one another via a communication bus 226.
The processor 218 may be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present invention. In the embodiment of the present invention, the processor 218 may be configured to receive information such as an I/O request from the controller 11, a logical address of the data block, and a stability level of the data block, and the processor 218 is further configured to execute the I/O request.
A communication interface 228 for communicating with the controller 11 and the storage medium 221.
The buffer 230(Cache) is used for buffering information received from the controller 11, such as a logical address of the data block, a stability level of the data block, and the like. Cache 230 may be any of a variety of non-transitory (non-transient) or transitory (transient) machine-readable media that may store data, such as RAM, SCM, NVM, and the like, without limitation. In addition, in some application scenarios, the cache 230 may also be located external to the main controller 220.
In this embodiment, a mapping table may be stored in the cache 230 for storing the corresponding relationship between the LBA of the data block received from the controller 11 and the stability level of the data block. In general, a mapping table for recording the mapping relationship between the LBA and the PBA is also stored in the cache 230, and in the embodiment of the present invention, the corresponding relationship between the LBA and the stability level may be increased on the basis of the mapping table.
Alternatively, a plurality of arrays, each corresponding to a stable level, may be stored in the cache 230, and the logical addresses of the plurality of data blocks corresponding to the stable level may be stored in the arrays.
Alternatively, the cache 230 may collectively store the logical addresses of the data blocks having the same stability level in a cache space of the cache 230 without storing the mapping table. For example, the controller 11 may send, in advance, cache region division information to the flash memory device 22, where the cache region division information includes different stability levels (e.g., 10 stability levels that are 1 to 10, respectively), and after receiving the cache region division information, the flash memory device 22 divides the cache 230 into 10 cache regions according to the 10 stability levels, where each cache region corresponds to one stability level and is dedicated to store a logical address of a data block corresponding to the stability level. Alternatively, the controller 11 may directly transmit the logical address of the data block and the stability level of the data block to the flash memory device 22 without transmitting the buffer area division information to the flash memory device 22 in advance. The flash memory device 22 divides a segment of the buffer area in the buffer 230 according to the stability level of the data block, and associates the buffer area with the stability level (stores the corresponding relationship between the buffer area and the stability level), and then the divided buffer area may be dedicated to store the logical address of the data block corresponding to the stability level. Both of the above two ways can realize the centralized storage of the logical addresses of the data blocks with the same stability level into one cache space of the cache 230.
A method for identifying the stability of a data block according to an embodiment of the present invention will be described below, which describes a process of obtaining a stability level of a data block according to a logical address of the data block from the perspective of the controller 11 and transmitting the stability level to the flash memory device 22. Referring to fig. 4, fig. 4 is a flowchart illustrating a method for identifying stability of a data block corresponding to a logical address, where the method may be applied to the storage system shown in fig. 1 and the controller 11 shown in fig. 2, where a plurality of logical addresses are stored in the cache 120 of the controller 11, and a hash table is also stored in the cache 120, where the hash table includes a plurality of entries, each entry corresponds to a logical address, and a count value is recorded in each entry, and the count value is used to indicate a number of times of modifying the data block corresponding to the logical address; the execution subject is the processor 118 in the controller 11. The method comprises the following steps:
Step S102: and calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value.
Specifically, the controller 11 may sequentially obtain the logical address of each data block from the plurality of logical addresses, thereby performing calculation and obtaining the hash value. The target logical address is taken as an example for explanation.
In addition, the triggering condition of step S102 may be that the size of all data blocks received by the controller 11 exceeds a preset capacity threshold, or is triggered by a timer, where the preset capacity threshold may be equal to the available capacity presented to the user by the storage system shown in fig. 1, or an integer multiple of the available capacity.
step S103: and determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry.
specifically, the hash table may contain a plurality of entries, each entry having a position in the hash table (for example, the position of each entry may be indicated by a number), and the target hash value calculated in step 102 may be equal to the number of the target entry, or other value directly pointing to the number of the target entry. Moreover, since each entry of the hash table records a count value, a target count value can be obtained according to the target hash value.
Step S104: and determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relation between the count value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address.
The number of the stability levels may be set in advance by the controller 11.
optionally, an implementation is: and dividing the count value recorded in the table entry into a plurality of count value intervals, wherein each count value interval corresponds to one stability level. For example, assuming that 10 stability levels are preset, the corresponding relationship between the counting value interval and the stability level can be as shown in table 1:
TABLE 1
Accordingly, determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relationship between the count value and the stability level may specifically be: determining a target counting value interval according to the target counting value, wherein the target counting value is positioned in the target counting value interval; and determining the stability level of the data block corresponding to the target logical address according to the target count value interval and the corresponding relation shown in the table 1. For example, if the target count value is 3, then the corresponding stability level is 2.
step S105: and sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
Specifically, the controller 11 may send one logical address and stability level to the flash memory device 22 at a time, or may send a plurality of logical addresses and stability levels to the flash memory device 22 at a time.
in this embodiment, the controller 11 may obtain a hash value according to a logical address calculation, where the hash value corresponds to an entry in a hash table, and the entry records a count value, where the count value is used to indicate the number of modifications of the data block corresponding to the logical address, so that a stability level of the data block corresponding to the logical address may be obtained according to the count value, where the stability level may reflect the stability of the data block corresponding to the logical address, and the stability level and the logical address of the data block are sent to the flash memory device 22, so that the flash memory device 22 may store the data blocks of the same stability level in a centralized manner.
referring to fig. 5, fig. 5 is a flow chart illustrating a method for identifying data block stability according to another embodiment of the present invention, which can be applied to the memory system shown in fig. 1.
in the present embodiment, steps S201 to S204 describe a process of how a write data request triggers the update of the count value in the hash table. Steps S201 to S204 may be applied to the controller 11 shown in fig. 2, and the execution subject is the processor 118 in the controller 11.
in step S201, the controller 11 receives a write data request sent by the host, where the write data request includes a data object and address information of the data object.
In step S202, the controller 11 divides the data object into a plurality of data blocks having the same size.
in this embodiment, taking the size of the data block as 4KB as an example, when the data object is larger than 4KB, it needs to be split into multiple data blocks; when the data object is less than 4KB, then no splitting is required.
Accordingly, the controller 11 may obtain the logical address of each data block according to the address information and the multi-level mapping table, and store the logical addresses in the cache 120.
In step S203, the controller 11 determines a target logical address from the plurality of logical addresses.
specifically, the controller 11 may scan the plurality of logical addresses, reading each logical address in turn. For convenience of description, the following steps are described by taking the processing method of the target logical address as an example, and it is understood that the processing method of other logical addresses is the same as the target logical address.
In step S204, the target logical address is calculated according to a preset hash function to obtain a target hash value, where the target hash value points to one entry in the hash table, and the count value recorded in the entry is increased.
In some cases, because the entries of the hash table are limited, hash values generated by multiple logical addresses operating with the same hash function may point to the same entry, and thus there is no one-to-one correspondence between the logical addresses and the entries. In this case, in order to obtain the number of times of modifying the data block corresponding to the logical address, a plurality of Hash (Hash) functions may be preset, the logical address is calculated by using the Hash functions, so as to obtain a plurality of Hash values, and then the count value in the entry pointed by each Hash value is updated respectively. As shown in fig. 6, the logical address (LBA) may be calculated by using four hash functions (H1, H2, H3, and H4, respectively), to obtain four hash values, each of which points to one entry of the hash table, so as to add 1 to the count value recorded in each entry. With respect to how to obtain the most accurate number of modifications of the data block corresponding to the logical address by using the four hash values, reference may be made to the following description of step S208.
The following describes how to obtain the count value in its corresponding entry according to the LBA calculation by using a specific example.
assume that the hash table contains 10000 entries, which is equivalent to a one-dimensional array containing 10000 elements. hash [ x ] represents a value held by the xth entry of the hash table, where x is an integer greater than or equal to 1.
Assuming that the LBA is 100, when a data block is written in the logical address with the LBA of 100, the operation of updating the count value of the hash table is as follows:
Firstly, 4 hash values are obtained through 4 hash functions, and the 4 hash functions are respectively:
Hash value 1 ═ (LBA × 11)% (number of entries in hash table);
Hash value 2 ═ (LBA × 13)% (number of entries in hash table);
Hash value 3 ═ (LBA × 15)% (number of entries in hash table);
hash value 4 ═ (LBA × 17)% (number of entries in hash table);
In this case, "%" represents the remainder operation. From this, it can be known that the hash value 1 is 1100; hash value 1 is 1300; hash value 3 is 1500; hash value 4 1700.
The entries corresponding to the four hash values are hash [1100], hash [1300], hash [1500] and hash [1700], and then the count values in these entries are respectively increased by 1.
In the manner described in step S201-step S204, the controller 11 may update the count value in the hash table according to the received data object. For a logical address, the more data blocks are received, the count value in the corresponding entry is sequentially incremented. Therefore, the count value recorded in one entry reflects the stability of the data block stored in its corresponding logical address.
Step S205 to step S209 describe a process in which the controller 11 identifies the stability level of the data block corresponding to each logical address stored in the cache memory 120 and transmits the stability level to the flash memory device 22. Steps S205-S209 may be applied in the controller 11 shown in fig. 2, the execution subject of which is the processor 118 in the controller 11. It should be noted that the identification process of the stability level is not in sequence with the process of updating the count value described in steps S201 to S204.
in step S205, when the task is triggered, the controller 11 reads the plurality of logical addresses from the cache 120.
The task herein refers to a task that the controller 11 identifies a stable level of the data block stored at each logical address stored in the cache 120, and the trigger condition may be that a preset time interval is reached, or that the total size of the data object received by the controller 11 from the host exceeds a preset threshold, etc. These two conditions may also be set simultaneously, and when one of the conditions is satisfied, the controller 11 starts reading the plurality of logical addresses from the cache 120.
In step S206, the controller 11 determines a target logical address from the plurality of logical addresses.
Specifically, the controller 11 may scan the plurality of logical addresses, reading each logical address in turn. For convenience of description, the following steps are described by taking the processing manner of the target logical address as an example, and it is understood that the processing manner of other logical addresses is similar to that of the target logical address. The target logical address in step S206 may be the same as or different from the target logical address in steps S203 to S204.
In step S207, the controller 11 calculates the target logical address according to a preset hash function to obtain a target hash value.
Specifically, the preset hash function refers to the hash function in step S204. When there are a plurality of hash functions, there are a plurality of hash values obtained by calculation.
In step S208, the controller 11 determines a target entry corresponding to the target logical address in the hash table according to the target hash value, where a target count value is recorded in the target entry.
Still taking LBA as 100 as an example, the hash values obtained by applying the four hash functions include: hash value 1-1100; hash value 1 is 1300; hash value 3 is 1500; hash value 4 1700. Four count values can be obtained from the four table entries by the four hash values, and the smallest count value is selected from the four count values as the target count value.
It can be understood that, since the same count value may be referred to by multiple LBAs (where referred to, the hash value calculated by the LBA through the hash function points to the count value), the smaller the count value is, the less the corresponding entry is referred to by other LBAs, so that the smallest count value is the most accurate, and the most representative of the number of modifications of the corresponding data block is provided, in this embodiment, the target count value is equal to the smallest count value.
In step S209, the controller 11 obtains the stability level of the data block corresponding to the target logical address according to the target count value.
For a specific implementation, refer to step S104 in the embodiment shown in fig. 4, which is not described herein again.
In step S210, the controller 11 sends the target logical address and the stable level of the data block corresponding to the target logical address to the flash memory device 22.
for a specific implementation, refer to step S105 in the embodiment shown in fig. 4, which is not described herein again.
It is understood that the controller 11 may transmit a plurality of logical addresses and stabilization levels corresponding to the logical addresses to the flash memory device 22 in the manner described in steps S206 to S210.
After the controller 11 finishes processing each logical address stored in the cache 120, the task is completed, and the count values recorded in the hash table may all be subtracted by a fixed value, so that the count value may start to be incremented by a smaller base number when the task starts next time.
Steps S211 to S213 describe a process of collectively storing data blocks having the same stability level after the flash memory device 22 receives a plurality of logical addresses and stability levels transmitted from the controller 11. Steps S211 to S213 may be applied to the flash memory device (e.g., SSD) shown in fig. 3A and 3B, and the execution subject is the processor 218 in the flash memory device 22.
In step S211, the flash memory device 22 stores the logical addresses of the plurality of data blocks and the stability levels corresponding to the logical addresses.
Alternatively, a storage manner is to establish a mapping table in the cache 230 of the flash memory device 22, for storing the corresponding relationship between the logical address of the data block received from the controller 11 and the stable level of the data block.
optionally, another storage method is to store a plurality of arrays in the cache 230, where each array corresponds to one stability level. The logical addresses of the data blocks are stored in their corresponding arrays, respectively.
Optionally, another storage manner is to divide the cache 230 into a plurality of cache regions in advance, and each cache region corresponds to one stability level. And respectively recording the logical addresses of the data blocks in the corresponding cache areas.
in step S212, the flash memory device 22 obtains a stability level corresponding to the target logical address, where the stability level is used to indicate stability of the data block.
The target logical address is one of the logical addresses stored in the flash memory device 22, and the target logical address is taken as an example.
In step S213, the flash memory device 22 writes the data block corresponding to the target logical address into the block corresponding to the stability level according to the stability level corresponding to the target logical address.
In this embodiment, in order to move data blocks with the same stability level to the same block, a correspondence relationship between the block in the flash memory chip and the stability level may be established. According to the corresponding relation, the data block corresponding to the target logic address can be read from the original block and written into the block corresponding to the stable level of the data block. The correspondence between the block and the stability level in the flash memory chip may be pre-established, or the correspondence between the stability level and the block may be recorded after writing one data block or a plurality of data blocks having the same stability level into one block for the first time.
the specific step of reading the data block corresponding to the target logical address from the original block may be: in general, the cache 230 or the flash memory chip of the flash memory device 22 stores a mapping table, where the mapping table is used to store the corresponding relationship between the logical address and the physical address of each data block, so that the data block can be read from the storage space where the corresponding physical address is located according to the logical address and the mapping table.
by adopting the mode provided by the embodiment, the data blocks with the same stability level can be stored in one block. Then, for a block storing a data block with a high stability level, the stored data block has a low possibility of becoming invalid data, and as a whole, the block does not contain invalid data or contains only a small amount of invalid data, and such a block belongs to a block with a relatively high utilization rate, and is not recovered when garbage collection is performed on the flash memory device 22; for a block storing a data block with a lower stability level, the stored data block has a higher possibility of becoming invalid data, and if most data or most data in one block becomes invalid data, accordingly, the block contains less valid data, and the data to be migrated during garbage collection is less, thereby reducing write amplification. The effect of the present embodiment is mainly that the amount of valid data to be moved during garbage collection is reduced. It can be seen that the write amplification of the flash memory device 22 can be reduced whether the block storing the data block with the higher stability level or the block storing the data block with the lower stability level, thereby extending the lifetime of the flash memory device 22 to some extent.
In addition, a preferred embodiment is: combining the above-described steps S212 to S213 with the garbage collection operation, that is, when the flash memory device 22 needs to perform garbage collection, performing garbage collection according to the manner described in steps S212 to S213, specifically, when it is determined that the number of free blocks included in the flash memory chip is lower than the first threshold, sequentially finding out the blocks including the most invalid data from the flash memory chip, obtaining the logical address of the data block to be moved from these blocks, then according to the logical address, finding out the corresponding relationship between the logical address and the stability level, obtaining the stability level corresponding to the logical address, and then writing the data block corresponding to the logical address into the corresponding block.
Another preferred embodiment is: the steps S212 to S213 described above are combined with the polling operation, that is, when the flash memory device 22 needs to perform polling, polling is performed in the manner described in the steps S212 to S213, specifically, when a preset polling period arrives, blocks that are not erased within the longest time are sequentially searched from the flash memory chip, a logical address of a data block to be moved is obtained from the blocks, then, according to the logical address, the logical address and the corresponding relationship between the stable levels are searched, the stable level corresponding to the logical address is obtained, and then, the data block corresponding to the logical address is written into the corresponding block.
According to the two preferred embodiments provided above, centralized storage of data blocks with the same stability level can be realized when the flash memory device 22 performs garbage collection or polling, and since the flash memory device 22 originally performs data transfer when performing garbage collection or polling, this embodiment does not have an additional data transfer operation, and write amplification can be further reduced.
In another preferred embodiment, the steps S212 to S213 may not be combined with garbage collection or polling operation, that is, in this embodiment, the triggering condition for data block moving is different from the two previous embodiments, and the triggering condition is that the number of the logical addresses corresponding to the same stability level stored in the cache reaches the preset threshold.
Then, how to determine whether the number of the logical addresses corresponding to the same stability level reaches the preset threshold may include the following three implementation manners:
In the first embodiment, it is determined whether the number of logical addresses with the same stability level reaches a preset threshold according to the mapping table stored in the cache 230.
the second embodiment is to determine whether the number of logical addresses stored in an array in the cache 230 reaches a preset threshold.
The third embodiment is to determine whether the number of logical addresses stored in one cache region in the cache 230 reaches a preset threshold.
In this embodiment, when the number of logical addresses reaches the threshold, the data block corresponding to the plurality of logical addresses just fills up a free block. At this time, the block corresponding to the stable level in step S213 may be a free block.
referring to fig. 7, fig. 7 is a device 70 for identifying stability of a data block according to an embodiment of the present invention, where the device 70 is located in the controller 11 and includes:
The storage module 701 is configured to store a plurality of logical addresses and a hash table, where the hash table includes a plurality of entries, each entry corresponds to one logical address, and a count value is recorded in each entry, where the count value is used to indicate the number of times of modifying a data block corresponding to the logical address.
A calculating module 702, configured to calculate a target logical address in the multiple logical addresses according to a preset hash function, so as to obtain a target hash value; and determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry.
A determining module 703, configured to determine, according to the target count value and a corresponding relationship between the count value and a stability level, a stability level of the data block corresponding to the target logical address, where the stability level is used to indicate stability of the data block corresponding to the target logical address;
a sending module 704, configured to send the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
In this embodiment, a hash value may be obtained by calculating according to a logical address, where the hash value corresponds to an entry in a hash table, and a count value is recorded in the entry, where the count value is used to indicate the number of modifications of a data block corresponding to the logical address, so that a stability level of the data block corresponding to the logical address may be obtained according to the count value, where the stability level may reflect the stability of the data block corresponding to the logical address, and the stability level and the logical address of the data block are sent to the flash memory device 22, so that the flash memory device 22 may store the data blocks with the same stability level in a centralized manner.
Optionally, in the above embodiment, the correspondence between the count value and the stability level includes a correspondence between a count value interval and the stability level; a determining module 703, configured to determine a target count value interval according to the target count value, where the target count value is located in the target count value interval; and determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
in addition, in the above embodiment, the calculating module 702 is further configured to obtain a target logical address in the plurality of logical addresses before the target logical address is calculated according to a preset hash function; calculating according to the target logical address and the hash function to obtain the target hash value; determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry; and increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
Optionally, the calculating module 702 is further configured to subtract a fixed value from the target count value recorded in the target table entry after the target logical address and the stable level of the data block corresponding to the target logical address are sent to the flash memory device.
An embodiment of the present invention further provides a computer program product for data processing, which includes a computer-readable storage medium storing program code, where the program code includes instructions for executing the method flow described in any of the foregoing method embodiments.
It will be understood by those of ordinary skill in the art that the foregoing storage media include: various non-transitory machine-readable media that can store program code, such as a U-Disk, a removable hard Disk, a magnetic Disk, an optical Disk, a Random-Access Memory (RAM), a Solid State Disk (SSD), or a non-volatile Memory (non-volatile Memory).
finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same.
Claims (17)
1. A controller, comprising a processor and a cache, wherein a plurality of logical addresses are stored in the cache, and a hash table is also stored in the cache, the hash table includes a plurality of entries, each entry corresponds to one logical address, and a count value is recorded in each entry, and the count value is used to indicate the number of times of modifying a data block corresponding to the logical address;
The processor is used for calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value;
Determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry;
Determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relation between the count value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address;
And sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
2. The controller according to claim 1, wherein the correspondence of the count value to the stability level comprises a correspondence of a count value interval to the stability level;
The processor is specifically configured to determine a target count value interval according to the target count value, where the target count value is located in the target count value interval;
And determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
3. The controller of claim 1,
the processor is further configured to obtain a target logical address in the plurality of logical addresses before the target logical address is calculated according to a preset hash function;
calculating according to the target logical address and the hash function to obtain the target hash value;
determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry;
And increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
4. the controller of claim 1,
the processor is further configured to subtract a fixed value from the target count value recorded in the target entry after the target logical address and the stable level of the data block corresponding to the target logical address are sent to the flash memory device.
5. the method for identifying the stability of the data block is applied to a controller, the controller comprises a processor and a cache, a plurality of logical addresses are stored in the cache, a hash table is also stored in the cache, the hash table comprises a plurality of entries, each entry corresponds to one logical address, a count value is recorded in each entry, and the count value is used for indicating the number of times of modification of the data block corresponding to the logical address; the method is performed by the processor and comprises:
Calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value;
determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry;
Determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relation between the count value and the stability level, wherein the stability level is used for representing the stability of the data block corresponding to the target logical address;
And sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
6. The method of claim 5, wherein the count value and stability level correspondence comprises a count value interval and stability level correspondence;
Determining the stability level of the data block corresponding to the target logical address according to the target count value and the corresponding relationship between the count value and the stability level includes:
Determining a target counting value interval according to the target counting value, wherein the target counting value is positioned in the target counting value interval;
And determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
7. The method of claim 5, wherein before the calculating the target logical address of the plurality of logical addresses according to the preset hash function, the method further comprises:
acquiring the target logical address;
Calculating according to the target logical address and the hash function to obtain the target hash value;
Determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry;
and increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
8. The method of claim 5, wherein after sending the target logical address and the stabilization level of the data block corresponding to the target logical address to a flash memory device, the method further comprises: and subtracting a fixed value from the target count value recorded in the target table entry.
9. A memory system comprising a controller according to any one of claims 1 to 4 and a flash memory device; the flash memory device comprises a main controller and a flash memory chip, wherein the flash memory chip comprises a plurality of blocks, and the main controller comprises a processor;
The processor is configured to obtain a stability level corresponding to a target logical address, where the stability level is used to indicate stability of a data block;
And writing the data block corresponding to the target logical address into the block corresponding to the stability level according to the stability level corresponding to the target logical address.
10. The storage system according to claim 9, further comprising:
And searching the block containing the most invalid data in the flash memory chip, wherein the block containing the most invalid data comprises the data block corresponding to the target logical address.
11. The storage system according to claim 9, further comprising:
And searching the unerased block in the longest time in the flash memory chip, wherein the unerased block in the longest time comprises the data block corresponding to the target logical address.
12. The storage system of claim 9, wherein the master controller further comprises a cache;
The obtaining of the stability level corresponding to the target logical address includes: and when the number of the logic addresses stored in the cache is determined to reach a preset threshold value, obtaining a stability level corresponding to the target logic address, wherein the stability level corresponding to the logic address is the same as the stability level corresponding to the target logic address.
13. The storage system of claim 12, wherein the predetermined threshold is equal to a quotient of a capacity of the block divided by a size of the data block.
14. An apparatus for identifying data block stability, the apparatus located in a controller, comprising:
The storage module is used for storing a plurality of logical addresses and a hash table, the hash table comprises a plurality of table entries, each table entry corresponds to one logical address, a count value is recorded in each table entry, and the count value is used for indicating the number of times of modifying a data block corresponding to the logical address;
The calculation module is used for calculating a target logical address in the plurality of logical addresses according to a preset hash function to obtain a target hash value; determining a target table entry corresponding to the target logical address in the hash table according to the target hash value, wherein a target count value is recorded in the target table entry;
a determining module, configured to determine, according to the target count value and a corresponding relationship between a count value and a stability level, a stability level of a data block corresponding to the target logical address, where the stability level is used to indicate stability of the data block corresponding to the target logical address;
And the sending module is used for sending the target logical address and the stable level of the data block corresponding to the target logical address to a flash memory device.
15. The apparatus of claim 14, wherein the count value and stability level correspondence comprises a count value interval and stability level correspondence;
The determining module is specifically configured to determine a target count value interval according to the target count value, where the target count value is located in the target count value interval; and determining the stability level of the data block corresponding to the target logical address according to the target counting value interval and the corresponding relation between the counting value interval and the stability level.
16. The apparatus of claim 14,
The calculation module is further configured to obtain a target logical address in the plurality of logical addresses before the target logical address is calculated according to a preset hash function;
calculating according to the target logical address and the hash function to obtain the target hash value;
determining the target table entry according to the target hash value, wherein a count value is recorded in the target table entry;
And increasing the count value recorded in the target table entry, wherein the target count value is equal to the increased count value recorded in the target table entry.
17. the apparatus of claim 14,
The calculation module is further configured to subtract a fixed value from the target count value recorded in the target table entry after the target logical address and the stable level of the data block corresponding to the target logical address are sent to the flash memory device.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2014/094655 WO2016101145A1 (en) | 2014-12-23 | 2014-12-23 | Controller, method for identifying data block stability and storage system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105917303A CN105917303A (en) | 2016-08-31 |
| CN105917303B true CN105917303B (en) | 2019-12-06 |
Family
ID=56148884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480035916.9A Active CN105917303B (en) | 2014-12-23 | 2014-12-23 | Controller, method for identifying stability of data block and storage system |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105917303B (en) |
| WO (1) | WO2016101145A1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286995B (en) * | 2018-03-19 | 2022-02-25 | 北京兆易创新科技股份有限公司 | Data reading and writing method and device |
| CN108920108B (en) * | 2018-07-13 | 2022-02-01 | 深圳忆联信息系统有限公司 | Cold data screening method and device, computer equipment and storage medium |
| CN108984124B (en) * | 2018-07-13 | 2022-03-25 | 深圳忆联信息系统有限公司 | Method and device for reducing write amplification, computer equipment and storage medium |
| CN110502451B (en) * | 2019-07-10 | 2023-01-06 | 深圳市金泰克半导体有限公司 | Solid state disk garbage recycling method and device, solid state disk and storage medium |
| CN112328512B (en) * | 2020-09-22 | 2023-07-28 | 北京计算机技术及应用研究所 | Cache synchronization system and method applied to multi-control storage system |
| CN112732178B (en) * | 2020-12-29 | 2024-02-13 | 北京浪潮数据技术有限公司 | SSD data clearing method and related device |
| CN113342615B (en) * | 2021-06-29 | 2022-08-26 | 海光信息技术股份有限公司 | Command monitoring method, device, controller, system, equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103135945A (en) * | 2013-03-25 | 2013-06-05 | 中国人民解放军国防科学技术大学 | Multi-channel dynamic read-write dispatching method used in solid state drive (SSD) |
| CN103942148A (en) * | 2013-01-21 | 2014-07-23 | 擎泰科技股份有限公司 | System and method of wear leveling for a non-volatile memory |
| CN103942159A (en) * | 2014-03-19 | 2014-07-23 | 华中科技大学 | Data read-write method and device based on mixed storage device |
| CN103942010A (en) * | 2013-01-22 | 2014-07-23 | Lsi公司 | Management of and region selection for writes to non-volatile memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5715455A (en) * | 1995-05-18 | 1998-02-03 | International Business Machines Corporation | Apparatus and method for storing file allocation table efficiently in memory |
-
2014
- 2014-12-23 WO PCT/CN2014/094655 patent/WO2016101145A1/en active Application Filing
- 2014-12-23 CN CN201480035916.9A patent/CN105917303B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942148A (en) * | 2013-01-21 | 2014-07-23 | 擎泰科技股份有限公司 | System and method of wear leveling for a non-volatile memory |
| CN103942010A (en) * | 2013-01-22 | 2014-07-23 | Lsi公司 | Management of and region selection for writes to non-volatile memory |
| CN103135945A (en) * | 2013-03-25 | 2013-06-05 | 中国人民解放军国防科学技术大学 | Multi-channel dynamic read-write dispatching method used in solid state drive (SSD) |
| CN103942159A (en) * | 2014-03-19 | 2014-07-23 | 华中科技大学 | Data read-write method and device based on mixed storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016101145A1 (en) | 2016-06-30 |
| CN105917303A (en) | 2016-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105917303B (en) | Controller, method for identifying stability of data block and storage system | |
| US10713161B2 (en) | Memory system and method for controlling nonvolatile memory | |
| US10789162B2 (en) | Memory system and method for controlling nonvolatile memory | |
| US9772790B2 (en) | Controller, flash memory apparatus, method for identifying data block stability, and method for storing data in flash memory apparatus | |
| US10761731B2 (en) | Array controller, solid state disk, and method for controlling solid state disk to write data | |
| US9229876B2 (en) | Method and system for dynamic compression of address tables in a memory | |
| KR102094236B1 (en) | Storage device and computer system | |
| KR20170009706A (en) | Storage device for reducing duplicated data and operation method thereof | |
| CN108475230B (en) | Storage system and system garbage recycling method | |
| CN108027764B (en) | Memory mapping of convertible leaves | |
| US20140223075A1 (en) | Physical-to-logical address map to speed up a recycle operation in a solid state drive | |
| CN111159059A (en) | Garbage recycling method and device and nonvolatile storage equipment | |
| CN112306898A (en) | Storage device, operation method thereof and electronic device comprising same | |
| JP2014220021A (en) | Information processor, control circuit, control program, and control method | |
| US9575883B2 (en) | Control device, storage device, and storage control method | |
| TW201624490A (en) | Memory device and non-transitory computer readable recording medium | |
| CN110389706B (en) | Fingerprint recovery method and storage system | |
| KR101716348B1 (en) | Memory system, operating method thereof and computing system including the same | |
| TW201624491A (en) | Information processing device and non-transitory computer readable recording medium | |
| US11941246B2 (en) | Memory system, data processing system including the same, and operating method thereof | |
| US20240248644A1 (en) | Memory system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |