CN105911318B - A kind of method of electric energy meter calibrating apparatus output harmonic wave, subharmonic and m-Acetyl chlorophosphonazo - Google Patents
A kind of method of electric energy meter calibrating apparatus output harmonic wave, subharmonic and m-Acetyl chlorophosphonazo Download PDFInfo
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Abstract
一种电能表检定装置输出谐波、次谐波和简谐波的方法,包括采用电能表检定装置原有能输出工频波形、可叠加工频整数倍谐波的第一信号源,本方法还增加一个只产生次谐波及间谐波的第二信号源。所述方法将第一信号源的输出与第二信号源的输出通过运算放大器搭建的加法器叠加合成;即可将第一将信号源的工频信号、工频整数倍谐波信号和第二信号源输出的次谐波信号、间谐波信号叠加合成一个波形信号;再将合成信号输出到功率放大器放大输出。本发明解决了传统方法在1套信号源上难以叠加任意谐波的问题,适用于电能表检定装置不仅要输出工频信号以及工频整数倍谐波信号,还能叠加或输出次谐波和间谐波,用于研究、分析谐波对电能计量的影响。
A method for outputting harmonics, sub-harmonics and simple harmonics of an electric energy meter verification device, including using a first signal source that can output power frequency waveforms and can superimpose power frequency integer multiple harmonics of the electric energy meter verification device. A second signal source that generates only sub-harmonics and inter-harmonics is also added. In the method, the output of the first signal source and the output of the second signal source are superimposed and synthesized through an adder built by an operational amplifier; that is, the power frequency signal of the first signal source, the power frequency integer multiple harmonic signal and the second The sub-harmonic signal and inter-harmonic signal output by the signal source are superimposed and synthesized into a waveform signal; then the synthesized signal is output to the power amplifier for amplification and output. The invention solves the problem that it is difficult to superimpose arbitrary harmonics on a set of signal sources in the traditional method, and is suitable for electric energy meter verification devices that not only output power frequency signals and power frequency integer multiple harmonic signals, but also superimpose or output subharmonics and Inter-harmonics, used to study and analyze the influence of harmonics on electric energy metering.
Description
技术领域technical field
本发明涉及一种电能表检定装置输出谐波、次谐波和简谐波的方法,属计量检测设备技术领域。The invention relates to a method for outputting harmonics, sub-harmonics and simple harmonics by a verification device of an electric energy meter, which belongs to the technical field of measuring and testing equipment.
背景技术Background technique
目前电子技术飞速发展,大量的非线性用电设备如电弧炼钢炉、冲击负荷、电力电子调频、电力机车牵引、电力充电设备接入电网。这些负荷的接入将对电网产生很大的干扰,不仅会产生50Hz工频整数倍的干扰谐波,还会产生频率大于50Hz但非工频整数倍频率的间谐波(如79Hz,63Hz,111Hz等),也可能会产生频率小于20Hz但非工频整数倍频率的次谐波(如9Hz,13Hz,11Hz等),现有的电能表检定装置只能产生检定电能表所需的工频输出,也可产生或在工频输出的基础上叠加2-21次谐波输出,即现有的电能表检定装置只能产生或叠加的谐波均为工频的整数倍频,无法产生或在工频基础上叠加非工频频率整数倍的间谐波和次谐波。At present, with the rapid development of electronic technology, a large number of non-linear electrical equipment such as electric arc steelmaking furnace, impact load, power electronic frequency modulation, electric locomotive traction, and electric charging equipment are connected to the grid. The access of these loads will cause great interference to the power grid. Not only will it generate interference harmonics that are integer multiples of the power frequency of 50Hz, but also interharmonics with frequencies greater than 50Hz but not integer multiples of the power frequency (such as 79Hz, 63Hz, 111Hz, etc.), may also produce sub-harmonics with a frequency less than 20Hz but not an integer multiple of the power frequency (such as 9Hz, 13Hz, 11Hz, etc.), the existing energy meter verification device can only generate the power frequency required for the verification of the energy meter Output, can also generate or superimpose 2-21 harmonic output on the basis of power frequency output, that is, the existing electric energy meter verification device can only generate or superimpose harmonics that are integer multiples of power frequency, and cannot generate or On the basis of the power frequency, inter-harmonics and sub-harmonics that are integer multiples of non-power frequency frequencies are superimposed.
目前电能表检定装置产生工频信号输出的原理为:将1个周期的正弦波波形离散成N个点,以3600点为例,每2个离散点间相差0.1°。将每个离散点号及其对应角度的正弦值一一对应存储在RAM中,离散点点号作为RAM的存储地址,其对应角度正弦值作为存储数值。比如第1点,地址为0001,其数值为Asin0.1;第k点地址为:000k,其数值为Asin0.1k。工作时CPU将存储在RAM中的数值按顺序送到D/A进行数模转换变成模拟信号,即离散点数值从RAM发送到D/A的节拍频率为:50×3600=180000Hz。模拟信号再经功率放大器输出即可供检定使用。具体工作流程如图1原电能表检定装置第一信号源工作示意图所示。At present, the principle of power frequency signal output generated by the verification device of the electric energy meter is: to discretize the sine wave waveform of one cycle into N points, taking 3600 points as an example, the difference between every two discrete points is 0.1°. Each discrete point number and the sine value of the corresponding angle are stored in the RAM in one-to-one correspondence, the discrete point number is used as the storage address of the RAM, and the corresponding angle sine value is used as the stored value. For example, the address of point 1 is 0001, and its value is Asin0.1; the address of point k is: 000k, and its value is Asin0.1k. When working, the CPU sends the values stored in the RAM to the D/A in sequence for digital-to-analog conversion into analog signals, that is, the beat frequency at which the discrete point values are sent from the RAM to the D/A is: 50×3600=180000Hz. The analog signal can be used for verification after being output by the power amplifier. The specific work flow is shown in Figure 1, the working diagram of the first signal source of the original electric energy meter verification device.
第一信号源包括CPU、第一存储器RAM、数模转换器D/A、第一数模转换器D/A(1)、第二数模转换器D/A(2)、驱动电路和电压频率转换器。如图1所示。The first signal source includes CPU, first memory RAM, digital-to-analog converter D/A, first digital-to-analog converter D/A (1), second digital-to-analog converter D/A (2), driving circuit and voltage frequency converter. As shown in Figure 1.
输出或叠加工频整数倍频率谐波的方法同上,还是将1个工频周期的波形离散成3600个点。将每个离散点号及其对应的函数值一一对应存储在RAM中,离散点点号作为RAM的存储地址,其对应函数值作为存储数值。第i点的数值为: The method of outputting or superimposing the integer multiple frequency harmonics of the power frequency is the same as above, and the waveform of 1 power frequency cycle is still discretized into 3600 points. Each discrete point number and its corresponding function value are stored in the RAM in one-to-one correspondence, the discrete point number is used as a storage address of the RAM, and its corresponding function value is used as a stored value. The value of point i is:
Mi:为函数第i点的函数值Mi: the function value of the i-th point of the function
Ak:第k次谐波的幅值Ak: Amplitude of the kth harmonic
以上函数表示计算合成波形第i点的函数值的公式,就是将所需要叠加的各次谐波在第i点的数值进行相加即可。由于工频整数倍谐波的频率为工频信号频率的整数倍,合成波形的包络线周期与工频波形周期相同,也就是用3600个离散点就能全面准确地代表合成波形。这种方法对于工频整数倍的谐波是非常有效的,但对于非工频频率整数倍的谐波是难以法实现的。比如要在工频输出的基础上叠加频率为77Hz的谐波,那么包络2种频率正弦波的包络线周期是2个频率正弦波周期的最小公倍数,即:T=20×(1000/77)=259.74026ms,是工频波形周期的1000/77=12.99倍,如果同样要确保工频输出波形每个采样点间隔为0.1°,那存储的点数必须为:3600×12.99=46753.267个,并且叠加的波形频率越高,需要存储的点数越多,对CPU的计算量和RAM的存储空间要求较高。关键是很多周期可能是无限小数或是循环小数,所以无法实现。The above function represents the formula for calculating the function value of the i-th point of the composite waveform, which is to add the values of the i-th point of each harmonic that needs to be superimposed. Since the frequency of the integer multiple harmonics of the power frequency is an integer multiple of the frequency of the power frequency signal, the cycle of the envelope curve of the synthesized waveform is the same as that of the power frequency waveform, that is, the synthesized waveform can be fully and accurately represented by 3600 discrete points. This method is very effective for harmonics of integer multiples of power frequency, but it is difficult to achieve harmonics of integer multiples of non-power frequency frequencies. For example, to superimpose harmonics with a frequency of 77Hz on the basis of the power frequency output, then the envelope period of the two frequency sine waves is the least common multiple of the two frequency sine wave periods, namely: T=20×(1000/ 77)=259.74026ms, which is 1000/77=12.99 times of the period of the power frequency waveform. If it is also necessary to ensure that the interval of each sampling point of the power frequency output waveform is 0.1°, the number of stored points must be: 3600×12.99=46753.267, Moreover, the higher the frequency of the superimposed waveform, the more points need to be stored, and the higher the requirements for the calculation amount of the CPU and the storage space of the RAM. The key is that many cycles may be infinite decimals or recurring decimals, so it cannot be realized.
因此需要找到一种电能表检定装置输出谐波、次谐波和间谐波的方法,实现电能表检定装置不仅可输出工频、可叠加工频整数倍谐波,也能输出间谐波、次谐波。用于对电能表的综合误差进行检测和评估,为研究间谐波、次谐波对电能计量的影响提供理论依据。Therefore, it is necessary to find a method for outputting harmonics, sub-harmonics and inter-harmonics of the electric energy meter verification device, so that the electric energy meter verification device can not only output the power frequency and superimpose the integer multiple harmonics of the power frequency, but also output the inter-harmonic, subharmonic. It is used to detect and evaluate the comprehensive error of the electric energy meter, and provides a theoretical basis for studying the influence of inter-harmonic and sub-harmonic on electric energy measurement.
发明内容Contents of the invention
本发明的目的是,为了解决电能表检定装置采用传统方法无法在工频输出的基础上叠加输出次谐波、间谐波的状况,即解决传统方法存在叠加次谐波、间谐波时,会因合成波形的包络周期大、周期不确定、可能是为非整数或无限循环小数等情况而无法实现的问题,本发明提出一种电能表检定装置输出谐波、次谐波和简谐波的方法。The purpose of the present invention is, in order to solve the situation that the energy meter verification device cannot superimpose output sub-harmonics and inter-harmonics on the basis of power frequency output by traditional methods, that is, when there are superimposed sub-harmonics and inter-harmonics in the traditional method, Due to the large envelope period of the synthesized waveform, the period is uncertain, and it may be a non-integer or an infinite cycle of decimals, the present invention proposes an electric energy meter verification device that outputs harmonics, sub-harmonics and simple harmonics. way of waves.
本发明的技术方案是,本发明一种电能表检定装置输出谐波、次谐波和简谐波的方法,保留电能表检定装置原有能输出工频波形、可叠加工频整数倍谐波的部分称为第一信号源,另外再增加一个次谐波信号源电路,称为第二信号源,第二信号源只产生次谐波及间谐波。The technical solution of the present invention is that a method for outputting harmonics, sub-harmonics and simple harmonics of an electric energy meter verification device in the present invention retains the original output power frequency waveform of the electric energy meter verification device and can superimpose power frequency integer multiple harmonics The part is called the first signal source, and another sub-harmonic signal source circuit is added, which is called the second signal source. The second signal source only generates sub-harmonics and inter-harmonics.
本发明方法将第一信号源的输出与第二信号源的输出通过运算放大器搭建的加法器叠加合成;即可将第一将信号源的工频信号、工频整数倍谐波信号和第二信号源输出的次谐波信号、间谐波信号叠加合成一个波形信号;再将合成信号输出到功率放大器放大输出。In the method of the present invention, the output of the first signal source and the output of the second signal source are superimposed and synthesized through an adder built by an operational amplifier; that is, the power frequency signal of the first signal source, the power frequency integer multiple harmonic signal and the second The sub-harmonic signal and inter-harmonic signal output by the signal source are superimposed and synthesized into a waveform signal; then the synthesized signal is output to the power amplifier for amplification and output.
所述第二信号源包括主电路、调幅电路和调频电路。The second signal source includes a main circuit, an amplitude modulation circuit and a frequency modulation circuit.
所述主电路包括CPU、第二存储器RAM(2)、第三数模转换器D/A(3)。工作时,CPU将1个周期的次谐波或间谐波信号离散成3600点,每个间隔为0.1°;将每个离散点号及其对应角度的正弦值一一对应存储在第二存储器RAM(2)中,离散点号作为第二存储器RAM(2)的存储地址,其对应角度正弦值作为存储数值;CPU将存储在第二存储器RAM(2)中的数值按顺序送到第三数模转换器D/A(3)进行数模转换变成模拟信号;输出波形的初始相位角设置和调整也通过主电路实现;电能表检定装置需输出三相电压和三相电流共6相输出,A、B、C各相差120°,这6相都共用第三存储器RAM(3)中的数据,只是读取第二存储器RAM(2)中数据的起始地址不一。The main circuit includes a CPU, a second memory RAM (2), and a third digital-to-analog converter D/A (3). When working, the CPU discretizes the sub-harmonic or inter-harmonic signal of one period into 3600 points, each interval is 0.1°; each discrete point number and the sine value of the corresponding angle are stored in the second memory in one-to-one correspondence In RAM (2), the discrete point number is used as the storage address of the second memory RAM (2), and its corresponding angle sine value is used as the stored value; the CPU sends the values stored in the second memory RAM (2) to the third The digital-to-analog converter D/A (3) performs digital-to-analog conversion into an analog signal; the initial phase angle setting and adjustment of the output waveform are also realized through the main circuit; the electric energy meter verification device needs to output three-phase voltage and three-phase current with a total of 6 phases The output, A, B, and C have a phase difference of 120°, and these 6 phases share the data in the third memory RAM (3), but the starting address for reading the data in the second memory RAM (2) is different.
所述调幅电路包括CPU、第四数模转换器D/A(4)和第二驱动(2)电路。所述调幅电路负责通过控制主电路第三数模转换器D/A(3)输出直流信号的幅值来实现调整主电路第三数模转换器D/A(3)的基准电压。主电路中的第三数模转换器D/A(3)一个特性就是其输出信号的幅值与基准电压的大小成正比,通过CPU将所需设置的幅值数字值发送到第四数模转换器D/A(4);第四数模转换器D/A(4)将该数字值转换为基准电压输出作为主电路第三数模转换器D/A(3)的基准电压,这样即可通过CPU改变第四数模转换器D/A(4)的输出电压来改变第三数模转换器D/A(3)的基准电压,实现输出信号的幅值控制。The amplitude modulation circuit includes a CPU, a fourth digital-to-analog converter D/A (4) and a second drive (2) circuit. The amplitude modulation circuit is responsible for adjusting the reference voltage of the third digital-to-analog converter D/A(3) of the main circuit by controlling the amplitude of the DC signal output by the third digital-to-analog converter D/A(3) of the main circuit. A characteristic of the third digital-to-analog converter D/A (3) in the main circuit is that the amplitude of its output signal is proportional to the size of the reference voltage, and the required amplitude digital value is sent to the fourth digital-analog converter through the CPU. Converter D/A (4); the fourth digital-to-analog converter D/A (4) converts the digital value into a reference voltage output as the reference voltage of the third digital-to-analog converter D/A (3) of the main circuit, so That is, the reference voltage of the third digital-to-analog converter D/A (3) can be changed by changing the output voltage of the fourth digital-to-analog converter D/A (4) through the CPU, so as to realize amplitude control of the output signal.
所述调频电路包括CPU、第五数模转换器D/A(5)和第二电压频率转换器V/F(2)转换电路。所述调频电路负责控制主电路第三数模转换器D/A(3)输出波形的频率。第三数模转换器D/A(3)的另一个特性就是其输出信号的频率与转换节拍成正比,通过CPU将所需设置的频率数字值发送到第五数模转换器D/A(5)。第五数模转换器D/A(5)将该数字值转换为模拟电压输出到第二电压频率转换器V/F(2)转换电路,第二电压频率转换器V/F(2)转换电路将电压转换为频率信号输出到第二存储器RAM(2)和第三数模转换器D/A(3)作为第二存储器RAM(2)和第三数模转换器D/A(3)的送数及转换节拍,这样即可通过CPU改变第五数模转换器D/A(5)的输出电压,再经第二电压频率转换器V/F(2)变换来改变第三数模转换器D/A(3)的输出频率,实现输出信号的频率控制。The frequency modulation circuit includes a CPU, a fifth digital-to-analog converter D/A (5) and a second voltage-to-frequency converter V/F (2) conversion circuit. The frequency modulation circuit is responsible for controlling the frequency of the output waveform of the third digital-to-analog converter D/A (3) of the main circuit. Another characteristic of the third digital-to-analog converter D/A (3) is that the frequency of its output signal is proportional to the conversion beat, and the frequency digital value to be set is sent to the fifth digital-to-analog converter D/A ( 5). The fifth digital-to-analog converter D/A (5) converts the digital value into an analog voltage and outputs it to the second voltage-frequency converter V/F (2) conversion circuit, and the second voltage-frequency converter V/F (2) converts The circuit converts the voltage into a frequency signal and outputs it to the second memory RAM (2) and the third digital-to-analog converter D/A (3) as the second memory RAM (2) and the third digital-to-analog converter D/A (3) The number of sending and conversion beats, so that the output voltage of the fifth digital-to-analog converter D/A (5) can be changed by the CPU, and then the third digital-to-analog converter can be changed through the conversion of the second voltage-frequency converter V/F (2). The output frequency of the converter D/A (3) realizes the frequency control of the output signal.
所述第二信号源与第一信号源都受第一信号源的CPU控制。Both the second signal source and the first signal source are controlled by the CPU of the first signal source.
所述加法器叠加合成使用了2级运算放大电路,其中第一级采用的是反向加法电路,第二级再加一反相器。Said adder superimposes and synthesizes using a 2-stage operational amplifier circuit, wherein the first stage adopts an inverse addition circuit, and the second stage adds an inverter.
所述加法器叠加合成电路如下:所述第二信号源产生了间谐波和次谐波输出后,再将第一信号源与第二信号源的输出信号进行相加,其中第一信号源的信号输出通过电阻R1一路接加法器的“-”端,另一路接电阻Rf,再通过电阻Rf连接加法器的输出端;第二信号源的输出通过电阻R2接加法器的“-”端,输入到加法电路;加法器的“+” 端接地;加法器的输出端一路通过电阻Rs连接反向器的“-”端;加法器的输出端的另一路通过电阻Rf连接反向器的输出端;反向器的“+”端接地。其中,V1为第一信号源输出电压;V2为第二信号源输出电压。The adder superposition synthesis circuit is as follows: after the second signal source generates inter-harmonic and sub-harmonic outputs, the output signals of the first signal source and the second signal source are added, wherein the first signal source The signal output of the signal source is connected to the "-" end of the adder through the resistor R1, the other is connected to the resistor Rf, and then connected to the output end of the adder through the resistor Rf; the output of the second signal source is connected to the "-" end of the adder through the resistor R2 , input to the addition circuit; the "+" end of the adder is grounded; one output end of the adder is connected to the "-" end of the inverter through the resistor Rs; the other output end of the adder is connected to the output of the inverter through the resistor Rf terminal; the "+" terminal of the inverter is grounded. Wherein, V1 is the output voltage of the first signal source; V2 is the output voltage of the second signal source.
本发明具体工作原理如图2工频、谐波、次谐波、间谐波信号发生工作示意图所示。The specific working principle of the present invention is shown in Fig. 2, a working schematic diagram of power frequency, harmonic, sub-harmonic and inter-harmonic signal generation.
第二信号源的工作原理为:CPU将1个周期的次谐波或间谐波离散成3600个点,将每个离散点号及其对应角度的正弦值一一对应存储在第二存储器RAM2中,离散点点号作为第二存储器RAM2的存储地址,其对应角度正弦值作为存储数值。比如第1点,地址为0001,其数值为Asin0.1;第k点地址为:000k,其数值为 Asin0.1k。工作时CPU将存储在第二存储器RAM2中的数值按顺序送到第三数模转换器D/A(3)进行数模转换变成模拟信号,第二信号源实现次谐波或间谐波的关键在于CPU控制第二存储器RAM2向第三数模转换器D/A(3)送数及第三数模转换器D/A(3)进行数模转换的频率来实现次谐波或间谐波的频率。The working principle of the second signal source is: the CPU discretizes the sub-harmonic or inter-harmonic of one cycle into 3600 points, and stores each discrete point number and the sine value of the corresponding angle in the second memory RAM2 Among them, the discrete point number is used as the storage address of the second memory RAM2, and its corresponding angle sine value is used as the stored value. For example, the address of point 1 is 0001, and its value is Asin0.1; the address of point k is: 000k, and its value is Asin0.1k. When working, the CPU sends the values stored in the second memory RAM2 to the third digital-to-analog converter D/A (3) in order for digital-to-analog conversion into analog signals, and the second signal source realizes sub-harmonic or inter-harmonic The key is that the CPU controls the second memory RAM2 to send data to the third digital-to-analog converter D/A (3) and the frequency of the third digital-to-analog converter D/A (3) to perform digital-to-analog conversion to achieve sub-harmonic or intermittent Harmonic frequency.
比如要实现 20Hz的次谐波输出,20Hz的次谐波的周期为50ms,在50ms的周期内要实现3600个点完成数模转换,那CPU控制第二存储器RAM2向第三数模转换器D/A(3)将3600点数送到第三数模转换器D/A(3)进行数模转换,转换频率为:f=3600/50=72Hz。For example, to realize the sub-harmonic output of 20Hz, the cycle of the sub-harmonic of 20Hz is 50ms, within the cycle of 50ms to realize 3600 points to complete the digital-to-analog conversion, then the CPU controls the second memory RAM2 to the third digital-to-analog converter D /A (3) sends 3600 points to the third digital-to-analog converter D/A (3) for digital-to-analog conversion, and the conversion frequency is: f=3600/50=72Hz.
同样要实现80Hz的间谐波输出时,80Hz的间谐波的周期为12.5ms,在12.5ms的时间内要完成3600个点的数模转换,即CPU控制第二存储器RAM2向第三数模转换器D/A(3)送数,第三数模转换器D/A(3)进行数模转换的频率为:f=3600/12.5=288Hz。Similarly, when the 80Hz interharmonic output is to be realized, the period of the 80Hz interharmonic is 12.5ms, and the digital-to-analog conversion of 3600 points must be completed within 12.5ms, that is, the CPU controls the second memory RAM2 to the third digital-to-analog The converter D/A (3) sends numbers, and the frequency of the third digital-to-analog converter D/A (3) for digital-to-analog conversion is: f=3600/12.5=288Hz.
产生了间谐波和次谐波输出后,再将第一信号源与第二信号源的输出信号进行相加,其中第一信号源的信号输出接图3的V1端,输入到加法电路;第二信号源的输出接到图3的V2端,输入到加法电路。加法器具体电路如附图3所示:工频及谐波信号源和次谐波及间谐波信号源合成工作示意图,加法器电路使用了2级运算放大电路,其中第一级采用的是反向加法电路,输出为Vo=-Vi,因此随后再加一反相器。After the inter-harmonic and sub-harmonic outputs are generated, the output signals of the first signal source and the second signal source are added, wherein the signal output of the first signal source is connected to the V1 terminal of Figure 3 and input to the addition circuit; The output of the second signal source is connected to the V2 terminal in FIG. 3 and input to the adding circuit. The specific circuit of the adder is shown in Figure 3: a schematic diagram of the synthesis of power frequency and harmonic signal sources and sub-harmonic and inter-harmonic signal sources. The adder circuit uses a two-stage operational amplifier circuit, of which the first stage uses The output of the reverse addition circuit is Vo=-Vi, so an inverter is then added.
图3中的R1=R2=Rf=Rs,Vo=-Rf/Rs[(-Rf/R1)×V1+(-Rf/R2)×V2]。因此加法器的最终输出结果为Vo=V1+V2。R1=R2=Rf=Rs in Fig. 3, Vo=-Rf/Rs[(-Rf/R1)×V1+(-Rf/R2)×V2]. Therefore, the final output of the adder is Vo=V1+V2.
本发明的有益效果是,本发明在电能表检定装置原有的工频输出、工频整数倍谐波输出的基础上,增加一套次谐波或间谐波信号发生器,再将2路信号通过运算放大器电路构建的加法器相加合成再输出,解决了传统方法在1套信号源上难以叠加任意谐波的问题。The beneficial effect of the present invention is that the present invention adds a set of sub-harmonic or inter-harmonic signal generators on the basis of the original power frequency output and power frequency integer multiple harmonic output of the electric energy meter verification device, and then 2 channels The signals are added and synthesized by the adder built by the operational amplifier circuit and then output, which solves the problem that it is difficult to superimpose any harmonics on a set of signal sources in the traditional method.
本发明适用于电能表检定装置不仅要输出工频信号以及工频整数倍谐波信号,还能叠加或输出次谐波和间谐波,用于研究、分析谐波对电能计量的影响。The invention is applicable to the verification device of the electric energy meter not only to output power frequency signals and power frequency integer multiple harmonic signals, but also to superimpose or output sub-harmonics and inter-harmonics for researching and analyzing the influence of harmonics on electric energy measurement.
附图说明Description of drawings
图1是原电能表检定装置信号源工作示意图;Fig. 1 is a working schematic diagram of the signal source of the original electric energy meter verification device;
图2是工频、谐波、次谐波、间谐波信号发生工作示意图;Figure 2 is a schematic diagram of the generation of power frequency, harmonic, sub-harmonic and inter-harmonic signals;
图3是工频及谐波信号源和次谐波及间谐波信号源合成工作示意图。Fig. 3 is a schematic diagram of synthesizing work of power frequency and harmonic signal sources and sub-harmonic and inter-harmonic signal sources.
具体实施方式Detailed ways
本发明的具体实施方式如下:The specific embodiment of the present invention is as follows:
本实施例的工频、谐波、次谐波、间谐波的信号源组成及工作原理如图2所示,次谐波、间谐波的第二信号源包括主电路、调幅电路和调频电路。The composition and working principle of the signal source of power frequency, harmonic, sub-harmonic and inter-harmonic in this embodiment are shown in Figure 2. The second signal source of sub-harmonic and inter-harmonic includes main circuit, amplitude modulation circuit and frequency modulation circuit.
本实施例第二信号源的主电路包括CPU、第二存储器RAM(2)和第三数模转换器D/A(3),工作时CPU将1个周期的次谐波或间谐波信号离散成3600点,每个间隔为0.1°。将每个离散点号及其对应角度的正弦值一一对应存储在第二存储器RAM(2)中,离散点号作为第二存储器RAM(2)的存储地址,其对应角度正弦值作为存储数值。比如第1点,地址为0001,其数值为Asin0.1;第k点地址为:000k,其数值为Asin0.1k。工作时CPU将存储在第二存储器RAM(2)中的数值按顺序送到第三数模转换器D/A(3)进行数模转换变成模拟信号。输出波形的初始相位角设置和调整也通过主电路实现,比如要设置输出波形初始相位角为30°,那CPU即可从第一RAM取数的起始地址可从第300点开始。电能表检定装置需输出三相电压和三相电流共6相输出,A、B、C各相差120°,这6相都共用第三存储器RAM(3)中的数据,只是读取第二存储器RAM(2)中数据的起始地址不一。The main circuit of the second signal source of the present embodiment includes a CPU, a second memory RAM (2) and a third digital-to-analog converter D/A (3). During work, the CPU converts a cycle of sub-harmonic or inter-harmonic signals Discrete into 3600 points, each interval is 0.1°. Store each discrete point number and the sine value of the corresponding angle in the second memory RAM (2) in one-to-one correspondence, the discrete point number is used as the storage address of the second memory RAM (2), and the corresponding angle sine value is used as the stored value . For example, the address of point 1 is 0001, and its value is Asin0.1; the address of point k is: 000k, and its value is Asin0.1k. When working, the CPU sends the values stored in the second memory RAM (2) to the third digital-to-analog converter D/A (3) in sequence for digital-to-analog conversion into analog signals. The setting and adjustment of the initial phase angle of the output waveform is also realized through the main circuit. For example, if the initial phase angle of the output waveform is set to 30°, then the CPU can start from the 300th point to fetch data from the first RAM. The watt-hour meter verification device needs to output three-phase voltage and three-phase current, a total of 6-phase output, A, B, C each have a difference of 120°, these 6 phases share the data in the third memory RAM (3), and only read the second memory The start addresses of data in RAM (2) are different.
本实施例第二信号源的调幅电路由CPU、第四数模转换器D/A(4)和第二驱动(2)电路组成,调幅电路负责通过控制主电路第三数模转换器D/A(3)输出直流信号的幅值来实现调整主电路第三数模转换器D/A(3)的基准电压。主电路中的第三数模转换器D/A(3)一个特性就是其输出信号的幅值与基准电压的大小成正比,本发明通过CPU将所需设置的幅值数字值发送到第四数模转换器D/A(4),第四数模转换器D/A(4)将该数字值转换为基准电压输出作为主电路第三数模转换器D/A(3)的基准电压,这样即可通过CPU改变第四数模转换器D/A(4)的输出电压来改变第三数模转换器D/A(3)的基准电压,实现输出信号的幅值控制。The amplitude modulation circuit of the second signal source in this embodiment is composed of CPU, the fourth digital-to-analog converter D/A (4) and the second drive (2) circuit. The amplitude modulation circuit is responsible for controlling the third digital-to-analog converter D/A of the main circuit. A(3) outputs the amplitude of the DC signal to adjust the reference voltage of the third digital-to-analog converter D/A(3) of the main circuit. A characteristic of the third digital-to-analog converter D/A (3) in the main circuit is that the amplitude of its output signal is proportional to the size of the reference voltage. The present invention sends the required amplitude digital value to the fourth through the CPU. Digital-to-analog converter D/A (4), the fourth digital-to-analog converter D/A (4) converts the digital value into a reference voltage output as the reference voltage of the third digital-to-analog converter D/A (3) of the main circuit , so that the CPU can change the output voltage of the fourth digital-to-analog converter D/A (4) to change the reference voltage of the third digital-to-analog converter D/A (3), so as to realize the amplitude control of the output signal.
本实施例第二信号源的调频电路包括CPU、第五数模转换器D/A(5)和第二电压频率转换器V/F(2)转换电路部分,调频电路负责控制主电路第三数模转换器D/A(3)输出波形的频率。第三数模转换器D/A(3)的另一个特性就是其输出信号的频率与转换节拍成正比,本发明通过CPU将所需设置的频率数字值发送到第五数模转换器D/A(5), 第五数模转换器D/A(5)将该数字值转换为模拟电压输出到第二电压频率转换器V/F(2)转换电路,第二电压频率转换器V/F(2)转换电路将电压转换为频率信号输出到第二存储器RAM(2)和第三数模转换器D/A(3)作为第二存储器RAM(2)和第三数模转换器D/A(3)的送数及转换节拍,这样即可通过CPU改变第五数模转换器D/A(5)的输出电压,再经第二电压频率转换器V/F(2)变换来改变第三数模转换器D/A(3)的输出频率,实现输出信号的频率控制。The frequency modulation circuit of the second signal source in this embodiment includes CPU, the fifth digital-to-analog converter D/A (5) and the second voltage-frequency converter V/F (2) conversion circuit part, and the frequency modulation circuit is responsible for controlling the third frequency of the main circuit. The frequency of the digital-to-analog converter D/A (3) output waveform. Another characteristic of the third digital-to-analog converter D/A (3) is that the frequency of its output signal is proportional to the conversion beat. The present invention sends the required frequency digital value to the fifth digital-to-analog converter D/A through the CPU. A(5), the fifth digital-to-analog converter D/A(5) converts the digital value into an analog voltage and outputs it to the second voltage-frequency converter V/F (2) conversion circuit, the second voltage-frequency converter V/ The F (2) conversion circuit converts the voltage into a frequency signal and outputs it to the second memory RAM (2) and the third digital-to-analog converter D/A (3) as the second memory RAM (2) and the third digital-to-analog converter D /A(3) sending number and conversion beat, so that the output voltage of the fifth digital-to-analog converter D/A(5) can be changed by the CPU, and then transformed by the second voltage-frequency converter V/F(2) to The output frequency of the third digital-to-analog converter D/A (3) is changed to realize the frequency control of the output signal.
本实施例分为2套信号源,第一信号源负责输出工频信号及工频整数倍谐波;第二信号源负责输出次谐波与间谐波。第二信号源与第一信号源的工作原理基本相同,输出不同频率的谐波可通过如前所述的调频电路实现。将第一信号源与第二信号源的输出波形经运算放大器构建的加法器相加合成,再经反向器输出及实现了电能表检定装置可输出工频、工频整数倍谐波、次谐波和间谐波。具体详见附图3:工频及谐波信号源和次谐波及间谐波信号源合成工作示意图。This embodiment is divided into two sets of signal sources. The first signal source is responsible for outputting power frequency signals and integer multiple harmonics of the power frequency; the second signal source is responsible for outputting sub-harmonics and inter-harmonics. The working principle of the second signal source is basically the same as that of the first signal source, and the output of harmonics of different frequencies can be realized through the frequency modulation circuit as mentioned above. The output waveforms of the first signal source and the second signal source are added and synthesized by the adder constructed by the operational amplifier, and then output through the inverter and realized that the electric energy meter verification device can output power frequency, power frequency integer multiple harmonics, sub Harmonics and interharmonics. For details, please refer to attached drawing 3: a schematic diagram of the synthesis of power frequency and harmonic signal sources and sub-harmonic and inter-harmonic signal sources.
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