CN105898334B - A kind of DC prediction circuits and its method applied to coding and decoding video - Google Patents

A kind of DC prediction circuits and its method applied to coding and decoding video Download PDF

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CN105898334B
CN105898334B CN201610471667.9A CN201610471667A CN105898334B CN 105898334 B CN105898334 B CN 105898334B CN 201610471667 A CN201610471667 A CN 201610471667A CN 105898334 B CN105898334 B CN 105898334B
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CN105898334A (en
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杜高明
郭晨阳
张阿敏
张多利
宋宇鲲
王春华
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Huangshan Development Investment Group Co.,Ltd.
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Hefei University of Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/46—Embedding additional information in the video signal during the compression process
    • H04N19/463—Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques

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Abstract

A kind of DC prediction circuits and DC Forecasting Methodologies applied to coding and decoding video of the invention；It is characterized in that including adder Multiplexing module, median register module, state self-adaption machine control module；The maximum that adder Multiplexing module obtains resource by being multiplexed adder effectively utilizes；Median register module is computed repeatedly by the way that important median storage is passed to the next cycle as input to reduce；The transmission of state self-adaption machine control module control data and redirecting for calculating cycle；The present invention can reduce circuit work area, reduce the execution cycle of circuit, increase working frequency and improve the accuracy rate of calculating on the basis of DC prediction algorithm functions are realized.

Description

A kind of DC prediction circuits and its method applied to coding and decoding video
Technical field
The invention belongs to the predictive coding field of video coding and decoding technology, specifically a kind of video that is applied to is compiled The DC prediction circuits and its method of decoding.
Background technology
With current scientific and technical continuous development, information technology and computer internet are changing in various degree respectively The daily life of people.Nowadays, people obtain information and are mainly derived from multimedia messages, and multimedia messages are with video For core.During video storage and transmission are constantly widely used, multimedia technology starts to expand research field gradually It is charged in the technology of efficient video coding.People for HD video and the requirement that occupies little space it is more and more stronger, video Encoding and decoding more seem important.DC predictive codings are one of intraframe prediction algorithms, and its popularity uses, and also cause people To the performance requirement more and more higher of its hardware circuit.
In the prior art, the hardware circuit of DC predictive codings has been greatly improved, and Zhou Wei, Huang Xiaodong et al. exist 2013 PCS (Picture Coding Symposium) deliver " EFFICIENT INTRA PREDICTION VLSI Circuit described in ARCHITECTURE FOR HEVC STANDARD ", compared in current DC prediction circuits and DC Forecasting Methodologies Simple and quick circuit；But still suffer from following four problem：
1st, circuit area not enough optimizes, and three-input adder is used for multiple times, and calculating is repeatedly duplicated in calculating process；
2nd, there is the defects of result of calculation is not accurate enough in prediction circuit, and there be the space reduced in the algorithm cycle, and cycle length is drawn The low processing speed of data, so that all having an impact to the speed of whole coding and decoding video；
3rd, the working frequency 357MHz of circuit, has greatly improved relative to circuit before, but still waits to improve to adapt to High-frequency coding rate, if the frequency of DC prediction algorithms is bottleneck, it will drag down the real-time coding speed of whole video sequence；
4th, there is the problem of inaccurate in implementation method, fail to consider in DC prediction algorithms completely, for caused by displacement Decimal place directly abandons problem, and accuracy rate reduces.
The content of the invention
The present invention proposes a kind of DC applied to coding and decoding video to solve above-mentioned the shortcomings of the prior art Prediction circuit and its method, to reduce circuit work area, reduce circuit computing cycle, raising working frequency and calculating Accuracy rate, so as to reduce the cost of coding and decoding video and power consumption.
The present invention is that technical scheme is used by reaching above-mentioned purpose：
A kind of the characteristics of DC prediction circuits applied to coding and decoding video of the present invention, is, for any one in 2 × N cycle interior predictions Pixel value in individual image in 4N × 4N regions, it is a prediction block to remember 4N × 4N regions Then top a line reference pixel reconstructed value of the prediction block PU is designated as A=[R0,-1,R1,-1,…,R4N-1,-1], the prediction block The PU row reference pixel reconstructed value of left one is designated as L=[R-1,0,R-1,1,…,R-1,4N-1]；It is T to remember the cycle, then TmRepresent M-th of cycle；Initialize n=1, m=1；
The DC prediction circuits include：Adder Multiplexing module, median register module, state self-adaption machine control mould Block；
The adder Multiplexing module is in m-th of cycle TmIt is interior to top a line reference pixel reconstructed value A and left One row reference pixel reconstructed value L carries out n-th calculating, obtains 3 accumulated values SUM_0, SUM_4 and SUM_6 of n-th calculating simultaneously Pass to the median register module to be stored, and obtain the first sub-block of the prediction block PU when n-th calculatesAnd directly export；
The state self-adaption machine control module reads 3 that the n-th calculates from the median register module Individual accumulated value SUM_0, SUM_4 and SUM_6 simultaneously pass to the adder Multiplexing module；
The adder Multiplexing module is in the m+1 cycle Tm+1The interior three accumulated value SUM_0 calculated the n-th, SUM_4 and SUM_6 and top a line reference pixel reconstructed value A carries out n-th calculating, obtains described in when n-th calculates Prediction block PU the second sub-block PU "n=[P0,0,P1,0,…,P4n-1,0]；To the n-th calculate three accumulated value SUM_0, SUM_4 and SUM_6 and the row reference pixel reconstructed value L of the left one are calculated, and obtain the prediction when n-th calculates Block PU the 3rd sub-block PU " 'n=[P0,1,P0,2,…,P0,4n-1]；
The first sub-block PU ' when being calculated by the n-thn, the second sub-block PU "nAnd the 3rd sub-block PU " 'nForm n-th Prediction block PU during calculatingn, n+1 is assigned to n, after m+2 is assigned into m, repeats the n-th meter of the adder Multiplexing module Calculate, untill n=N and m=2 × N, so as to obtain prediction block PU.
The characteristics of DC prediction circuits of the present invention applied to coding and decoding video, lies also in, and the adder is multiplexed mould Block includes：No.1 adder, No. two adders, No. three adders, No. four adders, No. five adders, No. six adders, No. seven Adder, No. eight adders, No.1 shift unit, No. two shift units, No. three shift units, No. four shift units, No. five shift units, No. six Shift unit, No. seven shift units, No. eight shift units, No. nine shift units；
The n-th of the adder Multiplexing module is calculated as：
In m-th of cycle TmInterior, the No.1 adder to No. four adders is rebuild to top a line reference pixel The value A and row reference pixel reconstructed value L of left one carries out n-th calculating, obtains four accumulated values SUM_0, SUM_ of n-th calculating 1、SUM_2、SUM_3；
Four accumulated values SUM_0, SUM_1, SUM_2, SUM_3 being calculated by No. eight adders the n-th and Constant " 4 " is calculated, and obtains the accumulated value SUM_7 of n-th calculating；
The No.1 shift unit carries out moving to right 3 bit manipulations to the accumulated value SUM_7 that the n-th calculates, and obtains n-th meter Calculate average value DCvalue；
No. two shift units carry out moving to left 1 bit manipulation to the average value DCvalue that the n-th calculates, and obtain n-th The median DCvalue ' of calculating；
The average value that the median DCvalue ' and n-th that No. six adders are calculated the n-th are calculated DCvalue is calculated, and obtains the accumulated value SUM_5 of n-th calculating；
The accumulated value SUM_5 and constant " 2 " that No. seven adders are calculated the n-th are calculated, and obtain n-th The accumulated value SUM_6 of calculating；
The median DCvalue ' and constant " 2 " that No. five adders are calculated the n-th are calculated, and obtain The accumulated value SUM_4 of n computations；
The first sub-block PU that the average value DCvalue calculated using the n-th calculates as the n-thn' in it is all Element value；
In the m+1 cycle Tm+1Accumulated value SUM_0 and n-th interior, that the No.1 adder is calculated the n-th The SUM_4 of calculating carries out n-th calculating, and obtained result recycles No. three shift units to carry out moving to right 2 bit manipulations, obtains the Second sub-block PU " of n computationsnIn first element value Pn-1,n-1；
No. two adders are to the element value R in top a line reference pixel reconstructed value An,-1Calculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. four shift units to carry out moving to right 2 bit manipulations, obtains n-th The the second sub-block PU " calculatednIn second element value Pn,n-1；
No. three adders are to the element value R in top a line reference pixel reconstructed value An+1,-1Calculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. five shift units to carry out moving to right 2 bit manipulations, obtains second Sub-block PU "nIn the 3rd element value Pn+1,n-1；
No. four adders are to the element value R in top a line reference pixel reconstructed value An+2,-1Calculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. six shift units to carry out moving to right 2 bit manipulations, obtains n-th The the second sub-block PU " calculatednIn the 4th element value Pn+2,n-1；
No. five adders are to the element value R in the row reference pixel reconstructed value L of left one-1,nCalculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. seven shift units to carry out moving to right 2 bit manipulations, obtains n-th The 3rd sub-block PU " ' calculatednIn first element value Pn-1,n；
No. six adders are to the element value R in the row reference pixel reconstructed value L of left one-1,n+1Calculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. eight shift units to carry out moving to right 2 bit manipulations, obtains n-th The 3rd sub-block PU " ' calculatednIn second element value Pn-1,n+1；
No. seven adders are to the element value R in the row reference pixel reconstructed value L of left one-1,n+2Calculated with n-th Accumulated value SUM_6 calculated, obtained result recycles No. nine shift units to carry out moving to right 2 bit manipulations, obtains n-th The 3rd sub-block PU " ' calculatednIn the 3rd element value Pn-1,n+2。
A kind of the characteristics of DC Forecasting Methodologies applied to coding and decoding video of the present invention be for 2 × N cycles interior prediction any one Pixel value in image in 4N × 4N regions, it is a prediction block to remember 4N × 4N regions Then top a line reference pixel reconstructed value of the prediction block PU is designated as A=[R0,-1,R1,-1,…,R4N-1,-1], the prediction block The PU row reference pixel reconstructed value of left one is designated as L=[R-1,0,R-1,1,…,R-1,4N-1]；It is T to remember the cycle, then TmRepresent M-th of cycle；N ∈ (1,2,4,8,16)；1≤n≤N；1≤m≤2×N；
The Forecasting Methodology is to carry out as follows：
Step 1, initialization n=1, m=1；
Step 2, in m-th of cycle TmIt is interior, obtain the accumulated value SUM_0 of n-th calculating using formula (1)：
SUM_0=Rn-1,-1+R-1,n-1 (1)
Step 3, in m-th of cycle TmIt is interior, the average value DCvalue of n-th calculating is obtained using formula (2), and with described The first sub-block that average value DCvalue calculates as the n-thIn all members Element value；
Step 4, in m-th of cycle TmIt is interior, obtain the accumulated value Sum_4 of n-th calculating using formula (3)：
Sum_4=2 × DCvalue+2 (3)
Step 5, in m-th of cycle TmIt is interior, obtain the accumulated value Sum_6 of n-th calculating using formula (4)：
Sum_6=3 × DCvalue+2 (4)
Step 6, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU " of n-th calculating using formula (5)n=[P0,0, P1,0,…,P4n-1,0] in first element value Pn-1,n-1：
Pn-1,n-1=(SUM_0+SUM_4) ÷ 4 (5)
Step 7, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU " of n-th calculating using formula (6)nIn second Individual element value Pn,n-1：
Pn,n-1=(Rn,-1+SUM_6)÷4 (6)
Step 8, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU " of n-th calculating using formula (7)nIn the 3rd Individual element value Pn+1,n-1：
Pn+1,n-1=(Rn+1,-1+SUM_6)÷4 (7)
Step 9, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU " of n-th calculating using formula (8)nIn the 4th Individual element value Pn+2,n-1：
Pn+2,n-1=(Rn+2,-1+SUM_6)÷4 (8)
Step 10, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU " ' of n-th calculating using formula (9)nIn One element value Pn-1,n：
Pn-1,n=(R-1,n+SUM_6)÷4 (9)
Step 11, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU " ' of n-th calculating using formula (10)nIn Second element value Pn-1,n+1：
Pn-1,n+1=(R-1,n+1+SUM_6)÷4 (10)
Step 12, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU " ' of n-th calculating using formula (11)nIn 3rd element value Pn-1,n+2：
Pn-1,n+2=(R-1,n+2+SUM_6)÷4 (11)
So as to obtain the second sub-blocks of prediction block PU PU " when n-th calculatesn=[P0,0,P1,0,…,P4n-1,0] and the Three sub-block PU " 'n=[P0,1,P0,2,…,P0,4n-1]；
Step 13, the first sub-block PU when being calculated by the n-th1', the second sub-block PU "nWith the 3rd sub-block PU " 'nForm Prediction block PU when n-th calculatesn；
Step 14, n+1 is assigned to n, after m+2 is assigned into m, repeat step 2 performs, until n=N and m=2 × N are Only, so as to obtaining prediction block PU.
Compared with prior art, advantageous effects of the invention are embodied in：
1st, the existing DC prediction algorithms circuit design of optimization proposed by the present invention, overcomes that circuit footprint is big, work frequency The problem of rate is not high enough, it is proposed that a kind of hardware implementation mode of DC prediction algorithms applied to coding and decoding video, employ point Cut processing framework, be multiplexed by adder, state self-adaption machine control and median deposit etc. technology, reduce prediction circuit Area, and improve the working frequency of prediction circuit.
2nd, the implementation of the DC prediction algorithms proposed by the present invention applied to coding and decoding video, passes through the multiplexing of adder Module, reduce computing repeatedly for data, logic gate number is reduced to 8762 from 12970, effectively reduce the occupancy face of circuit Product, so as to reduce the design cost of whole circuit.
3rd, the input proposed by the present invention that adder is controlled by state machine, is answered adder so as to reach With, while reduce redundant computation, and median cleverly is deposited using register, in original work period from 3 week Phase drops to 2 cycles, and DC prediction algorithms are one kind of coding and decoding video prediction algorithm, because the speed of DC prediction algorithms circuit work Degree improves 33%, so this will cause the speed of whole coding and decoding video to be obviously improved, and then improves work Frequency, so as to improve the speed of coding and decoding video.
4th, the implementation of the DC prediction algorithms proposed by the present invention applied to coding and decoding video, has simplified circuit structure, So that most fast working frequency reaches 500MHz, compared with circuit before, speed improves 25%, according to the work of circuit frequency Rate, the real-time coding speed of video sequence is lifted to 7680 × 4320@30fps from 4096 × 2160@30fps.
5th, the DC prediction algorithm circuit engineerings after hardware optimization proposed by the present invention, more accurately follow DC prediction algorithms Operation principle.When carrying out the calculating of Dcvalue values, it is contemplated that hardware circuit is in shifting process, it is possible that rounding up Situation, adding N calculating to take into account, effectively overcome and all cast out the error predictions of appearance, the point for having pixel originally Prediction into without pixel.The present invention compare before design, to algorithm realize it is more perfect, more accurate.
Brief description of the drawings
Fig. 1 is DC prediction modules of the present invention；
Fig. 2 is that DC of the present invention predicts hardware structure circuit；
Fig. 3 is the middle-value calculating circuit of DC prediction algorithms of the present invention；
Fig. 4 is the predictor calculation circuit of DC prediction algorithms of the present invention；
Fig. 5 is state machine circuit of the present invention；
Fig. 6 is optimum results experimental data comparison diagram of the present invention.
Embodiment
In the present embodiment, a kind of DC prediction circuits applied to coding and decoding video are used for any one in 2 × N cycle interior predictions Pixel value in individual image in 4N × 4N regions, note 4N × 4N regions are a prediction block Then prediction block PU top a line reference pixel reconstructed value is designated as A=[R0,-1,R1,-1,…,R4N-1,-1], prediction block PU left One row reference pixel reconstructed value is designated as L=[R-1,0,R-1,1,…,R-1,4N-1]；The note cycle is T, then TmRepresent m-th of cycle；
In specific implementation, N=1, then the pixel value in 2 cycle interior prediction any one image in 4 × 4 regions, note 4 × 4 regions are a prediction blockAs shown in figure 1, then prediction block PU top a line reference image Plain reconstructed value is designated as A=[R0,-1,R1,-1,R2,-1,R3-1], the prediction block PU row reference pixel reconstructed value of left one is designated as L= [R-1,0,R-1,1,R-1,2,R-1,3]；TmM-th of cycle is represented, then T1Represent the 1st cycle；Initialize n=1, m=1；
As shown in Fig. 2 DC prediction circuits include：Adder Multiplexing module, median register module, state self-adaption machine Control module；
Adder Multiplexing module is in the 1st cycle T1It is interior that top a line reference pixel reconstructed value A and the row of left one are referred to Pixel reconstructed value L carries out the 1st calculating, in obtaining 3 accumulated values SUM_0, SUM_4 and SUM_6 of the 1st calculating and passing to Between value register module stored, and obtain the first sub-block of the prediction block PU when calculating for the 1st time And directly export；
State self-adaption machine control module reads 3 accumulated value SUM_ of the 1st calculating from middle value register module 0th, SUM_4 and SUM_6 and adder Multiplexing module is passed to；
Adder Multiplexing module is in the 2nd cycle T2Interior three accumulated values SUM_0, SUM_4 and SUM_ to the 1st calculating 6 and top a line reference pixel reconstructed value A carries out the 1st calculating, prediction block PU the second sub-block when obtaining calculating for the 1st time PU″1=[P0,0,P1,0,P2,0,P3,0]；Three accumulated values SUM_0, SUM_4 and SUM_6 and left one of 1st calculating are arranged Reference pixel reconstructed value L is calculated, and obtains the 3rd sub-block PU " ' of the prediction block PU when calculating for the 1st time1=[P0,1,P0,2, P0,3]；
The first sub-block PU when being calculated by the 1st time1', the second sub-block PU "1And the 3rd sub-block PU " '1Form the 1st calculating When prediction block PU1, due to N=1, so n value is 1, i.e., it is once that can obtain predicted value PU only to need to calculate1=PU.
Adder Multiplexing module includes：No.1 adder, No. two adders, No. three adders, No. four adders, No. five plus Musical instruments used in a Buddhist or Taoist mass, No. six adders, No. seven adders, No. eight adders, No.1 shift unit, No. two shift units, No. three shift units, No. four shiftings Position device, No. five shift units, No. six shift units, No. seven shift units, No. eight shift units, No. nine shift units；
The 1st time of adder Multiplexing module is calculated as：
As shown in figure 3, in the 1st cycle T1Interior, No.1 adder to No. four adders is to top a line reference pixel weight The built-in value A and row reference pixel reconstructed value L of left one carry out the 1st time calculating, obtain the 1st time calculating four accumulated value SUM_0, SUM_1、SUM_2、SUM_3；
Four accumulated values SUM_0, SUM_1, SUM_2, SUM_3 and constant " 4 " of the 1st calculating are entered by No. eight adders Row calculates, and obtains the accumulated value SUM_7 of the 1st calculating；
No.1 shift unit carries out moving to right 3 bit manipulations to the accumulated value SUM_7 of the 1st calculating, obtains the 1st calculating average value DCvalue；
No. two shift units carry out moving to left 1 bit manipulation to the average value DCvalue of the 1st calculating, obtain the 1st time in calculating Between value DCvalue '；
No. six adders are counted to the average value DCvalue of median DCvalue ' and the 1st calculating of the 1st calculating Calculate, obtain the accumulated value SUM_5 of the 1st calculating；
No. seven adders are calculated the accumulated value SUM_5 and constant " 2 " of the 1st calculating, obtain the tired of the 1st calculating Value added SUM_6；
No. five adders are calculated the median DCvalue ' and constant " 2 " of the 1st calculating, obtain the 1st calculating Accumulated value SUM_4；
The first sub-block PU using the average value DCvalue of the 1st calculating as the 1st calculating1' in all elements value；
In the 2nd cycle T2It is interior, reuse eight adders of adder Module, the 1st cycle T1The centre of interior calculating Value deposit is used as the 2nd cycle T into distributor module using it2Interior input；
As shown in figure 4, No.1 adder is counted to the SUM_4 of accumulated value SUM_0 and the 1st calculating of the 1st calculating Calculate, obtained result recycles No. three shift units to carry out moving to right 2 bit manipulations, obtains the second sub-block PU " of the 1st calculating1In First element value P0,0；
No. two adders are to the element value R in a line reference pixel reconstructed value A of top1,-1With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. four shift units to carry out moving to right 2 bit manipulations, obtains the second son of the 1st calculating Block PU "1In second element value P1,0；
No. three adders are to the element value R in a line reference pixel reconstructed value A of top2,-1With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. five shift units to carry out moving to right 2 bit manipulations, obtains the second sub-block PU "1In 3rd element value P2,0；
No. four adders are to the element value R in a line reference pixel reconstructed value A of top3,-1With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. six shift units to carry out moving to right 2 bit manipulations, obtains the second son of the 1st calculating Block PU "1In the 4th element value P3,0；
No. five adders are to the element value R in the row reference pixel reconstructed value L of left one-1,1With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. seven shift units to carry out moving to right 2 bit manipulations, obtains the 3rd son of the 1st calculating Block PU " '1In first element value P0,1；
No. six adders are to the element value R in the row reference pixel reconstructed value L of left one-1,2With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. eight shift units to carry out moving to right 2 bit manipulations, obtains the 3rd son of the 1st calculating Block PU " '1In second element value P0,2；
No. seven adders are to the element value R in the row reference pixel reconstructed value L of left one-1,3With the accumulated value of the 1st calculating SUM_6 is calculated, and obtained result recycles No. nine shift units to carry out moving to right 2 bit manipulations, obtains the 3rd son of the 1st calculating Block PU " '1In the 3rd element value P0,3；
As shown in figure 5, state self-adaption machine control module includes two states：Calculate intermediate value state M_value and pre- Pixel state of value P_value is surveyed, two states are unconditionally to redirect automatically.
In this example, as shown in table 1, reference pixel value is by the row reference pixel reconstructed value of top one and the row reference image of left one Plain reconstructed value is formed；
The reference pixel value of table 1
Top reference position R0,-1 R1,-1 R2,-1 R3,-1
Pixel value 10 10 10 11
Left reference position R-1,0 R-1,1 R-1,2 R-1,3
Pixel value 10 10 10 11
In the present embodiment, a kind of DC Forecasting Methodologies applied to coding and decoding video are to carry out as follows：
Step 1, initialization n=1, m=1；
Step 2, in the 1st cycle T1It is interior, obtain the accumulated value SUM_0 of the 1st calculating using formula (1)：
SUM_0=R0,-1+R-1,0=20 (1)
Step 3, in the 1st cycle T1It is interior, the average value DCvalue of the 1st calculating is obtained using formula (2), and with average First sub-blocks of the value DCvalue as the 1st calculatingIn all elements value；
Step 4, in the 1st cycle T1It is interior, obtain the accumulated value Sum_4 of the 1st calculating using formula (3)：
Sum_4=2 × DCvalue+2=22 (3)
Step 5, in the 1st cycle T1It is interior, obtain the accumulated value Sum_6 of the 1st calculating using formula (4)：
Sum_6=3 × DCvalue+2=32 (4)
Step 6, in the 2nd cycle T2It is interior, obtain the second sub-block PU " of the 1st calculating using formula (5)1=[P0,0,P1,0, P2,0,P3,0] in first element value P0,0：
P0,0=(SUM_0+SUM_4) ÷ 4=10 (5)
Step 7, in the 2nd cycle T2It is interior, obtain the second sub-block PU " of the 1st calculating using formula (6)1In second member Plain value P1,0：
P1,0=(R1,-1+ SUM_6) ÷ 4=10 (6)
Step 8, in the 2nd cycle T2It is interior, obtain the second sub-block PU " of the 1st calculating using formula (7)1In the 3rd member Plain value P2,0：
P2,0=(R2,-1+ SUM_6) ÷ 4=10 (7)
Step 9, in the 2nd cycle T2It is interior, obtain the second sub-block PU " of the 1st calculating using formula (8)1In the 4th member Plain value P3,0：
P3,0=(R3,-1+ SUM_6) ÷ 4=10 (8)
Step 10, in the 2nd cycle T2It is interior, obtain the 3rd sub-block PU " ' of the 1st calculating using formula (9)1In first Element value P0,1：
P0,1=(R-1,1+ SUM_6) ÷ 4=10 (9)
Step 11, in the 2nd cycle T2It is interior, obtain the 3rd sub-block PU " ' of the 1st calculating using formula (10)1In second Individual element value P0,2：
P0,2=(R-1,2+ SUM_6) ÷ 4=10 (10)
Step 12, in the 2nd cycle T2It is interior, obtain the 3rd sub-block PU " ' of the 1st calculating using formula (11)1In the 3rd Individual element value P0,3：
P0,3=(R-1,3+ SUM_6) ÷ 4=10 (11)
So as to obtain prediction block the second sub-blocks of PU PU " when calculating for the 1st time1=[P0,0,P1,0,P2,0,P3,0] and the 3rd son Block PU " '1=[P0,1,P0,2,P0,3]；
Step 13, the second sub-block PU " by the 1st calculating1With the 3rd sub-block PU " '1Form prediction block when calculating the 1st time PU1；
Step 14, by 1≤n≤N；1≤m≤2 × N, which knows, only to be needed to calculate once, so as to obtain prediction block PU value Such as table 2；
The predicted pixel values of table 2
Predicted position P0,0 P1,0 P2,0 P3,0
Pixel value 10 10 10 10
Predicted position P0,1 P1,1 P2,1 P3,1
Pixel value 10 10 10 10
Predicted position P0,2 P1,2 P2,2 P3,2
Pixel value 10 10 10 10
Predicted position P0,3 P1,3 P2,3 P3,3
Pixel value 10 10 10 10
VLSI designs are carried out to DC prediction algorithms for 4 × 4 prediction block, and are retouched using Verilog HDL language State, emulated and integrated by Synopsys softwares, the comprehensive circuit that obtains most works frequently soon under SMIC 0.18um techniques Rate is 500MHz, and the area of circuit work is 8762gate, and the algorithm cycle is reduced to 2 cycles.The present invention and Zhou Wei, Huang Xiaodong Et al. deliver " EFFICIENT INTRA PREDICTION VLSI in 2013PCS (Picture Coding Symposium) Circuit is compared described in ARCHITECTURE FOR HEVC STANDARD ", and working frequency improves 40%, and gate number reduces 40%, the algorithm cycle reduces 33%, working frequency, logic gate number, the comparison diagram in algorithm cycle respectively shown in Fig. 6, if Expand on the platform of whole coding and decoding video, effect of optimization becomes apparent from.

Claims (3)

1. a kind of DC prediction circuits applied to coding and decoding video, it is characterized in that, in any one figure of 2 × N cycles interior prediction Pixel value as in 4N × 4N regions, it is a prediction block to remember 4N × 4N regions Then top a line reference pixel reconstructed value of the prediction block PU is designated as A=[R0,-1,R1,-1,…,R4N-1,-1], the prediction block The PU row reference pixel reconstructed value of left one is designated as L=[R-1,0,R-1,1,…,R-1,4N-1]；It is T to remember the cycle, then TmRepresent M-th of cycle；Initialize n=1, m=1；
The DC prediction circuits include：Adder Multiplexing module, median register module, state self-adaption machine control module；
The adder Multiplexing module is in m-th of cycle TmIt is interior that top a line reference pixel reconstructed value A and the row of left one are joined Examine pixel reconstructed value L and carry out n-th calculating, obtain 3 accumulated values SUM_0, SUM_4 and SUM_6 of n-th calculating and pass to The median register module is stored, and obtains the first sub-block of the prediction block PU when n-th calculatesAnd directly export；
The state self-adaption machine control module reads 3 that the n-th calculates from the median register module and tired out Value added SUM_0, SUM_4 and SUM_6 simultaneously pass to the adder Multiplexing module；
The adder Multiplexing module is in the m+1 cycle Tm+1Interior three accumulated values SUM_0, SUM_ calculated the n-th 4 and SUM_6 and top a line reference pixel reconstructed value A carries out n-th calculating, obtains prediction when n-th calculates Block PU the second sub-block PUn"=[P0,0,P1,0,…,P4n-1,0]；Three accumulated values SUM_0, the SUM_4 calculated the n-th Calculated with SUM_6 and the row reference pixel reconstructed value L of the left one, obtain the prediction block PU when n-th calculates The 3rd sub-block PUn" '=[P0,1,P0,2,…,P0,4n-1]；
The first sub-block PU when being calculated by the n-thn', the second sub-block PUn" and the 3rd sub-block PUn" ' form n-th calculates When prediction block PUn, n+1 is assigned to n, after m+2 is assigned into m, the n-th for repeating the adder Multiplexing module calculates, directly Untill n=N and m=2 × N, so as to obtain prediction block PU.
2. the DC prediction circuits according to claim 1 applied to coding and decoding video, it is characterized in that, the adder multiplexing Module includes：No.1 adder, No. two adders, No. three adders, No. four adders, No. five adders, No. six adders, seven Number adder, No. eight adders, No.1 shift unit, No. two shift units, No. three shift units, No. four shift units, No. five shift units, six Number shift unit, No. seven shift units, No. eight shift units, No. nine shift units；
The n-th of the adder Multiplexing module is calculated as：
In m-th of cycle TmIt is interior, the No.1 adder to No. four adders to top a line reference pixel reconstructed value A and The row reference pixel reconstructed value L of left one carry out n-th calculating, obtain n-th calculating four accumulated value SUM_0, SUM_1, SUM_2、SUM_3；
Four accumulated values SUM_0, SUM_1, SUM_2, the SUM_3 and constant calculated by No. eight adders the n-th " 4 " are calculated, and obtain the accumulated value SUM_7 of n-th calculating；
The No.1 shift unit carries out moving to right 3 bit manipulations to the accumulated value SUM_7 that the n-th calculates, and it is flat to obtain n-th calculating Average DCvalue；
No. two shift units carry out moving to left 1 bit manipulation to the average value DCvalue that the n-th calculates, and obtain n-th calculating Median DCvalue '；
The average value DCvalue that the median DCvalue ' and n-th that No. six adders are calculated the n-th are calculated enters Row calculates, and obtains the accumulated value SUM_5 of n-th calculating；
The accumulated value SUM_5 and constant " 2 " that No. seven adders are calculated the n-th are calculated, and obtain n-th calculating Accumulated value SUM_6；
The median DCvalue ' and constant " 2 " that No. five adders are calculated the n-th are calculated, and obtain n-th The accumulated value SUM_4 of calculating；
The first sub-block PU that the average value DCvalue calculated using the n-th calculates as the n-thn' in all elements Value；
In the m+1 cycle Tm+1Interior, the accumulated value SUM_0 and n-th that the No.1 adder is calculated the n-th are calculated SUM_4 carry out n-th calculating, obtained result recycles No. three shift units to carry out moving to right 2 bit manipulations, obtains n-th The the second sub-block PU calculatedn" in first element value Pn-1,n-1；
No. two adders are to the element value R in top a line reference pixel reconstructed value An,-1Calculated with n-th cumulative Value SUM_6 is calculated, and obtained result recycles No. four shift units to carry out moving to right 2 bit manipulations, obtains n-th calculating Second sub-block PUn" in second element value Pn,n-1；
No. three adders are to the element value R in top a line reference pixel reconstructed value An+1,-1Calculated with n-th tired Value added SUM_6 is calculated, and obtained result recycles No. five shift units to carry out moving to right 2 bit manipulations, obtains the second sub-block PUn" in the 3rd element value Pn+1,n-1；
No. four adders are to the element value R in top a line reference pixel reconstructed value An+2,-1Calculated with n-th tired Value added SUM_6 is calculated, and obtained result recycles No. six shift units to carry out moving to right 2 bit manipulations, obtains n-th calculating The second sub-block PUn" in the 4th element value Pn+2,n-1；
No. five adders are to the element value R in the row reference pixel reconstructed value L of left one-1,nCalculated with n-th cumulative Value SUM_6 is calculated, and obtained result recycles No. seven shift units to carry out moving to right 2 bit manipulations, obtains n-th calculating 3rd sub-block PUn" ' in first element value Pn-1,n；
No. six adders are to the element value R in the row reference pixel reconstructed value L of left one-1,n+1Calculated with n-th tired Value added SUM_6 is calculated, and obtained result recycles No. eight shift units to carry out moving to right 2 bit manipulations, obtains n-th calculating The 3rd sub-block PUn" ' in second element value Pn-1,n+1；
No. seven adders are to the element value R in the row reference pixel reconstructed value L of left one-1,n+2Calculated with n-th tired Value added SUM_6 is calculated, and obtained result recycles No. nine shift units to carry out moving to right 2 bit manipulations, obtains n-th calculating The 3rd sub-block PUn" ' in the 3rd element value Pn-1,n+2。
A kind of 3. DC Forecasting Methodologies applied to coding and decoding video, it is characterized in that in any one figure of 2 × N cycles interior prediction Pixel value as in 4N × 4N regions, it is a prediction block to remember 4N × 4N regions Then top a line reference pixel reconstructed value of the prediction block PU is designated as A=[R0,-1,R1,-1,…,R4N-1,-1], the prediction block The PU row reference pixel reconstructed value of left one is designated as L=[R-1,0,R-1,1,…,R-1,4N-1]；It is T to remember the cycle, then TmRepresent M-th of cycle；N ∈ (1,2,4,8,16)；1≤n≤N；1≤m≤2×N；
The Forecasting Methodology is to carry out as follows：
Step 1, initialization n=1, m=1；
Step 2, in m-th of cycle TmIt is interior, obtain the accumulated value SUM_0 of n-th calculating using formula (1)：
SUM_0=Rn-1,-1+R-1,n-1 (1)
Step 3, in m-th of cycle TmIt is interior, the average value DCvalue of n-th calculating is obtained using formula (2), and with the average value The first sub-block that DCvalue calculates as the n-thIn all elements value；
<mrow> <mi>D</mi> <mi>C</mi> <mi>v</mi> <mi>a</mi> <mi>l</mi> <mi>u</mi> <mi>e</mi> <mo>=</mo> <mrow> <mo>(</mo> <munderover> <mo>&amp;Sigma;</mo> <mrow> <mi>x</mi> <mo>=</mo> <mn>4</mn> <mi>n</mi> <mo>-</mo> <mn>4</mn> </mrow> <mrow> <mn>4</mn> <mi>n</mi> <mo>-</mo> <mn>1</mn> </mrow> </munderover> <msub> <mi>R</mi> <mrow> <mi>x</mi> <mo>,</mo> <mo>-</mo> <mn>1</mn> </mrow> </msub> <mo>+</mo> <munderover> <mo>&amp;Sigma;</mo> <mrow> <mi>y</mi> <mo>=</mo> <mn>4</mn> <mi>n</mi> <mo>-</mo> <mn>4</mn> </mrow> <mrow> <mn>4</mn> <mi>n</mi> <mo>-</mo> <mn>1</mn> </mrow> </munderover> <msub> <mi>R</mi> <mrow> <mo>-</mo> <mn>1</mn> <mo>,</mo> <mi>y</mi> </mrow> </msub> <mo>+</mo> <mn>4</mn> <mi>N</mi> <mo>)</mo> </mrow> <mo>&gt;</mo> <mo>&gt;</mo> <mrow> <mo>(</mo> <msubsup> <mi>log</mi> <mn>2</mn> <mrow> <mn>4</mn> <mi>N</mi> </mrow> </msubsup> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow>
Step 4, in m-th of cycle TmIt is interior, obtain the accumulated value Sum_4 of n-th calculating using formula (3)：
Sum_4=2 × DCvalue+2 (3)
Step 5, in m-th of cycle TmIt is interior, obtain the accumulated value Sum_6 of n-th calculating using formula (4)：
Sum_6=3 × DCvalue+2 (4)
Step 6, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU of n-th calculating using formula (5)n"=[P0,0, P1,0,…,P4n-1,0] in first element value Pn-1,n-1：
Pn-1,n-1=(SUM_0+SUM_4) ÷ 4 (5)
Step 7, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU of n-th calculating using formula (6)n" in second member Plain value Pn,n-1：
Pn,n-1=(Rn,-1+SUM_6)÷4 (6)
Step 8, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU of n-th calculating using formula (7)n" in the 3rd member Plain value Pn+1,n-1：
Pn+1,n-1=(Rn+1,-1+SUM_6)÷4 (7)
Step 9, in the m+1 cycle Tm+1It is interior, obtain the second sub-block PU of n-th calculating using formula (8)n" in the 4th member Plain value Pn+2,n-1：
Pn+2,n-1=(Rn+2,-1+SUM_6)÷4 (8)
Step 10, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU of n-th calculating using formula (9)n" ' in first Element value Pn-1,n：
Pn-1,n=(R-1,n+SUM_6)÷4 (9)
Step 11, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU of n-th calculating using formula (10)n" ' in second Element value Pn-1,n+1：
Pn-1,n+1=(R-1,n+1+SUM_6)÷4 (10)
Step 12, in the m+1 cycle Tm+1It is interior, obtain the 3rd sub-block PU of n-th calculating using formula (11)n" ' in the 3rd Element value Pn-1,n+2：
Pn-1,n+2=(R-1,n+2+SUM_6)÷4 (11)
So as to obtain the second sub-blocks of prediction block PU PU when n-th calculatesn"=[P0,0,P1,0,…,P4n-1,0] and the 3rd son Block PUn" '=[P0,1,P0,2,…,P0,4n-1]；
Step 13, the first sub-block PU when being calculated by the n-th1', the second sub-block PUn" and the 3rd sub-block PUn" ' form n-th Prediction block PU during secondary calculatingn；
Step 14, n+1 being assigned to n, after m+2 is assigned into m, repeat step 2 performs, untill n=N and m=2 × N, from And obtain prediction block PU.
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