CN105897111A - Digital frequency dividing and phase shifting circuit for driving control of three-phase synchronous motor - Google Patents
Digital frequency dividing and phase shifting circuit for driving control of three-phase synchronous motor Download PDFInfo
- Publication number
- CN105897111A CN105897111A CN201610409488.2A CN201610409488A CN105897111A CN 105897111 A CN105897111 A CN 105897111A CN 201610409488 A CN201610409488 A CN 201610409488A CN 105897111 A CN105897111 A CN 105897111A
- Authority
- CN
- China
- Prior art keywords
- frequency dividing
- input
- outfan
- circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
- H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
- H02P25/022—Synchronous motors
- H02P25/024—Synchronous motors controlled by supply frequency
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/004—Counters counting in a non-natural counting order, e.g. random counters
Abstract
The invention relates to a digital frequency dividing and phase shifting circuit for driving control of a three-phase synchronous motor. The digital frequency dividing and phase shifting circuit comprises a 2-4 frequency dividing circuit, a pseudo 4/3 frequency dividing circuit, a 64 frequency dividing circuit and a frequency dividing and phase shifting circuit, wherein an input end of the 2-4 frequency dividing circuit is connected with a square wave input signal and an output end is connected with the input end of the pseudo 4/3 frequency dividing circuit; the output end of the pseudo 4/3 frequency dividing circuit is connected with the input end of the frequency dividing and phase shifting circuit through the 64 frequency dividing circuit; and the output end of the frequency dividing and phase shifting circuit is externally connected with a drive circuit. Through combined frequency dividing design of the 2-4 frequency dividing circuit, the pseudo 4/3 frequency dividing circuit and the 64 frequency dividing circuit, the signal frequency is divided into six times of the final output signal frequency; the phase difference accuracy is improved; the phase difference of the circuit product is 120+/-0.3 degrees; reliable operation of the circuit is ensured; and the output frequency is stabilized at 1kHz.
Description
Technical field
The present invention relates to three-phase synchronous motor and drive control field, be specifically related to a kind of digital frequency division phase-shift circuit driving for three-phase synchronous motor and controlling.
Background technology
Three-phase synchronous motor is widely used in the military-civil electronic systems such as space flight, aviation, boats and ships, weapons, electronics, medical treatment, industry, and corresponding motor driving controling circuit have also been obtained extensively application.Along with the high speed development of electronic technology, most of three-phase synchronous motor driving control systems are higher to frequency and the phase contrast required precision of three-phase circuit control signal.Improving of frequency accuracy requires that the precision of frequency dividing improves accordingly, and the raising of phase contrast precision then requires that the precision of phase shift improves accordingly.But currently used three-phase synchronous motor drive circuit mostly uses FPGA or dsp chip combining to realize with software on hardware, this three-phase synchronous motor driving control system is due to reasons such as hardware production technologies, the frequency and the phase contrast required precision that make control signal are poor, are gradually replaced by digital frequency division phase-shift circuit control system.
Summary of the invention
It is an object of the invention to provide a kind of digital frequency division phase-shift circuit driving for three-phase synchronous motor and controlling, this circuit can not only ensure the precision of phase shift, and ensure that the reliability service of circuit.
For achieving the above object, present invention employs techniques below scheme: a kind of drive the digital frequency division phase-shift circuit controlled for three-phase synchronous motor, including 2-4 frequency dividing circuit, pseudo-4/3 frequency dividing circuit, 64 frequency dividing circuits and frequency dividing phase-shift circuit, the input of described 2-4 frequency dividing circuit is connected with square-wave input signal, its outfan is connected with the input of pseudo-4/3 frequency dividing circuit, the outfan of described pseudo-4/3 frequency dividing circuit is connected through the input of 64 frequency dividing circuits with frequency dividing phase-shift circuit, the outfan external drive circuit of frequency dividing phase-shift circuit.
nullDescribed pseudo-4/3 frequency dividing circuit includes three input nand gate D1、D5、D10，Not gate D2、D3、D4、D6、D9，With door D7、D8，Resistance R1、R2，Electric capacity C1、C2，The two of which input of described NAND gate D1 outfan with 2-4 frequency dividing circuit respectively is connected，The outfan of its another input NAND gate D2 is connected，The input of not gate D2 is through the external square-wave input signal of resistance R1，The input of one end NAND gate D2 of described electric capacity C1 is connected，Its other end ground connection，The one external square-wave input signal of input of described NAND gate D5，Its other two inputs NAND gate D3 respectively、The outfan of not gate D4 is connected，The input of not gate D3 and not gate D4 is connected with the outfan of 2-4 frequency dividing circuit，The outfan of described wherein input NAND gate D6 with door D7 is connected，It is connected with the outfan of 2-4 frequency dividing circuit with another input of door D7 and the input of not gate D6，It is connected with the input with door D8 with the outfan of door D7，The external square-wave input signal of another input with door D8，It is connected through the input of resistance R2 NAND gate D9 with the outfan of door D8，Described NAND gate D1、NAND gate D5 is connected with the input of NAND gate D10 with the outfan of not gate D9，The outfan of NAND gate D10 and the input of 64 frequency dividing circuits are connected.
nullDescribed frequency dividing phase-shift circuit is by XOR gate D13、D14、D15，With door D12，Not gate D11 and shift register D16 composition，The described input with door D12 outfan with XOR gate D13 and XOR gate D14 respectively is connected，The input of its output NAND gate D11 is connected，The outfan of not gate D11 is connected with an input of XOR gate D15，Another input of XOR gate D15 and an input of XOR gate D13 are all connected with the outfan Q2 of shift register D16，The another input of XOR gate D13 and an input of XOR gate D14 are all connected with the outfan Q1 of shift register D16，Another input of XOR gate D14 is connected with the outfan Q0 of shift register D16，The outfan of XOR gate D15 is connected with the input of shift register D16，The outfan Q0 of described shift register D16、Q1 and Q2 is the outfan of frequency dividing phase-shift circuit.
Described 2-4 frequency dividing circuit, 64 frequency dividing circuits all use seven grades of binary counters.
As shown from the above technical solution, three-phase synchronous motor of the present invention drives the digital frequency division phase-shift circuit controlled, by 2-4 frequency dividing circuit, pseudo-4/3 frequency dividing and the combination frequency dividing design of 64 frequency dividings, signal frequency is divided into 6 times of final output signal frequency, prepare for frequency dividing phase shift below and on this basis, early stage frequency dividing is got the signal period the least, to improve phase contrast precision.After using this circuit, circuit product phase contrast 120 ° ± 0.3 °, phase shift feedback uses error correction circuit, i.e. logic judging circuit, it is ensured that the reliability service of circuit, makes output frequency stabilize to 1kHz.
Accompanying drawing explanation
Fig. 1 is the circuit block diagram of the present invention；
Fig. 2 is the circuit diagram of pseudo-4/3 frequency dividing circuit of the present invention；
Fig. 3 is the circuit diagram that the present invention divides phase-shift circuit；
Fig. 4 is the circuit state transfer figure of shift register output end Q0, Q1, Q2 of the present invention.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings:
As shown in Figure 1, the digital frequency division phase-shift circuit driving control for three-phase synchronous motor of the present embodiment, including 2-4 frequency dividing circuit 1, pseudo-4/3 frequency dividing circuit 2,64 frequency dividing circuit 3 and frequency dividing phase-shift circuit 4, the input of 2-4 frequency dividing circuit 1 is connected with square-wave input signal, its outfan is connected with the input of pseudo-4/3 frequency dividing circuit 2, the outfan of pseudo-4/3 frequency dividing circuit 2 is connected through the input of 64 frequency dividing circuits 3 with frequency dividing phase-shift circuit 4, the outfan external drive circuit of frequency dividing phase-shift circuit 4.In the present embodiment, square-wave signal is 512kHz, this square-wave signal make after 2-4 frequency dividing circuit 1, pseudo-4/3 frequency dividing circuit 2,64 frequency dividing circuit 3 and frequency dividing phase-shift circuit 4 output A, B, C tri-the output frequency of end stabilize to 1kHz, it is ensured that the reliability service of circuit.
nullAs shown in Figure 2，Pseudo-4/3 frequency dividing circuit 2 includes three input nand gate D1、D5、D10，Not gate D2、D3、D4、D6、D9，With door D7、D8，Resistance R1、R2，Electric capacity C1、C2，The two of which input of NAND gate D1 outfan with 2-4 frequency dividing circuit 1 respectively is connected，The outfan of its another input NAND gate D2 is connected，The input of not gate D2 is through resistance R1 external 512kHz square-wave input signal，The input of one end NAND gate D2 of electric capacity C1 is connected，Its other end ground connection，The one external square-wave input signal of input of NAND gate D5，Its other two inputs NAND gate D3 respectively、The outfan of not gate D4 is connected，The input of not gate D3 and not gate D4 is connected with the outfan of 2-4 frequency dividing circuit 1，It is connected with the outfan of wherein input NAND gate D6 of door D7，It is connected with the outfan of 2-4 frequency dividing circuit 1 with another input of door D7 and the input of not gate D6，It is connected with the input with door D8 with the outfan of door D7，Another input external 512kHz square-wave input signal with door D8，It is connected through the input of resistance R2 NAND gate D9 with the outfan of door D8，NAND gate D1、NAND gate D5 is connected with the input of NAND gate D10 with the outfan of not gate D9，The outfan of NAND gate D10 and the input of 64 frequency dividing circuits 3 are connected.
nullAs shown in Figure 3，Frequency dividing phase-shift circuit 4 is by XOR gate D13、D14、D15，With door D12，Not gate D11 and shift register D16 composition，Outfan with XOR gate D13 and XOR gate D14 is connected respectively with the input of door D12，The input of its output NAND gate D11 is connected，The outfan of not gate D11 is connected with an input of XOR gate D15，Another input of XOR gate D15 and an input of XOR gate D13 are all connected with the outfan Q2 of shift register D16，The another input of XOR gate D13 and an input of XOR gate D14 are all connected with the outfan Q1 of shift register D16，Another input of XOR gate D14 is connected with the outfan Q0 of shift register D16，The outfan of XOR gate D15 is connected with the input of shift register D16，The outfan Q0 of shift register D16、Q1 and Q2 is the outfan of frequency dividing phase-shift circuit 4.
In the present embodiment, 2-4 frequency dividing circuit 1,64 frequency dividing circuit 3 all uses seven grades of binary counters.
The operation principle of the present invention:
First, the square-wave signal of 512kHz through frequency divider carry out 2 frequency dividings and 4 frequency dividing, obtain 256 kHz and 128kHz square-wave signals, the signal of two kinds of frequencies of 256kHz, 128kHz together with 512kHz square-wave signal by carrying out logical process as shown in Figure 2.Then it is by 4/3 frequency dividing by umber of pulse calculating and obtains the square-wave signal of pseudo-384kHz.Be a clock T with the cycle (1.953125us) of 512kHz, then 3 square wave interval times are 1.1T, 1.5T, 1.4T.
Secondly, this pseudo-actual 128kHz of 384kHz() square-wave signal carry out 64 frequency dividings by frequency divider again, obtained the actual 2kHz of pseudo-6kHz() square-wave signal, the most continuous three square waves are different for interval time, it is respectively 166.22us, 166.99us, 166.78us, be a clock T with the cycle (1.953125us) of 512kHz, then three square waves are respectively 85.1T, 85.5T, 85.4T interval time.
Again, using the square-wave signal of pseudo-6kHz as the clock trigger signal of shift register D16, as it is shown on figure 3, take Q0
nullQ2 Q4 is the control signal of three tunnel outputs，6 are triggered clock is 1 cycle，Then the cycle time of its output control signal is 85.1T+85.5T+85.4T+85.1T+85.5T+85.4T=512T，Frequency is 512kHz/512=1kHz,The time difference of three control signals is respectively 85.1T+85.5T=170.6T，85.4T+85.1T=170.5T，85.5T+85.4T=170.9T，Its phase contrast is respectively 170.6T/512T × 360 °=119.953 °, 170.5T/512T×360°=119.882°, 170.9T/512T×360°=120.164°,Phase contrast meets the index request of 120 ° ± 0.6 °.
Finally, frequency dividing phase-shift circuit 4 contains error correction circuit, i.e. logic judging circuit, as it is shown on figure 3, outfan Q0 Q1 Q2, Q3 Q4 that feedback signal is shift register D16 are come by Q2 displacement, so the ruuning situation of frequency dividing phase-shift circuit 4 Main Analysis Q0 Q1 Q2
Q0 Q1 Q2 has 6 kinds of states 000,100,110,111,011,001, and carries out loop cycle by these 6 kinds of states.Having 8 kinds of states according to these 3 state points of permutation and combination, also 010,101 two states do not appear in loop cycle.During circuit product uses, particularly start power up just, or it is possible that 010,101 two states when interference occurs, when the outfan Q0 Q1 Q2 of shift register D16 circulates in 6 kinds of states 000,100,110,111,011,001, D takes the rp state value of Q2, and when Q0 Q1 Q2 appearance 010,101 two states, D takes the original state state value of Q2.When starting to occur 010,101 two states time, state is pulled back to normal cycle period, and the state transition diagram of the outfan Q0 Q1 Q2 of shift register D16 is as shown in Figure 4.
Embodiment described above is only to be described the preferred embodiment of the present invention; not the scope of the present invention is defined; on the premise of designing spirit without departing from the present invention; various deformation that technical scheme is made by those of ordinary skill in the art and improvement, all should fall in the protection domain that claims of the present invention determines.
Claims (4)
1. one kind drives the digital frequency division phase-shift circuit controlled for three-phase synchronous motor, it is characterized in that: include 2-4 frequency dividing circuit, pseudo-4/3 frequency dividing circuit, 64 frequency dividing circuits and frequency dividing phase-shift circuit, the input of described 2-4 frequency dividing circuit is connected with square-wave input signal, its outfan is connected with the input of pseudo-4/3 frequency dividing circuit, the outfan of described pseudo-4/3 frequency dividing circuit is connected through the input of 64 frequency dividing circuits with frequency dividing phase-shift circuit, the outfan external drive circuit of frequency dividing phase-shift circuit.
nullThe digital frequency division phase-shift circuit driving control for three-phase synchronous motor the most according to claim 1，It is characterized in that: described pseudo-4/3 frequency dividing circuit includes three input nand gate D1、D5、D10，Not gate D2、D3、D4、D6、D9，With door D7、D8，Resistance R1、R2,Electric capacity C1、C2，The two of which input of described NAND gate D1 outfan with 2-4 frequency dividing circuit respectively is connected，The outfan of its another input NAND gate D2 is connected，The input of not gate D2 is through the external square-wave input signal of resistance R1，The input of one end NAND gate D2 of described electric capacity C1 is connected，Its other end ground connection，The one external square-wave input signal of input of described NAND gate D5，Its other two inputs NAND gate D3 respectively、The outfan of not gate D4 is connected，The input of not gate D3 and not gate D4 is connected with the outfan of 2-4 frequency dividing circuit，The outfan of described wherein input NAND gate D6 with door D7 is connected，It is connected with the outfan of 2-4 frequency dividing circuit with another input of door D7 and the input of not gate D6，It is connected with the input with door D8 with the outfan of door D7，The external square-wave input signal of another input with door D8，It is connected through the input of resistance R2 NAND gate D9 with the outfan of door D8，Described NAND gate D1、NAND gate D5 is connected with the input of NAND gate D10 with the outfan of not gate D9，The outfan of NAND gate D10 and the input of 64 frequency dividing circuits are connected.
nullThe digital frequency division phase-shift circuit driving control for three-phase synchronous motor the most according to claim 1，It is characterized in that: described frequency dividing phase-shift circuit is by XOR gate D13、D14、D15，With door D12，Not gate D11 and shift register D16 composition，The described input with door D12 outfan with XOR gate D13 and XOR gate D14 respectively is connected，The input of its output NAND gate D11 is connected，The outfan of not gate D11 is connected with an input of XOR gate D15，Another input of XOR gate D15 and an input of XOR gate D13 are all connected with the outfan Q2 of shift register D16，The another input of XOR gate D13 and an input of XOR gate D14 are all connected with the outfan Q1 of shift register D16，Another input of XOR gate D14 is connected with the outfan Q0 of shift register D16，The outfan of XOR gate D15 is connected with the input of shift register D16，The outfan Q0 of described shift register D16、Q1 and Q2 is the outfan of frequency dividing phase-shift circuit.
The digital frequency division phase-shift circuit driving control for three-phase synchronous motor the most according to claim 1, it is characterised in that: described 2-4 frequency dividing circuit, 64 frequency dividing circuits all use seven grades of binary counters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610409488.2A CN105897111B (en) | 2016-06-03 | 2016-06-03 | A kind of digital frequency division phase-shift circuit for three-phase synchronous motor drive control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610409488.2A CN105897111B (en) | 2016-06-03 | 2016-06-03 | A kind of digital frequency division phase-shift circuit for three-phase synchronous motor drive control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105897111A true CN105897111A (en) | 2016-08-24 |
| CN105897111B CN105897111B (en) | 2018-08-28 |
Family
ID=56729217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610409488.2A Active CN105897111B (en) | 2016-06-03 | 2016-06-03 | A kind of digital frequency division phase-shift circuit for three-phase synchronous motor drive control |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105897111B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158205A (en) * | 2011-03-14 | 2011-08-17 | 北京龙芯中科技术服务中心有限公司 | Clock frequency multiplier, device and clock frequency multiplication method |
| JP2013110859A (en) * | 2011-11-21 | 2013-06-06 | Hitachi Appliances Inc | Motor control device and air conditioner |
| CN203206212U (en) * | 2013-01-10 | 2013-09-18 | 大唐微电子技术有限公司 | Clock frequency division circuit, clock generation network and chip |
| CN102969860B (en) * | 2012-10-26 | 2015-01-28 | 华中科技大学 | Frequency converting control system |
| CN205725547U (en) * | 2016-06-03 | 2016-11-23 | 中国电子科技集团公司第四十三研究所 | A kind of digital frequency division phase-shift circuit driving control for three-phase synchronous motor |
-
2016
- 2016-06-03 CN CN201610409488.2A patent/CN105897111B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158205A (en) * | 2011-03-14 | 2011-08-17 | 北京龙芯中科技术服务中心有限公司 | Clock frequency multiplier, device and clock frequency multiplication method |
| JP2013110859A (en) * | 2011-11-21 | 2013-06-06 | Hitachi Appliances Inc | Motor control device and air conditioner |
| CN102969860B (en) * | 2012-10-26 | 2015-01-28 | 华中科技大学 | Frequency converting control system |
| CN203206212U (en) * | 2013-01-10 | 2013-09-18 | 大唐微电子技术有限公司 | Clock frequency division circuit, clock generation network and chip |
| CN205725547U (en) * | 2016-06-03 | 2016-11-23 | 中国电子科技集团公司第四十三研究所 | A kind of digital frequency division phase-shift circuit driving control for three-phase synchronous motor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105897111B (en) | 2018-08-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103780254A (en) | Phase lock loop with multiphase oscillator | |
| CN103546151B (en) | High-speed DLL (Delay-locked loop) | |
| CN102412836B (en) | Dual programmable subtraction frequency divider | |
| CN103675373B (en) | A kind of digital signal generating method realized in FPGA | |
| CN103166605B (en) | A kind of heterogeneous non-overlapping clock circuit | |
| CN205725547U (en) | A kind of digital frequency division phase-shift circuit driving control for three-phase synchronous motor | |
| CN104579316B (en) | Programmable frequency divider with fifty-percent duty cycles | |
| CN105897111A (en) | Digital frequency dividing and phase shifting circuit for driving control of three-phase synchronous motor | |
| CN108540128B (en) | Clock frequency dividing circuit and frequency dividing method thereof | |
| US6404839B1 (en) | Selectable clock divider circuit with a 50% duty cycle clock | |
| JPS62245814A (en) | Pulse circuit | |
| CN103888131A (en) | Locking detection circuit for PLL circuit | |
| JP2007282080A (en) | Four-phase output 2(2n+1) frequency division phase shifter | |
| CN106571813A (en) | Novel edge-type high-resistance digital phase discriminator | |
| KR20070084525A (en) | Microcontroller having a digital to frequency converter and/or a pulse frequency modulator | |
| CN102035538B (en) | High-speed programmable frequency divider | |
| CN202406098U (en) | Low-noise four-mode frequency divider | |
| CN203813760U (en) | Shift frequency divider circuit | |
| EP1626501A1 (en) | Variable division method and variable divider | |
| US9590637B1 (en) | High-speed programmable frequency divider with 50% output duty cycle | |
| CN203563053U (en) | High-speed DLL (Delay-locked loop) | |
| CN106209094A (en) | A kind of implementation method based on FPGA 50% dutycycle fractional frequency division | |
| US20200007113A1 (en) | Spectrally efficient digital logic | |
| US9564904B2 (en) | Asynchronous high-speed programmable divider | |
| US9319048B2 (en) | Clock divider |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |