CN105893644B - Layout pattern decomposition method for electron beam and double-pattern hybrid lithography process - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit semiconductor manufacturing, and relates to a method for decomposing a layout pattern in an electron beam and double-pattern photoetching process. The method expresses the decomposition problem of the layout pattern which simultaneously minimizes the use area of the electron beam and the number of the stitching points into a two-division problem of deleting points; the method comprises the following steps: constructing a conflict graph G containing virtual points according to the input layout file and the conflict distance B; converting the two division problems of the deletion points on the flattened conflict graph into the odd ring coverage problem; solving the odd ring coverage problem by using a primal-dual method; and post-processing the residual protruding edges. The method is high in feasibility, can obtain a solution result superior to that of the traditional two-stage method in reasonable time, and can be used for solving the problem of pattern decomposition of large-scale territory.

Description

Layout pattern decomposition method for electron beam and double-pattern hybrid lithography process

Technical Field

The invention belongs to the technical field of integrated circuit semiconductor manufacturing, and relates to a layout pattern decomposition method for an electron beam and double-pattern mixed etching process, which takes the minimum use of electron beams and the number of stitching points as optimization targets.

Background

With the further shrinking of the feature size of the integrated circuit, the exposure resolution of the conventional lithography process is approaching to the physical limit, and it is difficult to produce the chip with sub-22 nm feature size, so that the next generation lithography technologies such as ultra-violet lithography (EUV), Electron Beam Lithography (EBL) and Double Patterning Lithography (DPL) are required. Among these techniques, the extreme ultraviolet etching technique and the electron beam etching technique have not been mass-produced for various reasons. The double patterning lithography technique can significantly enhance the conventional 193nm lithography process, but even if the stitch point (sticch) is inserted by cutting the pattern on the layout into smaller pieces, there are still many solution-free conflicts that are difficult to eliminate. This problem is particularly acute for complex layouts.

In order to further eliminate the conflict-free in the double-pattern photoetching technology, a layout modification technology such as a layout compression technology [1] and a double-pattern photoetching layer distribution technology [2] after wiring is provided. However, these techniques inevitably alter the original layout of the layout, possibly destroying the electrical characteristics of the layout and even altering the functionality of the circuit.

A single etching technique cannot satisfy chips with increasingly smaller feature sizes and increasingly complex structures. Over the past decades, the industry and academia have begun to explore the combination of different etching process technologies, in particular the combination of lithography and electron beam etching processes [3] [4 ]. The photoetching and electron beam mixed etching process mainly comprises two processes: (1) high throughput but low resolution photo etching to produce most of the patterns on the chip layout; (2) low throughput but high resolution electron beam lithography is used to produce patterns with extremely tight gaps on the chip layout. If a double patterning lithography process is applied to the first stage process, the first stage lithographic capability is further enhanced, thereby reducing the use of second stage e-beam lithography.

Research in recent years shows that the 5 < 6 > 7 hybrid etching technology has very wide prospect. Document [5] describes a method of generating a one-dimensional layout by combining a Self-aligned Double Patterning (SADP) and an electron beam. Document [6] introduces a self-aligned double pattern and complementary electron beam hybrid process layout pattern decomposition method. Since in the self-aligned double patterning process, the patterns on the layout cannot be cut into smaller pieces by inserting stitching points, more electron beams are inevitably used in order to solve the problem of no solution conflict. In contrast, LELE (Litho-Etch-Litho-Etch) type of multiple pattern and e-beam hybrid lithography process [7] has a greater ability to resolve conflicts, especially for random logic circuit layouts, since stitching points can be inserted.

The method for solving the problem of layout pattern decomposition of the double pattern and electron beam mixed etching process adopts a direct two-stage method, also called a double pattern decomposition post-processing method, and comprises the following two steps: (1) firstly, double coloring is carried out on a conflict graph of a layout; (2) then, the minimum point set is deleted on the double-colored conflict graph to solve the conflict-free problem, and the pattern corresponding to the point set is produced by adopting electron beam etching. The advantage of this approach is that many of the existing classical double pattern layout decomposition methods can be reused. However, since the optimization of the number of double pattern stitches and the use of the electron beam is independently performed in two stages, respectively, the solution quality measured in terms of the number of stitches and the use of the electron beam in area weight is poor.

Aiming at the defects, the invention provides the electron beam and double pattern mixed etching process layout pattern decomposition method which simultaneously optimizes the number of double pattern stitching points and the use area of the electron beam. The method is used for solving the problem of layout pattern decomposition of the electron beam and double pattern mixed process for the first time by using a primal-dual method, and can obtain a high-quality solution result in a reasonable time so as to meet the requirements of practical application.

References relevant to the present invention are:

[1]S.-Y.Fang,S.-Y.Chen,and Y.-W.Chang,“Native-conflict and stitch-aware wire perturbation for double patterning technology,”Computer-AidedDesign of Integrated Circuits and Systems,IEEE Transactions on,vol.31,no.5,pp.703–716,2012.

[2]J.Sun,Y.Lu,H.Zhou,and X.Zeng,“Post-routing layer assignment fordouble patterning,”in ASP-DAC,2011,pp.793–798.

[3]S.Steen,S.McNab,L.Sekaric,I.Babich,J.Patel,J.Bucchignano,M.Rooks,D.Fried,A.Topol,J.Brancaccio et al.,“Looking into the crystal ball:futuredevice learning using hybrid e-beamand optical lithography(keynote paper),”inMicrolithography 2005.International Society for Optics and Photonics,2005,pp.26–34.

[4]Y.Du,H.Zhang,M.D.Wong,and K.-Y.Chao,“Hybrid lithographyoptimization with e-beam and immersion processes for 16nm 1D gridded design,”in ASP-DAC,2012,pp.707–712.

[5]Y.Ding,C.Chu,and W.-K.Mak,“Throughput optimization for SADP and e-beam based manufacturing of 1D layout,”in DAC,2014,pp.1–6.

[6]J.-R.Gao,B.Yu,and D.Z.Pan,“Self-aligned double patterning layoutdecomposition with complementary e-beam lithography,”in ASP-DAC,2014,pp.143–148.

[7]H.Tian,H.Zhang,Z.Xiao,and M.D.Wong,“Hybrid lithography for triplepatterning decomposition and e-beam lithography,”in SPIE AdvancedLithography.International Society for Optics and Photonics,2014,pp.90520P–90520P.

[8]M.X.Goemans and D.P.Williamson,“Primal-dual approximationalgorithms for feedback problems in planar graphs,”Combinatorica,vol.18,no.1,pp.37–59,1998.

[9]J.M.Schmidt,“A simple test on 2-vertex-and 2-edge-connectivity,”Information Processing Letters,vol.113,no.7,pp.241–244,2013.

[10]N.W.Parker,A.D.Brodie,and J.H.McCoy,“High-throughput NGLelectron-beam direct-write lithography system,”in Microlithography2000.International Society for Optics and Photonics,2000,pp.713–720.

[11]A.B.Kahng,C.-H.Park,X.Xu,and H.Yao,“Layout decomposition fordouble patterning lithography,”in IEEE/ACM International Conference onComputer-Aided Design(ICCAD).IEEE,2008,pp.465–472.

[12]W.-S.Luk and H.Huang,“Fast and lossless graph division method forlayout decomposition using SPQR-tree,”in ICCAD,2010,pp.112–115.

[13]G.Ausiello and et al,Complexity and Approximability Properties:Combinatorial Optimization Problems and Their ApproximabilityProperties.Springer,1999.

[14]F.Hadlock,“Finding a maximumcut of a planar graph in polynomialtime,”SIAM Journalon Computing,vol.4,no.3,pp.221–225,1975.

[15]H.-A.Choi,K.Nakajima,and C.S.Rim,“Graph bipartization and viaminimization,”SIAM Journal on Discrete Mathematics,vol.2,no.1,pp.38–47,1989.

[16]J.Hopcroft and R.Tarjan,“Efficient planarity testing,”Journal ofthe ACM(JACM),vol.21,no.4,pp.549–568,1974.

[17]Y.F.Yang,W.S.Luk,H.Zhou,C.H.Yan,and X.Zeng,“Layout decompositionco-optimization for hybrid e-beam and multiple patterning lithography,”inASP-DAC,2015.

disclosure of Invention

Aiming at the defects of the traditional two-stage method, the invention provides the electron beam and double pattern mixed etching process layout decomposition method which optimizes the number of double pattern stitching points and the use area of the electron beam simultaneously. The method establishes a conflict graph for an input layout according to a given conflict distance, and models a layout decomposition problem into a two-division (VDB) problem of Deletion points on the conflict graph. Because the problem is an NP difficult problem, the time complexity for solving the optimal solution is extremely high, and the requirement of practical application cannot be met. The method of the invention firstly applies the primal-dual method to solve the problem of the decomposition of the electron beam and double-pattern mixed photoetching layout, and can obtain high-quality solution results within reasonable time. The method of the invention fully utilizes duality of two forms of the same problem, improves the original problem by solving the dual problem, thereby effectively controlling algorithm complexity, obviously improving solving quality and better meeting the requirement of practical application.

Since the same polygon can be produced by two different process technologies, which results in higher production cost and reduced yield, the present invention assumes that the same polygon can be produced by only one process technology (i.e., electron beam lithography or double patterning lithography). The present invention employs a conventional variable-shape rectangular electron beam (VSB) [6] [7], and unlike the literature [6] [7] in which the number of VSBs is the optimization target, the present invention employs the total area of VSBs as the optimization target, since the writing time of the electron beam is determined by the total area of VSBs for a given beam current and dose, and the main difficulty of electron beam lithography is that throughput is insufficient.

For a given conflict graph G ═ (V, E)_c∪E_s) Where a point V in the set of vertices V represents a rectangle on the layout, E_cRepresenting a set of candidate conflict edges, E_sRepresenting a set of candidate stitched point edges. Weight function

A_vGenerally representing the rectangular area represented by the vertex v. Solving for a subset of V

So as to be constituted by vertices in VSub-graph G 'is a bipartite graph (i.e., a graph not containing odd rings), where G' is a sub-graph containing only vertex set V 'and corresponding edges (with overhanging edges removed), and corresponding two-color assignment results c: V' → [1,2 →]. In addition, for V ∈ V \ V', then for all (u, V) ∈ E_sU must also be in the set of points V \ V', since u, V belong to the same polygon. The electron beam throughput and the double pattern stitch number weighted cost are minimized, i.e.:

wherein α and β are given weight constants, E'_s＝{(u,v)|(u,v)∈E_s,u∈V',v∈V',c_u≠c_vTypically α > β, since the cost of the e-beam process is much greater than the stitched edges introduced in double pattern lithography.

The electron beam and double pattern hybrid lithography process layout decomposition problem has been formalized as a point-deletion two-division problem. Typically, this problem is an NP problem [13 ]. It should be noted that the simple dual pattern lithography process layout decomposition problem is an Edge Deletion partitioning (Edge Deletion partitioning) problem. Solving the two-partition problem of the deletion point is more difficult than solving the two-partition problem of the deletion edge because the two-partition problem of the deletion edge on the plane graph has an optimal algorithm of polynomial complexity [14], but for the two-partition problem of the deletion point, obtaining the optimal solution of the two-partition problem of the deletion point on the plane graph with the maximum vertex degree not less than 4 is still an NP-hard problem [15 ].

The flow of the mixed process layout pattern decomposition method provided by the invention is shown in figure 1. a.

The parameters of layout file, conflict distance B, electron beam area weight α and stitching edge weight β are input.

And outputting a result: electron beam and double pattern layer assignment of layout patterns.

Step 1: and constructing a conflict graph G containing virtual points according to the input layout file and the conflict distance B.

Step 2: the problem of resolving the layout pattern of the electron beam and double-pattern hybrid photoetching process is converted into the problem of odd ring coverage.

And step 3: solving the odd-numbered ring coverage problem by using a primal-dual method.

And 4, step 4: and adding the deleted non-planar edges back to the conflict graph G, then deleting the minimum point set to solve the residual conflict edges, and ending the algorithm.

Specifically, in step 1, the method of the present invention constructs a conflict graph containing virtual points through the following substeps:

step 1.1: according to the method in document [11] [12], polygons on a layout are cut into rectangles. The rectangle may be further cut into smaller pieces to resolve the conflict. Each rectangle constitutes a vertex in the conflict graph G. Fig. 2.b shows a specific example of a layout in which polygons are cut into rectangles.

Step 1.2: and constructing the conflict edges and the candidate stitching point edges in the conflict graph. That is, if two rectangles are from different polygons and their minimum separation is less than the conflict distance B, then they have a conflict edge between the corresponding vertices in the conflict graph; if two rectangles are from the same polygon and they are close to each other, then they have a candidate stitching point edge between the corresponding vertices in the conflict graph.

For example, fig. 2.c shows a specific example of constructing a collision graph on a cut rectangle, where: the solid line is the protruding edge, and the dotted line is the candidate stitching point edge. In fig. 2.c, the rectangles 21, 22, 23 are from the same polygon, 21 being close to 22, 22 being close to 23, there is one candidate stitch point edge between 21 and 22, 22 and 23 respectively. Rectangle 1 and rectangle 21 come from different polygons and the minimum separation between them is less than the collision distance, so there is a conflict edge between them.

Step 1.3: one candidate stitched edge is replaced with one virtual point and two corresponding virtual edges. Step 1.3 is repeated until all candidate stitched edges are replaced.

In order to uniformly consider the minimization of the electron beam using area and the number of the stitching points in a dot-deleted mode, the invention replaces one candidate stitching edge by one virtual point and two corresponding virtual edges. Such a substitution does not change the dichotomy property of the original conflict graph. For example, fig. 3.a is an even number of loops (not counting stitching edges), which remains after the stitching edges are replaced in fig. 3. b; fig. 3.c is an odd number of loops (disregarding the stitching edge) which remains after the stitching edge has been replaced in fig. 3. d. The weight of each virtual point is typically set to the weight of the corresponding stitched edge. The degree of the virtual point is always 2. In the two-division problem of the deletion point, if one virtual point is deleted only when the virtual point exists, which may cause odd-numbered rings, then keeping one virtual point is equivalent to making the corresponding candidate stitched edge invalid, and deleting one virtual point is equivalent to making the corresponding candidate stitched edge valid.

Specifically, in step 2, the method of the present invention converts the layout pattern decomposition problem into the odd ring coverage problem through the following substeps:

step 2.1: flattening the original conflict graph, which comprises the following steps:

step 2.1.1: all edges in the conflict graph are sorted by their weights.

Step 2.1.2: a maximum planar subgraph is found. Deleting all edges in an edge set of an original conflict graph, adding the sequenced edges back to the conflict graph one by one, detecting the planarity [16], and if the addition of the conflict edge does not cause the occurrence of a non-planar graph, keeping the edge; otherwise, the edge is deleted.

Step 2.2: and (4) finding and deleting the non-ring edges in the conflict graph by using a chain decomposition method [9 ].

Step 2.3: converting the two division problems of the deletion points on the conflict graph into the odd ring coverage problem, and specifically comprising the following steps of:

step 2.3.1: the original (primal) form of the odd ring coverage problem can be described as follows:

min∑_v∈Vw_v·x_v， (2.1)

where C is an odd ring, v is a vertex on the odd ring, O is the set of all odd rings, w_vIs the weight of the vertex v. x is an m-dimensional vector of which each element x_vA value of 1 indicates that v is an override, i.e., v is deleted, x_vA value of 0 indicates that v is reserved. Equation (2.2) indicates that each odd ring is covered by at least one vertex.

Constraining x by relaxing integers_vE {0,1} is x_vNot less than 0, the original form of the odd ring coverage problem can be converted into the form of the following linear programming:

min w^Tx， (3)

s.t.A·x≥p，

wherein, the number n of odd rings is | O |, the number m of the top points of the conflict graph is | V |, the operation | is to obtain the number of elements in the set, and the unit vector p with dimension n × 1^T(1, 1), w is the vertex weight vector, element a of the odd-numbered ring matrix a_ijThe definition is as follows:

step 2.3.2: a dual form of the problem is obtained. It can be confirmed that the dual problem of [17], problem (3) can be expressed in the form of,

min p^Ty， (4)

s.t.A^T·y≤w，

y≥0，

wherein y is a dual variable.

Problem (3) is in its original form and problem (4) is in its dual form. There is a complementary relaxed relationship between primitive and dual, i.e., if a set of feasible primitive-dual pairs x, y is the optimal solution, the following conclusions can be drawn:

original relaxation:

dual relaxation:

wherein, a^jIs the vector of the jth column in matrix A, a_iIs the vector in row i of matrix a.

Through the step 2.3.1 and the step 2.3.2, the two-division problem of the deletion points on the conflict graph can be converted into the odd ring coverage problem.

Specifically, in step 3, the method of the present invention solves the odd-numbered ring coverage problem using the primal-dual method by the following steps.

In the present invention, a subset of the set of all odd rings is found by computing Face rings (Face cycles) in the conflict graph, for which a minimum weighted vertex coverage is found. After deleting this partial odd ring overlay, the invention iteratively recalculates a face ring again and looks for another partial odd ring overlay until there are no odd rings. The application of the primal-dual method to solve the odd-numbered ring coverage problem comprises two iterations, namely an outer iteration and an inner iteration, and comprises the following sub-steps, wherein the flow chart is shown in fig. 1. b:

step 3.1: initializing set of vertices in conflict graph that need to be deleted

Step 3.2: starting outer layer iteration, if the conflict graph has no odd rings after the point set S is removed, covering all the odd rings by the point set S, ending the outer layer iteration, and turning to the step 3.8; if there are odd rings in the conflict graph after the point set S is removed, which indicates that the point set S has not covered all the odd rings, the algorithm proceeds to step 3.3.

Step 3.3: and deleting the non-ring edges in the conflict graph, and calculating an uncovered odd ring set FS.

On a plane graph, the method calculates face rings (a closed area formed by a group of edge sets connected end to end) on the graph by tracking the edge sets connected end to end, if the number of the edges of a certain face ring is odd, the degree of the face ring is odd, and the face ring is added into an odd ring set FS until all non-intersected odd rings (namely part of the odd ring set) are calculated.

Step 3.4: and initializing the dual variables corresponding to each odd ring.

For each odd ring in FS, there is a corresponding dual variable y_CInitialize all dual variables to 0, i.e., y_C＝0,

Step 3.5: the inner layer iteration starts, if the conflict graph has no uncovered odd rings, the algorithm meets the constraint, the inner layer iteration is finished, and the step 3.7 is carried out; if there are any uncovered odd rings in the conflict graph, the algorithm proceeds to step 3.6.

Step 3.6: calculating gap (C) of uncovered odd ring pair variables_i) Finding the most compact odd ring C_tightAnd corresponding vertex v_tightAnd adding S, updating dual variables of all odd rings, and then turning to step 3.5.

Let F denote the set of all uncovered odd rings. In order to track vertices from the same polygon, a mapping is defined,

let Cyc (VP (v)) represent the set of odd degree surface rings passing through any point in the point set VP (v), let Cyc (VP (v)) represent the set of odd degree surface rings

Indicating that there is no odd-numbered face ring subset covered in Cyc (VP (v)). The invention gradually changes all uncovered odd rings by finding the odd ring with the most compact gapThe dual variables of the number ring, namely:

and the corresponding vertex,

updating all dual variables, i.e. y_C＝y_C+gap(C_tight)，

The set S ═ S ∪ VP (v) is then expanded_tight)。

Step 3.7: the set of points S and their associated edges are removed from the conflict graph G and step 3.2 is entered.

Step 3.8: and locally improving the solving result, namely sequencing the points in the point set S in a descending order according to the weight, and for any vertex v epsilon S, if S \ VP (v) is a feasible odd ring cover, then S \ VP (v), wherein S \ VP (v) is the difference between the set S and the set VP (v).

Specifically, the specific process of adding the non-planar edge deleted in step 2.1 back to the conflict graph in step 4 and then deleting the minimum set of points to solve the remaining conflict edges is as follows: after solving the minimum weight odd ring overlay problem on the maximum planar subgraph, the method of the invention adds back the non-planar edges deleted in step 2. If adding back a non-planar edge does not result in a conflict, the edge will be retained. For all non-planar edges which can cause conflict, the method establishes a residual conflict graph again, and then deletes a minimal-weight vertex set to solve the conflict edges in the graph.

The invention finally outputs the coloring results of the deleted point set and the residual vertex set on the conflict graph, and can obtain the distribution results of the electron beams and the double-pattern photoetching layer of the corresponding patterns on the layout according to the coloring results, namely the final layout pattern decomposition result.

The layout pattern decomposition method has the following advantages:

1. the invention firstly converts the problem of the decomposition of the electron beam and double-pattern mixed etching layout into a special coverage linear programming problem which is an NP difficult problem. A heuristic algorithm of polynomial time complexity based on a primal-dual method is provided. For the special case where the conflict graph is a plan graph (still an NP-hard problem), the class problem form guarantees that the class problem has an approximation algorithm of polynomial time complexity.

2. The method simultaneously optimizes the use area of the electron beam and the number of double pattern stitching points, and compared with the traditional two-stage method, the method has the advantage that the solution result is closer to the global optimal solution.

3. The invention firstly relaxes variables and then improves the original problem by solving the dual problem, thereby effectively controlling the algorithm complexity which is O (n)²) And n is the number of the vertices of the conflict graph.

Drawings

FIG. 1.a is a flow chart of the method of the present invention.

FIG. 1.b is a flow chart for solving the odd-numbered ring coverage problem using the primal-dual.

Fig. 2.a is an uncut original layout.

And 2.b is a layout after cutting the polygon into rectangles.

FIG. 2.c is a conflict graph constructed on the layout cut into rectangles.

In FIG. 3, a, b, c, d and g are schematic diagrams of an even number of rings (with no stitching).

FIG. 3.b is a schematic diagram showing the binary property of the graph, wherein the stitched edge (d, g) is replaced by a virtual point h and two virtual edges (h, g), (h, d).

In fig. 3, a, c, d and g are an odd number of rings (the sewing edge is not counted).

Fig. 3.d is a schematic diagram showing the binary property of the graph, wherein the stitched edge (d, g) is replaced by a virtual point h and two virtual edges (h, g), (h, d).

FIG. 4.a is a schematic diagram of a layout pattern decomposition result in a double-pattern lithography process according to a first embodiment of the present invention.

Fig. 4.b is a schematic diagram of a layout pattern decomposition result of the electron beam and double pattern hybrid etching process in the first embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

EXAMPLES example 1

The first embodiment of the present invention is intended to illustrate that hybrid etching has a stronger etching capability than double pattern lithography. In this embodiment, the test layout is a 45nm cell library unit, and the collision distance is set to 200 nm. The dual pattern lithography process layout decomposition results and the hybrid etching process layout decomposition results are shown in fig. 4.

As can be seen from fig. 4.a, under the condition of the double-pattern lithography process, there are still many conflicts that cannot be eliminated after the layout is decomposed, and because of the existence of these non-solution conflicts, the layout cannot be produced under the condition of the double-pattern lithography process, and the layout needs to be modified again until all the non-solution conflicts can be eliminated. Fig. 4.b is a schematic diagram showing the electron beam and double pattern hybrid etching, under the condition of the hybrid etching process, the layout does not need to be modified, the polygonal patterns which have conflict on the layout but can be decomposed on two different masks can be produced by double pattern lithography, and the polygonal patterns which have conflict on the layout and can not be solved by being decomposed on two different masks can be directly etched by the electron beam. This embodiment clearly demonstrates that hybrid etching has a stronger etching capability than double pattern lithography.

EXAMPLES example 2

The minimum line width and the minimum line spacing of the test layout are respectively 30nm and 50nm in the embodiment, the weight constant α is respectively set to be 100 and 1, the conflict distance is set to be 120nm, a two-stage method is used as a comparison reference, the two-stage method is firstly used for carrying out double-pattern layout decomposition once, and then a point set with the minimum weight is deleted to solve the conflict edge which cannot be eliminated, and the method in the document [12] is used as a double-pattern layout decomposition solver in the first stage.

The method is realized by using a C + + programming language and runs on a 64-bit linux machine with a 3.00GHz central processing unit and a 4GB memory. The test layout is from the first metal layer layout in the ISCS-85 &89 test example. The statistical information of the test cases is shown in table 1. # Polygon represents the number of polygons, # Conf represents the initial number of collisions, # Node and # Edge represent the number of vertices and edges in the collision graph, respectively, # NPE represents the number of non-planar edges determined by the method of the present invention, and ratio represents the percentage of non-planar edges, i.e., ratio # NPE/# Edge.

The experimental results of this example are shown in Table 2.A represents the total area of the variable rectangular electron beams (VSB), # VSB represents the total number of the variable rectangular electron beams, # S represents the total number of the double pattern stitching points, and time represents the time consumed by the layout decomposition. two-stage-num represents a two-stage method with a VSB total number as an optimization target, and two-stage-area represents a two-stage method with a VSB total area as an optimization target. The two-stage-area method can reduce the electron beam usage by 37.3% on average, compared to the two-stage-num method, although the total number of VSBs is slightly increased. On average, the method of the invention can reduce the total area of the electron beam by 64.4% compared to the two-stage-area method. The run time of the present invention is slightly increased over the two-stage method, but is substantially comparable. The total number of double pattern stitching points # S determined by the method of the present invention is somewhat greater than the results of the two-stage method, and these increased stitching points are intended to resolve double pattern conflicts. Since the use cost of the electron beam is much larger than the production cost of the double pattern stitch, the primary goal of the layout decomposition is to reduce the total area a of the electron beam. The experimental result verifies the effectiveness of the method.

TABLE 1 test layout statistics

Layout	#Polygon	#Conf	#Node	#Edge	#NPE	ratio
							C432	1033	2937	2883	4787	273	5.70％
C499	2134	6494	5536	9896	681	6.88％
							C1355	2963	8390	8915	14342	610	4.25％
C3540	9910	25026	26274	41390	1899	4.59％
							C5315	14235	37184	38523	61472	3541	5.76％
C7552	20490	52846	55677	88034	4153	4.72％
							S38417	66182	142127	144501	220465	6942	3.15％
S35932	150137	354564	342529	546956	20957	3.83％
							S38584	162792	346718	355001	538932	17626	3.27％
S15850	155508	347250	349210	540952	19340	3.58％

TABLE 2 comparison of the results of the process of the invention and the two-stage process

Claims (4)

1.A layout pattern decomposition method for electron beam and double pattern hybrid photoetching process is characterized by comprising the following steps:

inputting parameters of a layout file, a conflict distance B, an electron beam area weight α and a stitching edge weight β;

and outputting a result: an electron beam and double pattern layer allocation scheme for the layout pattern;

step 1: constructing a conflict graph G containing virtual points according to the input layout file and the conflict distance B;

step 2: converting the layout pattern decomposition problem of the electron beam and double pattern hybrid photoetching process into an odd ring coverage problem; specifically, the layout pattern decomposition problem is converted into an odd ring coverage problem through the following substeps:

step 2.1: flattening the original conflict graph; the method specifically comprises the following substeps:

step 2.1.1: sorting all edges in the conflict graph according to the weights of the edges;

step 2.1.2: finding a maximum plane subgraph; deleting all edges in an edge set of an original conflict graph, adding the sequenced edges back to the conflict graph one by one, and carrying out planarity detection, if adding the conflict edge back does not cause a non-planar graph, keeping the edge; otherwise, deleting the edge;

step 2.2: finding and deleting the non-ring edges in the conflict graph by using a chain decomposition method;

step 2.3: converting two division problems of deleting points on a conflict graph into an odd ring coverage problem;

and step 3: solving the odd ring coverage problem by using a primal-dual method;

and 4, step 4: and adding the deleted non-planar edges back to the conflict graph G, then deleting the minimum point set to solve the residual conflict edges, and ending the algorithm.

2. The method for decomposing layout pattern in electron beam and double pattern hybrid lithography process according to claim 1, wherein the step 1 constructs the conflict graph including the virtual points by the following substeps:

step 1.1: cutting polygons on the layout into rectangles;

step 1.2: constructing conflict edges and candidate stitching edges in the conflict graph; that is, if two rectangles are from different polygons and their minimum separation is less than the conflict distance B, then they have a conflict edge between the corresponding vertices in the conflict graph; if two rectangles are from the same polygon and they are close to each other, then they have a candidate stitched edge between the corresponding vertices in the conflict graph;

step 1.3: replacing a candidate stitching edge by a virtual point and two corresponding virtual edges; step 1.3 is repeated until all candidate stitched edges are replaced.

3.A method according to claim 1 or 2, characterized in that said step 2.3 of converting the two-partition problem of the puncture points on the collision map into the odd-numbered ring coverage problem comprises the steps of:

step 2.3.1: the original (primal) form of the odd ring coverage problem can be described as follows:

min ∑_v∈Vw_v·x_v， (2.1)

where C is an odd ring, v is a vertex on the odd ring, O is the set of all odd rings, w_vIs the weight of vertex v; x is an m-dimensional vector of which each element x_vA value of 1 indicates that v is an override, i.e., v is deleted, x_vA value of 0 indicates that v is reserved; equation (2.2) indicates that each odd ring is covered by at least one vertex;

constraining x by relaxing integers_vE {0,1} is x_vNot less than 0, the original form of the odd ring coverage problem can be converted into the form of the following linear programming:

min w^Tx， (3)

s.t.A·x≥p，

x_v≥0,

wherein, the number n of odd rings is | O |, the number m of the top points of the conflict graph is | V |, the operation | is to obtain the number of elements in the set, and the unit vector p with dimension n × 1^T(1, 1), w is the vertex weight vector, odd for the odd ring matrix aElement a_ijThe definition is as follows:

step 2.3.2: obtaining a dual form of the problem; i.e. the dual problem of equation (3) can be expressed in the form of,

min p^Ty， (4)

s.t.A^T·y≤w，

y≥0，

wherein y is a dual variable.

4. The method for resolving layout pattern in electron beam and double pattern hybrid lithography process as claimed in claim 1, wherein said step 3 of solving the odd ring coverage problem with a primal-dual method comprises two iterations, an outer iteration and an inner iteration, comprising the sub-steps of:

step 3.1: initializing set of vertices in conflict graph that need to be deleted

Step 3.2: starting outer layer iteration, if the conflict graph has no odd rings after the point set S is removed, covering all the odd rings by the point set S, ending the outer layer iteration, and turning to the step 3.8; if odd rings still exist in the conflict graph after the point set S is removed, the point set S does not cover all the odd rings, and the algorithm enters step 3.3;

step 3.3: deleting the non-ring edges in the conflict graph, and calculating an uncovered odd ring set FS;

step 3.4: initializing a dual variable corresponding to each odd ring;

step 3.5: the inner layer iteration starts, if the conflict graph has no uncovered odd rings, the algorithm meets the constraint, the inner layer iteration is finished, and the step 3.7 is carried out; if there are any uncovered odd rings in the conflict graph, the algorithm proceeds to step 3.6;

step 3.6: calculating uncovered oddsGap (C) of number ring dual variable_i) Finding the most compact odd ring C_tightAnd corresponding vertex v_tightS is added, dual variables of all odd rings are updated, and then the step 3.5 is carried out;

let F denote the set of all uncovered odd rings; in order to track vertices from the same polygon, a mapping is defined,

let Cyc (VP (v)) represent the set of odd degree surface rings passing through any point in the point set VP (v), let Cyc (VP (v)) represent the set of odd degree surface rings

Represents the odd-degree face ring subset not covered yet in Cyc (VP (v)); the dual variables of all uncovered odd rings are gradually changed by finding the odd ring with the most compact gap, namely:

and the corresponding vertex,

updating all dual variables, i.e. y_C＝y_C+gap(C_tight)，

Then expand the set

；

Step 3.7: updating dual variables of all odd rings, expanding the set S, deleting the point set S from G, and turning to the step 3.2;

step 3.8: and locally improving the solving result, namely sequencing the points in the point set S in a descending order according to the weight, and for any vertex v epsilon S, if S \ VP (v) is a feasible odd ring cover, then S \ VP (v), wherein S \ VP (v) is the difference between the set S and the set VP (v).

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