CN1058824C - Synchronous display control circuit - Google Patents
Synchronous display control circuit Download PDFInfo
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- CN1058824C CN1058824C CN95119101A CN95119101A CN1058824C CN 1058824 C CN1058824 C CN 1058824C CN 95119101 A CN95119101 A CN 95119101A CN 95119101 A CN95119101 A CN 95119101A CN 1058824 C CN1058824 C CN 1058824C
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Abstract
The synchronous display control circuit in accordance with the present invention is mainly composed of odd-even field separation circuit, display control circuit, reference clock pulse generator, display clock circuit, odd-field pulse broadening circuit, even-field pulse broadening circuit and synchronous pulse-broadening circuit, in which the odd-even field separation circuit mainly is composed of pulse-broadening circuit 11, large register, small regiter and two AND devices, IC6 and IC7. The output ends of said two AND devices are respectively used as output end a of odd field and output end b of even field, and its display control circuit is composed of line-control circuit and dot-control circuit. Said invention possesses the advantages that it can enable tv images to reappear through array type display and helps to realize super-thin type television receiver of large screen.
Description
The present invention is a kind of synchronous display control circuit, especially the TV receiver display control circuit.
Existing television set is to utilize cathode ray tube as display, and its display control circuit must mate mutually with cathode ray tube.The developing direction of television set is large-screen and ultrathin type at present, the length-width ratio of cathode ray tube is the key factor that the restriction television set further develops, meanwhile, be tending towards ripe such as array displaies such as LCDs, but, make the array display still can not be applied to general television receiver because existing TV signal emission standard is finalized the design.
The object of the present invention is to provide a kind of synchronous display control circuit, can make array-type display reproduce television image.
The technical solution adopted in the present invention is: described synchronous display control circuit mainly is made up of parity field split circuit, display control circuit, reference clock pulse generator, read clock circuit and strange field pulse widening circuit, even field pulse widening circuit, sync stretch circuit, wherein, the control end Vk of reference clock pulse generator is connected with original range separation circuit in the television set by the Q end of a d type flip flop.The input of described parity field split circuit is connected with the output of range separation circuit with reference clock pulse generator 2, parity field split circuit 1 has strange field signal output a and even field signal output b, wherein strange field signal output a is connected with strange field pulse widening circuit 8 by P type the 3rd MOS switching tube K3, simultaneously strange field signal output a also is connected clock drive end and the input D of second d type flip flop IC2, described even field signal output b is by second, the 4th MOS switching tube K2, K4 is connected with even field pulse widening circuit 9, wherein the control end of the 2nd MOS switching tube K2 is connected on the output Q of described second d type flip flop IC2, and the 4th MOS switching tube K4 is connected between the 2nd MOS switching tube K2 and the even field pulse widening circuit 9.The output of above-mentioned strange field pulse widening circuit 8 and even field pulse widening circuit 9 is connected on the display control circuit 6 simultaneously, and, the output of strange field pulse widening circuit 8 is connected with the conducting control end of the 4th MOS switching tube K4, and the output of even field pulse widening circuit 9 is connected with the conducting control end of the 3rd MOS switching tube K3.Described sync stretch circuit 10 is connected on the television set between the original range separation circuit 3 and display control circuit 6, described read clock circuit 7 is connected between the output and display control circuit 6 of sync stretch circuit 10, and original looking put output circuit and be connected on the display simultaneously on described display control circuit and the television set.
Above-mentioned parity field split circuit is mainly by stretch circuit 11, big register and little register and two and a door IC6, IC7 forms, these two and a door IC6, the output of IC7 is respectively as a strange output a and an idol output b, described big register is connected in sequence by 16 d type flip flop B1～B16, the Q end of each d type flip flop Bn links to each other with the D end of next d type flip flop Bn-1, and the D of the 16th d type flip flop B16 end is connected with original range separation circuit 3 in the television set by described stretch circuit 11, trigger B1 in the big register, B2, B13, the Q of B14 end as the output of big register with door IC6,7 input connects.Described little register by the 3rd, four d flip-flop IC3, IC4 and form with door IC5, wherein the D of 3d flip-flop IC3 end is connected with original range separation circuit 3 in the television set, and the Q of 3d flip-flop IC3 end is connected with the D end of four d flip-flop IC4, three, four d flip-flop IC3,4 Q end is connected simultaneously with the input of door IC5 and is connected, should be connected simultaneously with the output of door IC5 and the input of an IC6 and IC7.
Described display control circuit is made up of row control circuit and some control circuit, the control circuit of wherein going mainly is made of 576 d type flip flops (L1-L576), the output Q of each d type flip flop Ln links to each other with the data terminal D of next d type flip flop Ln+1, the output Q of the 576th d type flip flop L576 links to each other with the data terminal D of first d type flip flop L1, the set end S of first d type flip flop L1 is connected with the output of a strange widening circuit 8, and this set end S is connected with the reset terminal R of the 289th d type flip flop L289, also be connected by the reset terminal R of diode with the 2nd～288 d type flip flop L2～288 and the 290th～576 d type flip flop L290～576, the set end of the 289th d type flip flop is connected with an idol widening circuit 9, and this set end S is connected with the reset terminal R of the 1st d type flip flop L1, also is connected by the reset terminal R of diode with the 2nd～288 d type flip flop L2～288 and the 290th～576 d type flip flop L290～576.The clock end of each d type flip flop is connected with the output Q of the 768th d type flip flop C768 in the some control circuit.The output Q of preceding 288 d type flip flop L1～288 in above-mentioned 576 d type flip flops respectively by the MOS switching tube successively with the corresponding connection of odd-numbered line light-emitting component in the display screen 5, the output Q of back 288 d type flip flop L289～576 pass through respectively the MOS switching tube successively with the corresponding connection of even number line light-emitting component in the display screen 5.
Described some control circuit mainly is made of 768 d type flip flop C1～768, the output Q of each d type flip flop Cn links to each other with the data terminal D of next d type flip flop Cn+1, the output Q of the 768th d type flip flop C768 is connected with the data terminal of first d type flip flop C1, and be connected with the clock end of each d type flip flop L1～576 in the row control circuit, the set end S of first d type flip flop C1 is connected with the output of a strange widening circuit 8, and this set end S is connected with the reset terminal R of the 385th d type flip flop C385, also be connected with the reset terminal R of the 386th～768 d type flip flop with the 2nd～384 by diode, the set end S of the 385th d type flip flop is connected with an idol widening circuit 9, and this set end S is connected with the reset terminal R of first d type flip flop C1, also is connected by the reset terminal R of diode with the 2nd～384 d type flip flop and the 386th～768 d type flip flop.The clock end of each d type flip flop and natural frequency are that the output of the read clock circuit 7 of 14.71MHz is connected.The output of each d type flip flop is connected with each row luminescent device in the display screen 5 successively by the MOS switching tube respectively.The set end S of first d type flip flop in described some control circuit also is connected the control end of read clock circuit and the output of sync stretch circuit 10 simultaneously.
For guaranteeing when the converted channel, the clock pulse of foregoing circuit keeps synchronously with the new TV signal of advancing of switching, and the parity field image sequence carries out, the present invention can also comprise and changes frequency control circuit, this changes frequency control circuit and is connected with the reset terminal R of the second d type flip flop IC2 with the first d type flip flop IC1, is used for feeding during channel switch the reset signal of a high level.After channel switch was finished, entire circuit began operate as normal again.
The display that is used with the present invention should adopt array-type display, it is arranged with array way by electrooptic cell and constitutes, the electrooptic cell that is adopted should have linear characteristic, i.e. its brightness should be directly proportional with electric current, and comparatively desirable array-type display has LCD etc. at present.
The invention has the advantages that to make array-type display reproduce TV image, help realizing the ultrathin television receiver of large-screen.
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1: circuit theory diagrams of the present invention
Fig. 2: the circuit diagram of parity field split circuit among the present invention
Fig. 3: the circuit diagram of display control circuit among the present invention
Fig. 4: the circuit diagram of the widening circuit that uses among the present invention
Fig. 5: the circuit diagram of the clock circuit that uses among the present invention
Fig. 6: the oscillogram of each several part in the present embodiment
Embodiment: present embodiment is described to be a kind of synchronous display control circuit that is used for monochromatic pattern displaying, mainly by parity field split circuit 1, display control circuit 6, reference clock pulse generator 2, read clock circuit 7 and strange field pulse widening circuit 8, idol field pulse widening circuit 9, sync stretch circuit 10 is formed, wherein reference clock pulse generator 2 is connected with original range separation circuit 3 in the television set by the Q end of the first d type flip flop IC1, the output that the clock drive end of this first d type flip flop IC1 and input D are connected range separation circuit 3 simultaneously, the Q output of this first d type flip flop IC1 is connected with the control end Vk of described reference clock pulse generator 2, the output of original range separation circuit 3 and reference clock pulse generator 2 is connected in parity field split circuit 1 and the television set, parity field split circuit 1 has strange field signal output a and even field signal output b, wherein strange field signal output a is connected with strange field pulse widening circuit 8 by P type the 3rd MOS switching tube K3, simultaneously strange field signal output a also is connected clock drive end and the input D of the second d type flip flop IC2, described even field signal output b is connected with even field pulse widening circuit 9 with P type the 4th MOS switching tube K4 by N type the 2nd MOS switching tube K2, wherein the control end of the 2nd MOS switching tube K2 is connected on the output Q of the described second d type flip flop IC2, and the 4th MOS switching tube K4 is connected between the 2nd MOS switching tube K2 and the even field pulse widening circuit 9.The output of above-mentioned strange field pulse widening circuit 8 and even field pulse widening circuit 9 is connected on the display control circuit 6 simultaneously, simultaneously, the output of strange field pulse exhibition circuit 8 and the conducting control connection of the 4th MOS switching tube K4, the output of even field pulse widening circuit 9 is connected with the conducting control end of the 3rd MOS switching tube K3.Described sync stretch circuit 10 is connected on the output of range separation circuit 3, this sync stretch circuit 10 is connected with display control circuit 6, and described read clock circuit 7 is connected between the output and display control circuit 6 of sync stretch circuit 10.The display unit of using that cooperatively interacts with it is single colour liquid crystal display, according to China's secam television signal and TV image resolution, the display screen 5 that is adopted in this example is single colour liquid crystal display, have 576 row * 768 a row luminous point, in the accompanying drawing 3, each luminous point is represented with light-emitting diode, the negative electrode of every row luminous point connects together, and respectively by a N type MOS switching tube ground connection, the anode of every capable luminous point links together, and puts output circuit and be connected by original looking in a N type MOS switching tube and the television set respectively.
Above-mentioned parity field split circuit 1 is mainly by stretch circuit 11, big register and little register and two with an IC6, IC7 forms, these two and a door IC7, the output of IC6 is respectively as a strange output a and an idol output b, described big register is connected in sequence by 16 d type flip flop B1～B16, the Q end of each d type flip flop Bn links to each other with the D end of next d type flip flop Bn-1, and the D of the 16th d type flip flop B16 end is as the input of this big register, this input is connected with original range separation circuit 3 in the television set by described stretch circuit 11, the Q end of the second d type flip flop B2 and the 14th d type flip flop B14 is respectively by non-gate device IC9 in the big register, IC8 is connected input above-mentioned and door IC6 and IC7 simultaneously, the Q end of the 13rd d type flip flop B13 is connected the input with door IC6 and IC7 simultaneously, the Q of first d type flip flop B1 end is connected with input with door IC6, and the Q of the first d type flip flop B1 holds and passes through not gate device IC10 and be connected with input with door IC7.Described little register by the 3rd, four d flip-flop IC3, IC4 and form with door IC5, wherein the D of 3d flip-flop IC3 end is connected with original range separation circuit 3 in the television set, and the Q of 3d flip-flop IC3 end is connected with the D end of the 14th d type flip flop IC4, three, the Q of the 4th trigger IC3, IC4 end is connected simultaneously with the input of door IC5 and is connected, and should be connected the input with door IC6 and IC7 with the output of door IC5 simultaneously.
Above-mentioned widening circuit 11 can adopt NOR gate monostable flipflop or other existing stretch circuit form, and each used in this example widening circuit is the NOR gate monostable flipflop, as shown in Figure 4.
In this example the structure of each clock circuit as shown in Figure 5, wherein the clock cycle of reference clock pulse generator 2 is 16us, the high level width is 8us, its signal output part is connected with the clock drive end of each d type flip flop in the large and small register simultaneously.
The working condition of above-mentioned parity field split circuit 1 is, the lock-out pulse of sending here from range separation circuit, the high level width of leading Eq pulse be 4.7us and 2.35us only, shown in a1, a2 and a5 among Fig. 6, at this moment, the preceding half cycle of clock pulse is a low level, and this low level width is 8us, and the second half high level of clock pulse is when arriving, the high level of lock-out pulse misses, little register output low level.When field system chronizing impulse arrives, because the high level width of per 1/6 field system chronizing impulse is 27.3us, during this period, must there be the rising edge of two clock pulse high level to arrive, make and door IC5 output high level.When little register is done above-mentioned work, range separation circuit 3 is through the wide ripple signal of pulse widening circuit 11 to big register output 16us, as shown in Figure 6, under the driving of clock pulse, these signals enter each d type flip flop successively, make the Q output of each d type flip flop B1～B16 have corresponding state, along with width of cloth split circuit output signal do not stop change, the Q end of each d type flip flop also changes by same rule, when field system chronizing impulse arrives, the state of each d type flip flop is: the 3rd to the tenth four d flip-flop B3～B14 is corresponding with leading Eq pulse, and first, second d type flip flop B1～B2 is corresponding with the signal of the preceding 32us of leading Eq pulse.Owing to be spaced apart 64us between strange leading Eq pulse and last horizontal synchronizing pulse of its place ahead, and be spaced apart 32us between the leading Eq pulse of idol field and last horizontal synchronizing pulse of its place ahead, as a1 among Fig. 6, a2.So, as shown in Figure 2, when an idol field system chronizing impulse arrives, little register is output as high level, the output of trigger B1 and trigger B13 is high level in the simultaneously big register, and output is low level when trigger B2, B14, respectively through not gate IC8, IC9 upset becoming high level, so with door IC6 output high level, promptly the idol of a parity field split circuit output b is a high level.When strange field system chronizing impulse arrives, little register is output as high level, trigger B13 is output as high level in the simultaneously big register, the output of trigger B1, B2, B14 is low level, respectively through not gate IC8, IC9, IC10 upset becoming high level, so with door IC7 output high level, promptly strange output a of parity field split circuit is high level.Referring to Fig. 1, if first field system chronizing impulse of start back is even field system chronizing impulse, though the idol of a split circuit output b is high level, owing to be connected to the second metal-oxide-semiconductor K2 on this end, and its control end does not obtain high level continuity signal as yet, so K2 is in off state, this idol field signal can not enter subsequent conditioning circuit, and first strange field system chronizing impulse arrives until the start back.Strange output of parity field split circuit is high level, and after the second d type flip flop IC2 started the second metal-oxide-semiconductor K2, an idol output was just connected with other circuit.An above-mentioned strange output and an idol output are connected with a strange widening circuit 8 and an idol field widening circuit 9 respectively, are 1.3827ms with its signal broadening of exporting, and the pulse back edge behind the broadening is alignd with edge after the blanking level.
Described display control circuit 6 is made up of row control circuit and some control circuit, the control circuit of wherein going mainly is made of 576 d type flip flops, the output Q of each d type flip flop Ln links to each other with the data terminal D of next d type flip flop Ln+1, the output Q of the 576th d type flip flop L576 links to each other with the data terminal D of first d type flip flop L1, the set end S of first d type flip flop L1 is connected with the output of a strange widening circuit 8, and this set end S is connected with the reset terminal R of the 289th d type flip flop L289, also be connected by the reset terminal R of diode with 2-288 d type flip flop L2-288 and 290-576 d type flip flop L290-576, the set end S of the 289th d type flip flop L289 is connected with an idol widening circuit 9, and this set end S is connected with the reset terminal R of first d type flip flop L1, also is connected by the reset terminal R of diode with 2-288 d type flip flop L2-288 and 290-576 d type flip flop L290-576.The clock end of each d type flip flop is connected with the output Q of the 768th d type flip flop C768 in the some control circuit.The output Q of preceding 288 d type flip flop L1-288 in above-mentioned 576 d type flip flops respectively by corresponding M OS switching tube successively with display screen 5 in the corresponding connection of each even number line light-emitting component, the output Q of back 288 d type flip flop L289-576 pass through respectively corresponding M OS switching tube successively with the corresponding connection of odd-numbered line light-emitting component in the display screen 5.Described some control circuit mainly is made of 768 d type flip flop C1-768, the output Q of each d type flip flop Cn links to each other with the data terminal D of next d type flip flop Cn+1, the output Q of the 768th d type flip flop C768 is connected with the data terminal of first d type flip flop C1, and be connected with the clock end of each d type flip flop L1-576 in the row control circuit, the set end S of first d type flip flop C1 is connected with the output of a strange widening circuit 8, and this set end S is connected with the reset terminal R of the 385th d type flip flop C385, also be connected with the reset terminal R of 386-768 d type flip flop with 2-384 by diode, the set end S of the 385th d type flip flop is connected with an idol widening circuit 9, and this set end S is connected with the reset terminal R of first d type flip flop C1, also is connected with the reset terminal R of 386-768 d type flip flop with 2-384 by diode.The clock end of each d type flip flop and natural frequency are that the output of the read clock circuit 7 of 14.71MHZ is connected.The output of each d type flip flop is connected with each row light-emitting component in the display screen 5 successively by corresponding M OS switching tube respectively.The set end S of first d type flip flop in described some control circuit also is connected the control end of read clock circuit simultaneously.
The course of work of this routine described circuit is: after the start, first synchronization pulse by original range separation circuit output in the television set triggers the first d type flip flop IC1, by its Q end output low level signal enabling reference clock, make the clock pulse and the synchronization pulse of its output synchronous, referring to a1, a6 among Fig. 6.Meanwhile, after entering a split circuit 1, the synchronization pulse of range separation circuit 3 outputs is divided into two-way, one the tunnel through pulse widening circuit 11 broadenings behind 16us, enter in the middle of the big register of forming by 16 d type flip flops, the output state of big register will change according to synchronization pulse.Another road then enters little register, and when field system chronizing impulse arrived, little register output high level was according to the output state of big register this moment, a field sync signal is exported in one of strange output a that must meeting-place split circuit 1 or idol output b conducting.If what at first arrive after the start is even field system chronizing impulse, because N type the 2nd MOS switching tube K2 not conducting as yet this moment, this signal can not be delivered in the subsequent conditioning circuit, when treating that first strange field sync signal arrives, strange output a output pulse signal of field split circuit is to a strange widening circuit 8, trigger the second d type flip flop IC2 simultaneously, make its output Q locking high level, the 2nd MOS switching tube K2 keeps conducting state.Above-mentioned strange field signal enters in strange the widening circuit, and is broadened to 1.3827ms, delivers to display control circuit, simultaneously, makes P type the 4th MOS switching tube K4 get electric shutoff, to guarantee in the strange field signal output procedure that the idol field is output signal not.When an idol field sync signal arrives next time, because switching tube K2 conducting, the output signal of an idol output b promptly can normally enter an idol widening circuit 9, above-mentioned even field signal enters in idol the widening circuit 9 broadening to 1.3827ms, deliver to display control circuit, simultaneously, make P type the 3rd MOS switching tube K3 get electric shutoff, to guarantee in the even field signal output procedure that strange field is output signal not.Aforesaid execution result is, during every 40ms in, must have a strange field signal and an even field signal to be sent to display control circuit on time.First horizontal synchronizing pulse after the start will be put control circuit through widening circuit 10 broadenings to the 10.5us and will be changed to initial condition, after the high level, read clock starts, the point control circuit is started working under clock drives, but this moment, the row control circuit did not start as yet usually, display screen can not be worked, when first strange field system chronizing impulse arrives by the time, again will put control circuit and be changed to initial condition, and will go control circuit and be changed to initial condition, then under the driving of read clock 7, the point control circuit is started working, wherein 768 d type flip flops power on successively, and the output high level makes corresponding switching tube conducting, at this moment first d type flip flop L1 is output as high level in the capable control circuit, corresponding switching tube conducting, so frequency conducting successively that the second row luminous point is pressed read clock, when the 768th d type flip flop in the control circuit powers on and exports high level, this signal not only is used for the corresponding columns of light elements of driving switch pipe conducting, and drive the corresponding switching tube of row control circuit utilization as the clock signal of row control circuit and cut off the second row light-emitting component, the fourth line of conducting simultaneously light-emitting component is so begin to scan fourth line.And the like, 1-288 d type flip flop is triggered successively, the output high level, and the corresponding switching tube of conducting is capable, scans all even number lines successively, and after the 288th d type flip flop was triggered and scans the 576th row of screen, even number line scanning was finished.Even subsequently field signal arrives, and the 289th d type flip flop is changed to high level, scans all odd-numbered lines since first row, and the interlacing that can finish two field pattern elephants shows.In the scanning process, each constantly must have a light-emitting component conducting, and the output signal of video amplifier circuit 4 shows with brightness at this point, promptly can form the demonstration of TV image.
Owing to have blanking interval in the existing TV signal, this blanking interval can cause the display periphery black line to occur, though this does not influence image quality, but it must be a defective unexpectedly, for avoiding above-mentioned situation to occur, can cut off getting in touch between the output Q of the 1st, 576 row light-emitting components and corresponding d type flip flop L288, L289 in the display 5, promptly be not connected with corresponding M OS switching tube, perhaps, can omit correspondingly the MOS switching tube and display on correspondingly light-emitting component.In like manner, can cut off getting in touch between the wet output Q that shows the 1st, 768 row light-emitting components and corresponding d type flip flop C1, C768 in the device, omit perhaps that corresponding M OS manages and display on correspondingly light-emitting component.
That is adopted in the present embodiment changes frequency control circuit as shown in Figure 1, its circuit is that the reset terminal R of first, second d type flip flop IC1, IC2 is connected with power supply ED by P type the one MOS switching tube K1 simultaneously, the control end of the one MOS switching tube K1 is connected with three lead-out terminal BL, BH, BU of original channel preselection device 12 on the television set simultaneously, go into for preventing that voltage is contrary, these three outputs respectively are provided with an isolating diode.During converted channel, do not pressed on earth as yet at the new channel button, when former button has been upspring, these three output BL, BH, the equal output low level of BU make a MOS switching tube K1 conducting, send reset signal by power supply ED to first and second d type flip flop IC1, IC2, after new channel key is effectively connected, an output high level must be arranged in above-mentioned three outputs, switching tube K1 is ended, entire circuit begins again to rework.
Claims (3)
1, a kind of synchronous display control circuit, comprise display control circuit (6) and read clock circuit (7), it is characterized in that it also comprises parity field split circuit (1), reference clock pulse generator (2), with strange field pulse widening circuit (8), idol field pulse widening circuit (9), sync stretch circuit (10) is formed, wherein said reference clock pulse generator (2) is connected with original range separation circuit (3) in the television set by the Q end of first d type flip flop (IC1), parity field split circuit (1) is connected with the output of range separation circuit (3) with reference clock pulse generator (2), this parity field split circuit (1) has strange field signal output (a) and even field signal output (b), wherein strange field signal output (a) is connected with strange field pulse widening circuit (8) by the 3rd MOS switching tube (K3), simultaneously strange field signal output (a) also is connected the clock drive end and the input D of second d type flip flop (IC2), described even field signal output (b) is by second, the 4th MOS switching tube (K2, K4) be connected with even field pulse widening circuit (9), wherein the control end of the 2nd MOS switching tube (K2) is connected on the output Q of described second d type flip flop (IC2), the 4th MOS switching tube (K4) is connected between the 2nd MOS switching tube (K2) and the even field pulse widening circuit (9), the output of above-mentioned strange field pulse widening circuit (8) and even field pulse widening circuit (9) is connected on the display control circuit (6) simultaneously, and, the output of strange field pulse widening circuit (8) is connected with the conducting control end of the 4th MOS switching tube (K4), the output of idol field pulse widening circuit (9) is connected with the conducting control end of the 3rd MOS switching tube (K3), described sync stretch circuit (10) is connected between range separation circuit (3) and the display control circuit (6), described read clock circuit (7) is connected between the output and display control circuit (6) of sync stretch circuit (10), and original looking put output circuit (4) and be connected simultaneously on the display (5) on described display control circuit (6) and the television set;
Above-mentioned parity field split circuit (1) is mainly by stretch circuit (11), big register, little register and the 6th, the 7th and a door (IC6, IC7) form, wherein big register is by 16 d type flip flop (B1～B16) be connected in sequence, the Q end of each d type flip flop (Bn) links to each other with the D end of next d type flip flop (Bn-1), the D end of the 16th d type flip flop (B16) is connected with original range separation circuit (3) in the television set by described stretch circuit (11), in the big register the 1st, 2,13,14 d type flip flop (B1, B2, B13, B14) Q end is connected with the input of door (IC6) with the 6th, described little register is by the 3rd in described 16 d type flip flops, four d flip-flop (IC3, IC4) and the 5th form with door (IC5), the D end of wherein said 3d flip-flop (IC3) is connected with original range separation circuit (3) in the television set, and its Q end is connected with the D end of described four d flip-flop (IC4), the described the 3rd, four d flip-flop (IC3, IC4) Q end be connected simultaneously the described the 5th with the input of door (IC5), the 5th is connected the described the 6th simultaneously with the output of door (IC5), the 7th with the door (an IC6, IC7) input;
Described display control circuit (6) is made up of row control circuit and some control circuit, the control circuit of wherein going mainly is made of 576 d type flip flops (L1～576), the output Q of each d type flip flop (Ln) links to each other with the data terminal D of next d type flip flop (Ln+1), the output Q of the 576th d type flip flop (L576) in described 576 d type flip flops links to each other with the data terminal D of first d type flip flop (L1) wherein, the set end S of first d type flip flop (L1) in the described capable control circuit is connected with the output of strange widening circuit (8), and the reset terminal R of the 289th d type flip flop (L289) in this set end S and described 576 d type flip flops is connected, also be connected by the 2nd～288 d type flip flop (L2～288) in diode and the described capable control circuit and the reset terminal R of the 290th～576 d type flip flop (L290～576), the set end of described the 289th d type flip flop (L289) is connected with an idol widening circuit (9), and this set end S is connected with the reset terminal R of the 1st d type flip flop (L1) in the described capable control circuit, also be connected with the reset terminal R of described the 2nd～288 d type flip flop (L2～288) with the 290th～576 d type flip flop (L290～576) by diode, the clock end of this each d type flip flop of circuit is connected with the output Q of the 768th d type flip flop (C768) in the some control circuit, the output Q of preceding 288 d type flip flops (L1～288) in above-mentioned 576 d type flip flops respectively by N type MOS switching tube successively with display screen (5) in the corresponding connection of even number line light-emitting component, in this circuit the output Q of back 288 d type flip flops (L289～576) pass through respectively N type MOS switching tube successively with display screen (5) in the corresponding connection of odd-numbered line light-emitting component;
Described some control circuit mainly is made of 768 d type flip flops (C1～768), the output Q of each d type flip flop (Cn) links to each other with the data terminal D of next d type flip flop (Cn+1), the output Q of the 768th d type flip flop (C768) links to each other with the data terminal D of first d type flip flop (C1) wherein in described some control circuit, and be connected with the clock end of row each d type flip flop (L1～576) in the control circuit, the set end S of first d type flip flop (C1) is connected with the output of strange widening circuit (8) in described some control circuit, and this set end S is connected with the reset terminal R of the 385th d type flip flop (C385) in the described some control circuit, also by in diode and the described some control circuit the 2nd～384 be connected with the reset terminal R of the 386th～768 d type flip flop, the set end S of the 385th d type flip flop (C385) is connected with an idol widening circuit (9) in described some control circuit, and this set end S is connected with the reset terminal R of the 1st d type flip flop (C1) in the described some control circuit, also be connected with the reset terminal R of the 386th～768 d type flip flop of the 2nd～384 d type flip flop (C2～384) and this circuit (C386～768) in the described some control circuit by diode, the clock end of above-mentioned each d type flip flop is connected with the output of read clock circuit (7), the output of above-mentioned each d type flip flop is connected with each row luminescent device in the display screen (5) successively by the MOS switching tube respectively, and the set end S of first d type flip flop in described some control circuit also is connected the control end of read clock circuit and the output of sync stretch circuit (10) simultaneously.
2, synchronous display control circuit as claimed in claim 1, its spy is that it comprises and changes frequency control circuit, the described frequency control circuit that changes is connected with the reset terminal R of described first and second d type flip flop (IC1, IC2), is used for providing during channel switch the reset signal of a high level.
3, synchronous display control circuit as claimed in claim 2, its spy is that the described frequency control circuit that changes is that the reset terminal R of first and second d type flip flop (IC1, IC2) is connected with power supply (ED) by a P type the one MOS switching tube (K1) simultaneously, the control end of this P type the one MOS switching tube (K1) is connected with three lead-out terminals (BL, BH, BU) of original channel preselection device (12) on the television set simultaneously, go into for preventing that voltage is contrary, these three outputs respectively are provided with an isolating diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95119101A CN1058824C (en) | 1995-08-18 | 1995-11-16 | Synchronous display control circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95108892 | 1995-08-18 | ||
| CN95108892.0 | 1995-08-18 | ||
| CN95119101A CN1058824C (en) | 1995-08-18 | 1995-11-16 | Synchronous display control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1157529A CN1157529A (en) | 1997-08-20 |
| CN1058824C true CN1058824C (en) | 2000-11-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95119101A Expired - Fee Related CN1058824C (en) | 1995-08-18 | 1995-11-16 | Synchronous display control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1058824C (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2175502Y (en) * | 1993-08-07 | 1994-08-24 | 季晓勇 | Control device for multi TV picture in same screen displaying |
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1995
- 1995-11-16 CN CN95119101A patent/CN1058824C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2175502Y (en) * | 1993-08-07 | 1994-08-24 | 季晓勇 | Control device for multi TV picture in same screen displaying |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1157529A (en) | 1997-08-20 |
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