CN105869565A - Gate drive circuit - Google Patents
Gate drive circuit Download PDFInfo
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- CN105869565A CN105869565A CN201610408389.2A CN201610408389A CN105869565A CN 105869565 A CN105869565 A CN 105869565A CN 201610408389 A CN201610408389 A CN 201610408389A CN 105869565 A CN105869565 A CN 105869565A
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- 230000000087 stabilizing effect Effects 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 8
- 230000035882 stress Effects 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 230000032683 aging Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 101100205847 Mus musculus Srst gene Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000013499 data model Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention provides a gate driving circuit which comprises a driving switch, an input module, a pull-down module, a first switch, a second switch, a third switch, a capacitor and a reset switch. The driving switch is controlled by the voltage level of the first node. The input module is coupled to the first node. The pull-down module is coupled with one end of the driving switch. The first switch has two end couplings coupled to the charging signal terminal and the second node, respectively, and a control terminal coupled to the storage node. Two ends of the second switch are respectively coupled to the second reference voltage end and the third node, and the control end is coupled to the storage node. The third switch has two ends coupled to the third node and the first node, respectively, and a control end coupled to the second node. The two ends of the capacitor are respectively coupled with the storage node and the second node. Two ends of the reset switch are respectively coupled to the first node and the first reference voltage end, and the control end is coupled to the reset signal end. The desired gate driving signal is generated again after the touch sensing period, so that the elements in the gate driving circuit are prevented from being rapidly aged due to the influence of long-time bias stress.
Description
Technical field
The present invention relates to a kind of gate driver circuit, particularly relate to one after the touch detection stage to joint
Point recharges to export the gate driver circuit of gate drive signal.
Background technology
Along with the evolution of technology, panel now has often integrated display and touch controllable function, to provide
Operation interface is to user easily.In embedded (in-cell) contact panel, embedded touch face
Plate is provided with gate driver circuit and touch-control circuit, and gate drive signal line on same substrate
Each other may be very close to touching signals line, therefore gate drive signal can be done each other with touching signals
Disturb.Owing to the intensity of gate drive signal is relatively strong, by capacitance coupling effect, gate drive signal is past
Toward noise can be caused to disturb touching signals, and reduce signal to noise ratio (the signal to noise of touch control operation
ratio,SNR)。
In traditional practice, in order to avoid touching signals is disturbed by gate drive signal, typically exist
Time during the touch-control sensing of enable touch-control circuit, the several signal specific in gate driver circuit can be drawn
As little as low level, to avoid gate driver circuit to operate with touch-control circuit and interfering with each other simultaneously.But in
This simultaneously, how to allow gate driver circuit during touch-control sensing later can normal operation again, then become
The problem must thought deeply during for design gate driver circuit.On the other hand, due to gate driver circuit
Element is easily subject to long deviated stress (voltage stress) impact, grid under such framework
Element in the drive circuit of pole the most easily has aging problem.
Summary of the invention
A kind of gate driver circuit of offer is provided, remains to again after during touch-control sensing
Normal operation, and prevent the element in gate driver circuit the most aging.
Gate driver circuit disclosed in this invention, including drive switch, input module, drop-down module,
First switch, second switch, the 3rd switch, electric capacity and Resetting Switching.Drive switch according to first segment
The voltage of point optionally adjusts the voltage that voltage is clock signal driving signal, and primary nodal point quilt
Feed-in input signal.Input module couples primary nodal point, in order to according to previous stage this driving signal or
This driving signal-selectivity ground of rear stage adjusts the voltage of this input signal.Drop-down module couples drives
One end of switch, in order to optionally to drive this according to one first pulldown signal or one second pulldown signal
Dynamic switch is coupled to one first reference voltage end, to adjust the voltage of this driving signal.First switch
One end couples charging signals end, and the other end couples secondary nodal point, controls end and couples storage node.Store
Node is fed into input signal.One end of second switch couples the second reference voltage end, and the other end couples
3rd node, controls end and couples storage node.One end of 3rd switch couples the 3rd node, the other end
Couple primary nodal point, control end and couple secondary nodal point.The two ends of electric capacity are respectively coupled to storage node and
Two nodes.One end of Resetting Switching couples primary nodal point, and the other end couples the first reference voltage end, control
End processed couples reset signal end.
Another gate driver circuit disclosed in this invention, including: drive switch, input module, weight
Put switch and temporary storage module, drive switch to be controlled by the voltage quasi position of primary nodal point and optionally adjust
The voltage quasi position of whole driving signal, drives signal to be provided to outfan, and primary nodal point is fed into input
Signal；Input module couples primary nodal point, in order to according to the driving signal of previous stage or driving of rear stage
Dynamic signal-selectivity ground adjusts the voltage quasi position of input signal；The two ends of Resetting Switching are respectively coupled to first
Node and the first reference voltage end, the control end of Resetting Switching couples reset signal end；Temporary storage module coupling
Connecing primary nodal point, charging signals end and the second reference voltage end, temporary storage module has storage node；Its
In, before the touch-control sensing stage, input signal is fed into storage node and primary nodal point, in touch-control
In the sensing stage, the voltage quasi position of reset signal end is high voltage level, and primary nodal point is turned on to
One reference voltage end, storage node keeps in the voltage quasi position of input signal, after the touch-control sensing stage
The multiple charging stage in, the voltage of charging signals end is high voltage level, and the voltage of reset signal end is accurate
Position is low voltage level, and temporary storage module draws high the voltage of primary nodal point according to the voltage quasi position of storage node
Level.
Comprehensively the above, the invention provides a kind of gate driver circuit, by data voltage is pre-
Exist in a storage node, thus be able to when the touch-control sensing stage, suspend the behaviour of gate driver circuit
Make, and release the voltage of part of nodes to avoid the element can be by long deviated stress.And touching
After the control sensing stage terminates, then with the voltage stored by storage node and corresponding switch element weight
Newly corresponding node is charged.Therefore, after being allowed gate driver circuit during touch-control sensing again
The desired gate drive signal of secondary generation, and avoid the element in gate driver circuit by time long simultaneously
Between the impact of deviated stress and quick aging.
The above explanation about present disclosure and the explanation of following embodiment are in order to demonstrate and to solve
Release spirit and the principle of the present invention, and provide the patent claim of the present invention further to explain.
Accompanying drawing explanation
Fig. 1 is the function block schematic diagram according to the gate drivers depicted in one embodiment of the invention.
Fig. 2 is the electricity of a kind of embodiment according to one of them gate driver circuit depicted in Fig. 1
Road schematic diagram.
Fig. 3 is the time diagram according to the gate driver circuit depicted in Fig. 2.
Fig. 4 is the another embodiment according to one of them gate driver circuit depicted in Fig. 1
Circuit diagram.
Description of reference numerals:
1 gate drivers
10_1～10_N ..., 10_N ' gate driver circuit
120,120 ' input module
140 drop-down modules
160 Voltage stabilizing modules
C1, C2, C3 electric capacity
CK clock signal
Cha charging signals
D2U the second input signal
U2D the first input signal
G [1], G [2], G [3]～G [N-1], G [N], G [N+1] ... drive signal
NA storage node
NB secondary nodal point
NC the 3rd node
NG outfan
NQ primary nodal point
P [N] the second pulldown signal
Q [N] voltage quasi position
ST [1] enabling signal
ST1 pulls up the stage
The ST2 touch-control sensing stage
The ST3 multiple charging stage
ST4 drives the stage
ST5 transition stage
The ST6 drop-down stage
Sin, Sin ', Sin " input signal
Srst reset signal
T1 first switchs
T2 second switch
T3 the 3rd switchs
T4 the 4th switchs
T5 the 5th switchs
Td drives switch
Tin1, Tin1 ', Tin3 ' the first input switch
Tin2, Tin2 ', Tin4 ' the second input switch
Tpd1, Tpd2 pull down switch
Trst Resetting Switching
Ts1, Ts2 stabilized switch
VDD the second reference voltage level
VSS the first reference voltage level
XCK the first pulldown signal
Detailed description of the invention
Hereinafter describing detailed features and the advantage of the present invention the most in detail, its content be enough to
Any relevant art of being familiar with is made to understand the technology contents of the present invention and implement according to this, and according to this explanation
Book disclosure of that, claim and accompanying drawing, any relevant art of being familiar with can be readily understood upon this
Invent relevant purpose and advantage.Below example further describes the viewpoint of the present invention, but
Non-to limit scope of the invention anyways.
Refer to Fig. 1, Fig. 1 is the function side according to the gate drivers depicted in one embodiment of the invention
Block schematic diagram.As it is shown in figure 1, gate drivers 1 includes gate driver circuit 10_1～10_N ....
Wherein, N is a positive integer more than 3.In this embodiment, gate driver circuit 10_1～10_N ...
The most sequentially concatenate, gate driver circuit 10_1～10_N ... in order to produce driving signal
G [1]～G [N] ....More specifically, gate driver circuit 10_1 according to clock signal CK with
Enabling signal ST [1] produces and drives signal G [1].Enabling signal ST [1] is art technology people
Member institute energy self-defining, is not any limitation as at this.Similarly, during gate driver circuit 10_2 foundation
Arteries and veins signal CK produces driving signal G [2] with driving signal G [1].As for gate driver circuit
10_3～10_N ... relevant start when can analogize with foregoing according to Fig. 1, then repeat no more in this.
Gate driver circuit 10_1～10_N is such as with non-crystalline silicon (Amorphous Silicon, A-Si) technique, many
Crystal silicon (Poly-Silicon) technique or low temperature silicon substrate (low-temperature silicon substrate)
Technique is made, and is not any limitation as at this.The follow-up framework with Fig. 1 illustrates for demonstration example, so
Actually gate drivers 1 may be used without a biography two or and passes the framework of three, and not with this embodiment
It is limited.
Please referring next to Fig. 2, Fig. 2 is according to one of them gate driver circuit depicted in Fig. 1
Plant the circuit diagram of embodiment.With gate driver circuit 10_N in the embodiment corresponding to Fig. 2
As a example by be introduced, structure that so remaining gate driver circuit is had and start and raster data model electricity
Road 10_N is similar, and skilled artisan is when analogizing from this specification and obtain.Such as Fig. 2 institute
Show, gate driver circuit 10_N have driving switch Td, input module 120, drop-down module 140,
First switch T1, second switch T2, the 3rd switch T3 and, electric capacity C1 and Resetting Switching Trst.
The first end driving switch Td couples clock signal end to receive clock signal CK.Drive switch
Second end of Td couples outfan NG, drives switch Td to provide optionally through outfan NG and drives
Dynamic signal G [N].The control end driving switch Td couples primary nodal point NQ, primary nodal point NQ and is presented
Enter and have input signal Si n, and primary nodal point NQ has voltage quasi position Q [N].Input module 120 couples
Primary nodal point NQ, and input module 120 receive the first input voltage U2D, the second input voltage D2U,
Driving signal G [N-1] of previous stage and driving signal G [N+1] of rear stage.Drop-down module 140 couples
Outfan NG and the first reference voltage end, drop-down module 140 receives the by the first reference voltage end
One reference voltage VSS.Voltage stabilizing module 160 couples primary nodal point NQ and the first reference voltage end, surely
Die block 160 receives the first reference voltage VSS by the first reference voltage end.Follow-up with the first reference
Voltage VSS is that low voltage level illustrates.
In one embodiment, when scanning direction be from top to bottom when, the first input voltage U2D is
High voltage level, the second input voltage D2U is low voltage level, and when scanning direction is from lower to upper
When, the first input voltage U2D is low voltage level, and the second input voltage D2U is that high voltage is accurate
Position.Described scanning direction and the first input voltage U2D and the relative size of the second input voltage D2U
System can freely define for skilled artisan, does not repeats them here.Follow-up system is with scanning
Direction is from top to bottom, and the first input voltage U2D is high voltage level and the second input voltage D2U
Embodiment for low voltage level illustrates.
One end of first switch T1 couples charging signals end to receive charging signals Cha, and first switchs T1
The other end couple secondary nodal point NB, the control end of the first switch T1 couples storage node NA.Storage
Deposit node NA and be fed into input signal Si n.Storage node NA has voltage quasi position NA, and second
Node NB has voltage quasi position B [N].One end of second switch T2 couples the second reference voltage end to connect
Receiving the second reference voltage VDD, the other end of second switch T2 couples one the 3rd node NC, and second opens
The control end closing T2 couples storage node NA.Follow-up accurate with the second reference voltage VDD for high voltage
Position illustrates.One end of 3rd switch T3 couples the 3rd node NC, the other end of the 3rd switch T3
Coupling primary nodal point NQ, the control end of the 3rd switch T3 couples secondary nodal point NB.The two of electric capacity C1
End is respectively coupled to storage node NA and secondary nodal point NB.One end of Resetting Switching Trst couples first segment
Point NQ, the other end of Resetting Switching Trst couples the first reference voltage end to receive the first reference voltage
The control end of VSS, Resetting Switching Trst couples reset signal end to receive reset signal Srst.Section three,
Point NC has voltage quasi position C [N].
Switch Td is driven optionally to adjust driving letter according to the voltage quasi position Q [N] of primary nodal point NQ
The voltage quasi position that voltage quasi position is clock signal CK [N] of number G [N].For another angle, drive
Dynamic switch Td is controlled by voltage quasi position Q [N] and optionally outfan NG is conducted to clock signal
End.In one embodiment, when voltage quasi position Q [N] is high voltage level, switch Td is driven to be led
Lead to and the voltage quasi position driving signal G [N] is adjusted to the voltage quasi position of clock signal CK [N].
Input module 120 is in order to according to driving signal G [N-1] of previous stage or the driving signal of rear stage
G [N+1] and optionally the voltage quasi position of input signal Si n is adjusted to the first input voltage U2D or
Second input voltage D2U.In the embodiment shown in Figure 2, input module 120 such as has more
One input switch Tin1 and the second input switch Tin2.One end of first input switch Tin1 receives first
Input voltage U2D, the other end of the first input switch Tin1 couples primary nodal point NQ, the first input
The end that controls of switch Tin1 receives driving signal G [N-1] of previous stage.Second input switch Tin2's
One end receives the second input voltage D2U, and the other end of the second input switch Tin2 couples primary nodal point
The end that controls of NQ, the second input switch Tin2 receives driving signal G [N+1] of rear stage.Therefore,
When driving signal G [N-1] of previous stage is high voltage level and driving signal G [N+1] of rear stage is low
During voltage quasi position, the first input switch Tin1 turns on and the second input switch Tin2 is not turned on, first segment
The voltage quasi position Q [N] of some NQ is adjusted to the first input voltage U2D.Driving signal when previous stage
G [N-1] is low voltage level and time driving signal G [N+1] of rear stage is high voltage level, and first is defeated
Enter to switch Tin1 to be not turned on and the second input switch Tin2 conducting, the voltage quasi position of primary nodal point NQ
Q [N] is adjusted to the second input voltage D2U.
Drop-down module 140 is in order to select according to the first pulldown signal XCK or the second pulldown signal P [N]
Property ground outfan NG is coupled to the first reference voltage end, optionally will drive signal G's [N]
Voltage quasi position is adjusted to the first reference voltage VSS.Wherein, the first pulldown signal XCK is the most reverse
Clock signal CK, in the second pulldown signal P [N] for example, gate driver circuit 10_N some joint
The voltage quasi position of point or can also be the driving signal of an outside, at this with the second pulldown signal P [N]
For gate driver circuit 10_N illustrates as a example by the voltage quasi position of one node.Above are only citing to show
Model, is the most all not limited.As it can be seen, drop-down module 140 such as have the Tpd1 that pulls down switch,
Tpd2.The pull down switch two ends of Tpd1 are respectively coupled to outfan NG and the first reference voltage end, drop-down
The control end of switch Tpd1 receives the first pulldown signal XCK.Pull down switch the two ends respectively coupling of Tpd2
Connecing outfan NG and the first reference voltage end, the control end of the Tpd2 that pulls down switch receives the second drop-down letter
Number P [N].When one of them of the first pulldown signal XCK and the second pulldown signal P [N] is high voltage
During level, pull down switch Tpd1, Tpd2 are turned on accordingly, so that outfan NG is coupled to first
Reference voltage end.
Additionally, in the middle of the embodiment shown in Fig. 2, gate driver circuit 10_N has more electric capacity C2
With the 4th switch T4.The two ends of electric capacity C2 are respectively coupled to the one end driving switch Td and drive switch
The control end of Td, to form a coupling path.The two ends of the 4th switch T4 are coupled to primary nodal point NQ
And between storage node NA, the control end of the 4th switch T4 receives the first pulldown signal XCK.The
Input signal Si n is optionally fed into storage according to the first pulldown signal XCK by four switch T4
Node NA.In this embodiment, when the first pulldown signal XCK is high voltage level, the 4th opens
Close T4 to be switched on and input signal Si n is fed into storage node NA.In other examples,
Input signal Si n can be to be fed in a different manner in storage node NA, lifts it again after please holding
His example explanation.
For asking narration simple and clear, define as the above-mentioned and follow-up high voltage level mentioned is at this is high electric
Pressure level VH, and to define above-mentioned low voltage level be same low voltage level VL.But, in
In practice, above-mentioned each signal can be respectively provided with different high voltage level or different low-voltages
Level, this can freely design for skilled artisan, not be any limitation as at this.
Please with reference to Fig. 3 with explanation gate driver circuit make flowing mode, Fig. 3 is for according to Fig. 2 institute
The time diagram of the gate driver circuit illustrated.As it is shown on figure 3, the one of gate driver circuit 10_N
Be defined in during individual operation pull-up stage ST1, touch-control sensing stage ST2, multiple charging stage ST3,
Driving stage ST4, transition stage ST5 and drop-down stage ST6.Wherein, as gate driver circuit 10_N
When affiliated contact panel carries out touch-control sensing, gate driver circuit 10_N just can enter touch-control sensing rank
Section ST2, and followed by entering multiple charging stage ST3, and sequentially enter driving stage ST4, transition rank
Section ST5 and drop-down stage ST6.And when the contact panel belonging to gate driver circuit 10_N touches
During control sensing, gate driver circuit 10_N sequentially enter pull-up stage ST1, multiple charging stage ST3,
Driving stage ST4, transition stage ST5 and drop-down stage ST6.Follow-up with gate driver circuit 10_N
Belonging to contact panel carry out the mode of operation of touch-control sensing as a example by illustrate.
In pull-up stage ST1, driving signal G [N-1] of previous stage and the first pulldown signal XCK
For high voltage level VH.Now, the first input switch Tin1, first switch T1, second switch T2,
4th switch T4, driving switch Td and the Tpd1 that pulls down switch are switched on.Accordingly, input signal Si n
Voltage quasi position be adjusted to the first input voltage U2D, and input signal Si n is fed into first segment
Point NQ and storage node NA so that the voltage quasi position Q [N] and storage node NA of primary nodal point NQ
Voltage quasi position A [N] be close to identical.The voltage quasi position B [N] of secondary nodal point NB is low voltage level
VL.The voltage quasi position C [N] of the 3rd node NC is high voltage level VH.And outfan NG is by coupling
Being connected to the first reference voltage end, therefore driving signal G [N] is low voltage level VL.Wherein, second
The voltage quasi position of three end points of switch T2 is all very close to high voltage level VH or be equal to high electricity
Pressure level VH, therefore second switch T2 is less biased against the impact of stress in this stage, the most unlikely
Charging ability originally is still possessed in rapid degradation.Flowing mode is made according to above-mentioned, the first switch T1,
Second switch T2 and the 3rd switch T3 also can be defined as a temporary storage module, in order to temporarily to store input
The voltage quasi position of signal Sin storage node NA in temporary storage module.
In one embodiment, each node voltage quasi position in time pulling up stage ST1 can be expressed as follows:
Q [N]=VH-VTH_Tin1
G [N]=VL
A [N]=VH-VTH_Tin1
B [N]=VL
C [N]=VH-VTH_Tin1-VTH_T2
Wherein, VTH_Tin1 is the conducting voltage of the first input switch Tin1, and VTH_T2 is second
The conducting voltage of switch T2.
In touch-control sensing stage ST2, the contact panel belonging to gate driver circuit 10_N carries out touch-control
Sensing, reset signal Srst is pulled to high voltage level VH, and other signals that Fig. 3 illustrates are then for low
Voltage quasi position VL.Now, Resetting Switching Trst is switched on, and primary nodal point NQ is coupled to the first ginseng
Examining voltage end, voltage quasi position Q [N] is pulled low accordingly as low voltage level VL, driving signal G [N]
Also it is low voltage level VL.And owing to storage node NA keeps in the voltage quasi position of input signal Si n,
First switch T1 is also turned on second switch T2.The voltage quasi position of remaining node above-mentioned is the most generally
Remain unchanged.In one embodiment, time span for example, 200 microsecond of touch-control sensing stage ST2
(micro second, μ s) and the length in relatively other stages, but owing to voltage quasi position Q [N] is in this stage
In be pulled low, and prevented from driving switch Td to be biased the impact of stress the most for a long time.
In one embodiment, each node voltage quasi position when touch-control sensing stage ST2 can be expressed as follows:
Q [N]=VL
G [N]=VL
A [N]=VH-VTH_Tin1
B [N]=VL
C [N]=VH-VTH_Tin1-VTH_T2
In multiple charging stage ST3, charging signals Cha is high voltage level, and its that Fig. 3 illustrates
His signal is then low voltage level VL.Now, the first switch T1, second switch T2, the 3rd switch
T3 is switched on.Accordingly, the voltage quasi position Q [N] of primary nodal point NQ is driven high as high voltage level
VH and make drive switch Td be switched on.In other words, although voltage quasi position Q [N] is at touch-control sensing
Stage, ST2 was pulled low, but by above-mentioned sequential operation, and be able to by the first switch T1, the
Two switch T2, the 3rd switch T3 and storage node NA voltage quasi position A [N] again by voltage quasi position
Q [n] adjusts to of a relatively high voltage quasi position, and situation when being generally returned to pull-up stage ST1.
For the considering of circuit design, second switch T2 and the 3rd switch T3 is to primary nodal point NQ
Charging ability can be designed to similar in the first input switch Tin1 charging energy to primary nodal point NQ
Power.As earlier mentioned, answered by bias for a long time owing to second switch T2 and the 3rd switch T3 is avoided that
Power affects and possesses charging ability originally, therefore, although gate driver circuit 10_N is in the pull-up stage
ST1 and multiple charging stage ST3 respectively by different charge paths to primary nodal point NQ, still can
Voltage quasi position Q [N] is pulled to similar voltage quasi position, and makes gate driver circuit 10_N either
No experience touch-control sensing stage ST2 can export consistent driving signal G [N].In a kind of definition mode
In, the 3rd switch T3 also can be considered charge switch, its two ends be respectively coupled to the second reference voltage end with
Primary nodal point NQ, when the control end of the 3rd switch T3 i.e. charge switch is coupled to charging signals
During end, primary nodal point NQ is optionally conducted to second according to charging signals Cha by the 3rd switch T3
Reference voltage end.As to how the correlative detail according to voltage quasi position Q [N] output drive signal G [N] please
See follow-up narration.In one embodiment, each node voltage quasi position when multiple charging stage ST3
Can be expressed as follows:
Q [N]=VH-VTH_T3
G [N]=VL
A [N]=VH-VTH_Tin1+ (VH-VL)
B [N]=VH
C [N]=VH
Wherein, VTH_T3 is the conducting voltage of the 3rd switch T3.
In driving stage ST4, clock signal CK is adjusted to high voltage level VH, and Fig. 3 paints
Other signals shown are then for low voltage level VL.Now, first switch T1, second switch T2 and drive
Dynamic switch Td conducting.The coupling path that the voltage quasi position of primary nodal point NQ is formed by electric capacity C2
And pushed away get Geng Gao by clock signal CK, and then driving switch Td is made stably to turn on.Accordingly, drive
Dynamic signal G [N] is high voltage level VH, and the voltage quasi position of driving signal G [N] can be close with waveform
Voltage quasi position when the display floater belonging to gate driver circuit 10_N does not carries out the touch-control sensing stage
With waveform.In one embodiment, each node is in driving voltage quasi position during stage ST4 can express such as
Under:
Q [N]=VH-VTH_T2+ (VH-VL)
G [N]=VH
A [N]=VH-VTH_Tin1
B [N]=VL
C [N]=VH-VTH_Tin1-VTH_T2
In transition stage ST5, each signal is low voltage level VL.Accordingly, signal is driven
G [N] is low voltage level VL.In one embodiment, each node voltage when transition stage ST5 is accurate
Position can be expressed as follows:
Q [N]=VH-VTH_T2
G [N]=VL
A [N]=VH-VTH_Tin1
B [N]=VL
C [N]=VH-VTH_Tin1-VTH_T2
In drop-down stage ST6, the first pulldown signal XCK and driving signal G [N+1] of rear stage
For high voltage level VH.Now, the second input switch Tin2 and the 4th switch T4 is switched on and makes
The voltage quasi position of storage node NA is adjusted to low voltage level VL.The Tpd1 that pulls down switch is switched on
And make to drive signal G [N] to be stably maintained at low voltage level VL.In one embodiment, respectively save
Point voltage quasi position when drop-down stage ST6 can be expressed as follows:
Q [N]=VL
G [N]=VL
A [N]=VL
B [N]=VL
C [N]=VH-VTH_Tin1-VTH_T2
In this embodiment, in addition to above-mentioned effect, by second switch T2 and the 3rd switch
T3 and corresponding sequential operation, must be to prevent the electric leakage to primary nodal point NQ of second reference voltage end
Stream, thus avoid making voltage quasi position Q [N] by the effect of leakage of the second reference voltage end misalignment.Additionally,
4th switch T4 may be used to charge storage node NA, it is also possible to outside during operation to storage
Node NA voltage stabilizing, and the parts number of gate driver circuit 10_N is the most more simplified.Surely
The correlative detail of pressure asks for an interview follow-up narration.In this embodiment, most switch element is a behaviour
Only it is switched on once in during work, and reduces the number of times of operation, also alleviate each switch element aging
Problem.
It is true that as in figure 2 it is shown, gate driver circuit 10_N more can have Voltage stabilizing module 160, surely
Die block 160 such as has electric capacity C3 and stabilized switch TS1, TS2.One end of electric capacity C3 couples
Clock signal end is to receive clock signal CK, and the other end of electric capacity C3 couples the one of stabilized switch TS1
End and the control end of stabilized switch TS2.The other end of stabilized switch TS1 couples the first reference voltage end
To receive the first reference voltage VSS, the control end of stabilized switch TS1 couples primary nodal point NQ to connect
Receive voltage quasi position Q [N].One end of stabilized switch TS2 couples primary nodal point NQ, stabilized switch TS2
The other end couple the first reference voltage end to receive the first reference voltage VSS.Voltage stabilizing module 160 depends on
Optionally primary nodal point NQ is turned on according to the voltage quasi position of voltage quasi position Q [N] and clock signal CK
To the first reference voltage end.By Voltage stabilizing module 160, gate driver circuit 10_N was able in the operation phase
Outside between, namely other grades gate driver circuit 10_1～10_N-1～... during start, make storage
Node NA and outfan NG maintains corresponding voltage quasi position, and then avoids each node suspension joint (floating)
Cause distortion.Storage node NA then first passes through the 4th switch T4 and is selectively coupled to first
Node NQ, then carry out further voltage stabilizing by Voltage stabilizing module 160.
Please referring next to Fig. 4, Fig. 4 is another according to one of them gate driver circuit depicted in Fig. 1
A kind of circuit diagram of embodiment.In the embodiment shown in fig. 4, gate driver circuit 10_N '
Structure with to make flowing mode generally similar, in this no longer with the gate driver circuit 10_N shown in Fig. 2
Repeat.Unlike the embodiment corresponding to Fig. 2, in the embodiment shown in fig. 4, input mould
Block 120 ' has multiple first input switch and multiple second input switches, namely the first input switch
Tin1 ', Tin3 ' and the second input switch Tin2 ', Tin4 '.Additionally, the embodiment shown in Fig. 4 is not
There is the 4th switch T4 and there is the 5th switch T5.
First input switch Tin1 ' and the second input switch Tin2 ' couple relation relative to other elements
Similar the first input switch Tin1 in Fig. 2 and the second input switch Tin2, repeats no more in this.
And the two ends of the first input switch Tin3 ' are respectively coupled to storage node NA and the first input voltage U2D,
The end that controls of the first input switch Tin3 ' receives driving signal G [N-1] having previous stage.Second input is opened
The two ends closing Tin4 ' are respectively coupled to storage node NA and the second input voltage D2U, and the second input is opened
The end that controls closing Tin4 ' receives driving signal G [N+1] having rear stage.The two ends of the 5th switch T5 are divided
Not coupling storage node NA and the first reference voltage end, the control end of the 5th switch T5 then couples second
Pulldown signal P [N].
In this embodiment, input module 120 ' in order to according to previous stage driving signal G [N-1], after
Driving signal G [N+1] of one-level, the first input voltage U2D and the second input voltage D2U, to carry
For input signal Si n ' primary nodal point NQ, and offer input signal Si n are provided " give storage node NA, from
And optionally adjust voltage quasi position Q [N] and voltage quasi position A [N].Input signal Si n " have and input
The voltage quasi position that signal Sin ' is similar, the most in the embodiment shown in fig. 4, voltage quasi position Q [N] with
Voltage quasi position A [N] also can be adjusted to similar voltage quasi position in pull-up stage ST1.Follow-up phase
Close details it has been observed that repeat no more in this.
In this embodiment, the second pulldown signal P [N] is the voltage of a node in Voltage stabilizing module 160
Level.But as earlier mentioned, the second pulldown signal P [N] can also be an external signal.And it is real with regard to this
For executing example, when gate driver circuit 10_N during operation outside, namely at the grid of other grades
Drive circuit 10_1～10_N-1～... during start, storage node NA be able to by the 5th switch T5 coupling
It is connected to the first reference voltage end, and makes voltage quasi position A [N] for holding low voltage level VL, it is to avoid store
Node NA suspension joint and have influence on drive signal G [N] voltage quasi position.On the other hand, in this embodiment
In, each switch element during an operation in only switched on once and reduce the number of times of operation,
Also the problem that each switch element is aging is alleviated.
Comprehensively the above, the invention provides a kind of gate driver circuit, by data voltage is pre-
Exist in a storage node, thus be able to when the touch-control sensing stage, except suspending gate driver circuit
Operation outside, also release the voltage of at least one node to avoid the element can should by bias for a long time
Power affects and deteriorates, and then possesses the charging ability of each switch.On the other hand, in the touch-control sensing stage
After end, then drive corresponding switch with again to corresponding joint with the voltage stored by storage node
Point charging, to produce the driving signal consistent with expection.Therefore, it is able to integrating touch controllable function in aobvious
While showing panel, gate driver circuit is allowed to be independent of each other as much as possible with touch-control circuit, meanwhile, more
The element being avoided that in gate driver circuit is affected and rapid degradation by long deviated stress.
Although the present invention is open as above with aforesaid embodiment, so it is not limited to the present invention.?
Without departing from the spirit and scope of the present invention, the variation done and retouching, the patent all belonging to the present invention is protected
Protect scope.The protection domain defined about the present invention refer to appended claim.
Claims (9)
1. a gate driver circuit, it is characterised in that including:
One drives switch, optionally adjusts a driving signal according to the voltage quasi position of a primary nodal point
Voltage quasi position is the voltage quasi position of a clock signal, and this primary nodal point is fed into an input signal；
One input module, couples this primary nodal point, in order to this driving signal or rear according to previous stage
This driving signal-selectivity ground of level adjusts the voltage quasi position of this input signal；
Drawing-die block once, couples one end of this driving switch, in order to according to one first pulldown signal or
This driving switch is optionally coupled to one first reference voltage end by the second pulldown signal, is somebody's turn to do to adjust
Drive the voltage quasi position of signal；
One first switch, one end of this first switch couples a charging signals end, and the other end couples one the
Two nodes, control end and couple a storage node, and this storage node is fed into this input signal；
One second switch, one end of this second switch couples one second reference voltage end, and the other end couples
One the 3rd node, controls end and couples this storage node；
One the 3rd switch, the 3rd switch one end couple the 3rd node, the other end couple this first
Node, controls end and couples this secondary nodal point；
One electric capacity, the two ends of this electric capacity are respectively coupled to this storage node and this secondary nodal point；And
One Resetting Switching, one end of this Resetting Switching couples this primary nodal point, the other end couple this first
Reference voltage end, controls end and couples a reset signal end.
2. gate driver circuit as claimed in claim 1, it is characterised in that also include that the 4th opens
Closing, one end of the 4th switch couples this storage node, and the other end couples this primary nodal point, and the 4th
This storage node is optionally coupled to this primary nodal point according to this first pulldown signal by switch.
3. gate driver circuit as claimed in claim 2, it is characterised in that this input module includes:
One first input switch, one end couples this primary nodal point, according to this driving signal choosing of previous stage
Selecting property the voltage quasi position of this primary nodal point is adjusted to one first input voltage；And
One second input switch, one end couples this primary nodal point, according to this driving signal choosing of rear stage
Selecting property the voltage quasi position of this primary nodal point is adjusted to one second input voltage.
4. gate driver circuit as claimed in claim 1, it is characterised in that this input module includes:
Multiple first input switches, wherein one end of this first input switch couples this primary nodal point,
And the voltage quasi position of this primary nodal point adjusted to one the according to this driving signal-selectivity ground of previous stage
One input voltage, wherein one end of another this first input switch couples this storage node, and according to front
The voltage quasi position of this storage node is adjusted to this first input electricity by this driving signal-selectivity ground of one-level
Pressure；And
Multiple second input switches, wherein one end of this second input switch couples this primary nodal point,
And the voltage quasi position of this primary nodal point adjusted to one the according to this driving signal-selectivity ground of rear stage
Two input voltage levels, wherein one end of another this second input switch couples this storage node, and depends on
According to rear stage this driving signal-selectivity the voltage quasi position of this storage node is adjusted to this second defeated
Enter voltage.
5. gate driver circuit as claimed in claim 4, it is characterised in that also include that the 5th opens
Closing, one end of the 5th switch couples this storage node, and the other end couples this first reference voltage end,
This storage node is optionally conducted to this first reference by the 5th switch according to this second pulldown signal
Voltage end.
6. gate driver circuit as claimed in claim 1, it is characterised in that this first pulldown signal
For this reverse clock signal.
7. gate driver circuit as claimed in claim 1, it is characterised in that also include a voltage stabilizing mould
Block, this Voltage stabilizing module couples this primary nodal point, and this Voltage stabilizing module is accurate according to the voltage of this primary nodal point
This primary nodal point is optionally conducted to this first reference voltage with the voltage quasi position of this clock signal by position
End.
8. a gate driver circuit, it is characterised in that including:
One drives switch, is controlled by the voltage quasi position of a primary nodal point and optionally adjusts a driving letter
Number voltage quasi position, this driving signal is provided to an outfan, and this primary nodal point is fed into an input
Signal；
One input module, couples this primary nodal point, in order to this driving signal or rear according to previous stage
This driving signal-selectivity ground of level adjusts the voltage quasi position of this input signal；
One Resetting Switching, two ends are respectively coupled to this primary nodal point and one first reference voltage end, this replacement
The control end of switch couples a reset signal end；
One temporary storage module, couples this primary nodal point, a charging signals end and one second reference voltage end,
This temporary storage module has a storage node；
Wherein, before a touch-control sensing stage, this input signal be fed into this storage node with this
One node, in this touch-control sensing stage, the voltage quasi position of this reset signal end is high voltage level,
This primary nodal point is turned on to this first reference voltage end, and this storage node keeps in this input signal
Voltage quasi position, in the multiple charging stage of after this touch-control sensing stage, the voltage of this charging signals end
Level is high voltage level, and the voltage quasi position of this reset signal end is low voltage level, this temporary module
The voltage quasi position of this primary nodal point is drawn high according to the voltage quasi position of this storage node.
9. gate driver circuit as claimed in claim 8, it is characterised in that this temporary storage module includes
One charge switch, the two ends of this charge switch are respectively coupled to this second reference voltage end and this primary nodal point,
In this multiple charging stage, this temporary storage module is according to voltage quasi position and this charging signals of this storage node
The control end of this charge switch is conducted to this charging signals end, with by this first segment by the voltage quasi position of end
Point is conducted to this second reference voltage end.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105105953 | 2016-02-26 | ||
| TW105105953A TWI575492B (en) | 2016-02-26 | 2016-02-26 | Gate driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105869565A true CN105869565A (en) | 2016-08-17 |
| CN105869565B CN105869565B (en) | 2019-01-04 |
Family
ID=56649388
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610408389.2A Expired - Fee Related CN105869565B (en) | 2016-02-26 | 2016-06-12 | gate drive circuit |
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| Country | Link |
|---|---|
| CN (1) | CN105869565B (en) |
| TW (1) | TWI575492B (en) |
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| CN107170411A (en) * | 2017-05-12 | 2017-09-15 | 京东方科技集团股份有限公司 | GOA unit, GOA circuits, display driver circuit and display device |
| CN107808635A (en) * | 2016-09-08 | 2018-03-16 | 联咏科技股份有限公司 | The sensing device further and method for sensing of display panel |
| CN109801602A (en) * | 2019-03-08 | 2019-05-24 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| US10453368B2 (en) | 2016-09-08 | 2019-10-22 | Novatek Microelectronics Corp. | Apparatus and method for sensing display panel |
| CN111402829A (en) * | 2020-04-10 | 2020-07-10 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN112382239A (en) * | 2020-11-05 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| TWI762286B (en) * | 2021-04-27 | 2022-04-21 | 友達光電股份有限公司 | Driving device and display |
| CN115691393A (en) * | 2022-11-14 | 2023-02-03 | 惠科股份有限公司 | Gate drive circuit and display device |
| WO2024045452A1 (en) * | 2022-08-29 | 2024-03-07 | 惠科股份有限公司 | Gate drive circuit and display apparatus |
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| CN109785786B (en) * | 2018-12-25 | 2020-09-11 | 友达光电（昆山）有限公司 | Drive circuit and touch control grid drive circuit |
| TWI688928B (en) * | 2019-01-21 | 2020-03-21 | 友達光電股份有限公司 | Gate driving circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI575492B (en) | 2017-03-21 |
| TW201730863A (en) | 2017-09-01 |
| CN105869565B (en) | 2019-01-04 |
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