CN105868150B - Lag synchronization data receiver and its method - Google Patents
Lag synchronization data receiver and its method Download PDFInfo
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- CN105868150B CN105868150B CN201610182760.8A CN201610182760A CN105868150B CN 105868150 B CN105868150 B CN 105868150B CN 201610182760 A CN201610182760 A CN 201610182760A CN 105868150 B CN105868150 B CN 105868150B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
A kind of device and method thereof of the transmission of synchronous selection pass in advance.Synchronous selection pass transmission device should be shifted to an earlier date, to compensate the misalignment on synchronous data bus, which includes a resistance circuit, a core clock generator and a synchronous gate driver.For the resistance circuit to provide a ratio signal, which indicates a lead, gates signal with a synchrodata related with a data group in advance.The core clock generator is coupled to the ratio signal, which shifts to an earlier date a data strobe timing signal with the lead.The synchronous selection pass driver generates synchrodata gating signal to receive the data strobe timing signal, and according to the data strobe timing signal, and the synchrodata gates signal in advance with the lead.
Description
This case be the applying date be on June 21st, 2012, application No. is 201210211885.0, it is entitled " same in advance
The divisional application of the application for a patent for invention of the device and method thereof of step gated transmission ".
Technical field
The present invention relates to a kind of microelectronic fields, more particularly to a kind of related to the transmission and reception of source synchronous signal
Data device and method synchronous with clock.
Background technique
Modern computer system provides the data exchange between bus agent device using a kind of source synchronous system bus,
Such as data exchange of the boundary between microprocessor and hub memory.Source synchronous bus protocol makes data can be with a high speed
Bus speed transmit.The operating principle of source synchronous agreement is that data are output in bus by a transfer bus proxy server
Continue a set time, and issues or convert one and correspond to the data-strobe signal (strobe signal) of the data to indicate
One reception bus agent device data are effective.Data signals and data-strobe signal are all logical along identical propagation path
Bus is crossed to transmit, therefore when the conversion for detecting corresponding data-strobe signal, receiver can relatively confirm that data are that have
Effect.
However data-strobe signal and data signals are easy because mistake occurs for some reasons.The source of mistake first is that when
The inaccuracy of clock generation circuit, clock generation circuit are usually phase-locked loop (phase locked loop), total to be blocked in
Data signals on line and conversion gated data indicate that the data are effective.These inaccuracy may be from design
The factor of the limit, the tolerance of manufacture or environment.In ideal conditions, gated data is the midway essence between data validity interval
It really converts, so that receiver receives the setting time of data and the retention time is equal.Relevant clock generation circuit
In inaccuracy may cause the skew (skewing) of data signals and/or data-strobe signal so that condition of acceptance is not
It is optimal.
The source of another mistake is caused by the distribution as the data-strobe signal in a reception device.Although system
Designer ensures with exhausting one's ability to gate signal and its relevant data signals are along phase on a system board (i.e. motherboard)
With transmission path transmit, however it is well known, once data-strobe signal enters reception device, must distribute to
All internal synchronization receivers related with data-strobe signal.In certain devices, additional conveying length is needed to transmit
Data-strobe signal will likely so delay the delivery time of data signals to different receivers, and then generate synchronous pass
The phase skew sent.
Therefore, compensate synchronous data bus on signal unjustified (misalignment) device and method be it is necessary to
's.
By one data strobe of adjustment and its corresponding data signals, so that the signal on synchronous bus is optimally
The technology of transmission is also necessary.
Further it is provided that mechanism under motherboard grade of adjustment one data strobe and its relevant data signals is also that have must
It wants.
Furthermore in order to reach optimization reception state, it is a kind of under motherboard grade by synchronous bus signal be aligned can
Programmer is also necessary.
Summary of the invention
The present invention proposes to solve for prior art problem, disadvantage and limitation.In addition, the present invention provides a preferable skill
Art is to optimize the transmission and reception of the source synchronous signal in different devices, such as microprocessor and its supports device.?
In one embodiment, provide a kind of device to compensate the non-alignment on synchronous data bus, the device include a resistor network,
One core clock generator and a synchronous gate driver.The resistor network is to provide a ratio signal to indicate that one shifts to an earlier date
Amount gates signal with a synchrodata related with a data group in advance.The core clock generator is coupled to ratio news
Number, a data strobe timing signal is shifted to an earlier date with the lead.The synchronous selection pass driver receives the data strobe timing signal, and
Synchrodata gating signal is generated according to the data strobe timing signal, and synchrodata gating is interrogated in advance with the lead
Number.
The one kind that also provides of the invention shifts to an earlier date synchronous selection pass transmitting device, non-right on synchronous data bus to compensate
It together, should synchronous selection pass transmitting device include in advance a resistor network and a microprocessor.The resistor network is to provide a ratio
Example signal, the ratio signal indicate a lead, gate signal with a synchrodata related with a data group in advance.This is micro-
Processor includes a core clock generator and a synchronous gate driver.The core clock generator is coupled to ratio news
Number, a data strobe timing signal is shifted to an earlier date with the lead.The synchronous selection pass driver receives the data strobe timing signal, and
Synchrodata gating signal is generated according to the data strobe timing signal, wherein the synchrodata gates signal with the lead
In advance.
The present invention also provides a kind of methods of the non-alignment on compensation synchronous data bus, including mention by a resistor network
For a ratio signal, which indicates a lead, with synchrodata gating news related with a data group in advance
Number；A core clock generator is coupled to the ratio signal, the core clock generator is made to propose last data choosing with the lead
Signal when amounting to；And data strobe timing signal is provided to a synchronous gate driver, according to the data strobe timing signal
Synchrodata gating signal is generated, and the synchrodata gates signal in advance with the lead.
About the applicability in industry, invention can be implemented in the computer installations of general service or specific use to be used
A microprocessor in.
Detailed description of the invention
Fig. 1 shows the block diagram of an embodiment of source synchronous data system now.
Fig. 2 shows the timing diagram of the source synchronous signal situation of the source synchronous data system of Fig. 1.
Fig. 3 shows the block diagram of an embodiment of synchronous selection pass transmission device in advance of the invention.
Fig. 4 shows the block diagram of an embodiment of radial synchronous selection pass distributing equipment of the invention.
Fig. 5 shows the block diagram of an embodiment of Lag synchronization data receiver of the invention.
Fig. 6 display shows the block diagram of an embodiment of delay locked loop of the invention.
Fig. 7 display shows the block diagram of an embodiment of optimization sync signal programmable device of the invention.
Accompanying drawings symbol description
100 source synchronous data systems
102 bus clock generators
110 device A
111 core clock generators
112 synchronous selection pass drivers
113 synchrodata drivers
120 device B
122 synchronous receivers
200 timing diagrams
201 describe bus timing signal
202 data timing signals
203 data strobe timing signals
210 first situations
211 signals
212 data-strobe signals
220 second situations
221 signals
222 data-strobe signals
300 shift to an earlier date synchronous selection pass transmission device
310 shift to an earlier date gated transmission device
311 core clock generators
331 phase-locked loops element forward
332 frequency dividers
333 delay locked loops
312 synchronous selection pass drivers
400 radial synchronous selection pass distributing equipments
420 device C
434 composite delay elements
434.1~434.N delay element
422 synchronous receivers
500 Lag synchronization data receivers
520 delayed data reception devices
522 synchronous receivers
533 delay locked loops
600 delay locked loops
601 delayed encoders
602 multiplexers
603 analog-to-digital converters
700 optimize sync signal programmable device
701 shift to an earlier date signal device
711 core clock generators
712 synchronous selection pass drivers
722 synchronous receivers
731 testing action united organization interfaces
732 synchronous bus optimizers
733 delay locked loops
BCLK bus timing signal
DCLK data timing signal
DSCLK data strobe timing signal
DSTROBE, DSTROBE1~DSTROBEN data-strobe signal
DATA1~DATAN data bit signal
I invalid period
The V valid period
T1, T2, T3, T4 time
R1, R2 resistance
RAT ratio signal
VDD reference voltage
REF reference signal
DREF postpones reference signal
DDATA delayed data position signal
IN, OUT signal
DSEL [63:0] the delayed selection culture bus
U1A, U1B, U2A, U2B~U63A, U63B reverser
D0~D63 postpones tap
JTAG [N:0] standard testing action united organization bus
DSTROBEX, DSTROBEY data-strobe signal
ARAT, DRAT bus
Specific embodiment
To further illustrate that each embodiment, the present invention are provided with attached drawing.Attached drawing is a part of disclosure of the present invention,
Mainly to illustrate embodiment, and explain in combination with the associated description of specification the operation principles of embodiment.With reference in these
Hold, those skilled in the art will be understood that other possible embodiments and advantages of the present invention.Therefore, the present invention is not limited to
The embodiment for showing and describing below, should so authorize the widest scope for meeting operations described below principle and novel feature.
It is same about being used to transmit now and receiving source used in the device of data in view of above-mentioned prior art discussion
The shortcomings that transmission of step signal and relevant technology, the prior art and limitation will combine Fig. 1, Fig. 2 discussion.Then, the present invention will join
Fig. 3 to Fig. 7 is examined to discuss.Data-strobe signal and data bit signal of the present invention by delay and in advance in a pair of of device
Mechanism come the shortcomings that overcoming the prior art and limitation, so that correction is by the gating signal and data signals caused by any reason
Non-alignment (misalignment), to optimize this to the flux between device.
Referring first to Fig. 1, display is according to now in transmission and the system block diagrams of receipt source synchrodata.Source
Synchrodata system 100 includes a signal transmission 110 (following weighing device A) and 120 (following weighing device of a reception device
B), device A 110 is coupled to reception device 120 by a source synchronous bus 130, and source synchronous bus 130 includes a data
Gate signal DSTROBE and relative multiple data bit signal DATA1~DATAN.Source synchronous data system 100 also wraps
A bus clock generator 102 is included, device A 100 is coupled to by bus timing signal BCLK.Device A 110, device B
120 and bus clock generator 102 be usually all arranged in a motherboard (not shown), and data bit signal DATA1~
DATAN, data-strobe signal DSTROBE and bus timing signal BCLK then essentially as device A 110 and device B 120 it
Between interconnect the path of mechanism.Data-strobe signal DSTROBE is from point 13S input unit B 120, and data bit signal
DATA1~DATAN is respectively from point 131~13N input unit B 120.According to a kind of typical synchronous state sample implementation, one group of data
The physical length of the access record of position signal DATA1~DATAN and relative data-strobe signal DSTROBE
(physical length) is equal, so that any transmission line undergone by data-strobe signal DSTROBE acts on, such as
Transmission delay is also undergone by data bit signal DATA1~DATAN.The target of source synchronous data system 100 is in bus
Data bit signal DATA1~DATAN on 130 valid period midway accurately change data gating signal DSTROBE shape
State (state), therefore the transmission data best reception state appropriate in device B 120 is provided.
There is device A 110 the synchronous gate driver 112 of a core clock generator 111, one and multiple synchrodatas to drive
Dynamic device 113, core clock generator 111 are coupled to synchronous selection pass driver 112 and multiple synchrodata drivers 113.Core
Clock generator 111 generates a boundary in the data strobe timing signal DSCLK and a data meter of other timing signal (not shown)
When signal DCLK.The data-strobe signal DSTROBE and data strobe timing signal DSCLK that synchronous selection pass driver 112 generates
Same-phase, the data bit signal DATA1~DATAN and data timing signal DCLK same-phase that synchrodata driver 113 generates.
Data strobe timing signal DSCLK and data timing signal DCLK be according to bus timing signal BCLK obtain, therefore can with come
The data transmission and reception synchronization comprehensively between other device (not shown) in source-synchronous data system 100.According to an allusion quotation
The embodiment of type, data timing signal DCLK and data strobe timing signal DSCLK are the frequency multiplication of bus timing signal BCLK, are made
Obtain the alignment of data strobe DSTROBE of the data bit signal DATA1~DATAN in bus 130 within the valid period
It (alignment) is accurate.In other examples, two kinds of gating types can be used single derivative timing signal, and
The edge trigger data transmission of derivative timing signal, and in one gating of other edge triggering of derivative timing signal.
Device B 120 includes multiple corresponding synchronous receivers 122, and each of multiple synchronous receivers 122 receives number
According to one in the signal DATA1~DATAN of position, all synchronous receivers 122 receive data-strobe signal DSTROBE.Work as number
According to (data-strobe signal DSTROBE changes state) when gating signal DSTROBE timing, synchronous receiver 122 is checked respectively for
One in its other data bit signal DATA1~DATAN.
Those skilled in the art is to be appreciated that the source synchronous data system 100 in Fig. 1 represents device A 110
And the state sample implementation that the one of device B 120 simplifies, it may type or laptop computer, tablet computer or any spy on the table
It is found in the computing device and instrument of different purposes.For more specifically, device A 110 and device B 120 can be by central processing lists
First (central processing unit, CPU) or microprocessor, chipset (supporting chipset) or memory
Interface, hub memory or controller, direct memory access (DMA) unit (direct memory access unit), figure
Controller and its similar device are realized.Typically, these devices 110,120 can be bus agent device, and by point-to-point
Source synchronous bus 130 be coupled against each other, as exemplified by the bus 130 of Fig. 1.
From broadly, in order to transmit data, one of them (such as device A 110) of bus agent device will drive bus
The subset (subset) in data bit signal DATA1~DATAN and data-strobe signal DSTROBE on 130, and another
It, can be by the data bit signal DATA1 in bus 130 when bus agent device (such as device B 120) detection and reception driving signal
The state of one or more subsets in~DATAN and data strobe DSTROBE carrys out acquisition data.It is used for two bus generations now
The bus protocol of the data transmission between device is managed there are many kind, the detailed description of these different technologies has exceeded the application
The range of book.It can fully understand herein, during bus transfer, be transmitted in two or more bus agent devices 110,120
Between " data " may include address information, data related with address information, control information or status information, be so not limited to
This.No matter why is the type of data of the transmission in bus 130, it is notable that the source synchronous number now of this specification
According to the bus protocol that system 100 uses for a kind of common " source synchronous " agreement, to realize with very high total linear speed
Degree is to transmit data.The principle of bus protocol against existing technologies, the operation of source synchronous communications protocol is that transmission is total
Line proxy server 110 by data bit signal DATA1~DATAN in a data group export to bus 130 continue one it is fixed when
Between, and the data-strobe signal DSTROBE for corresponding to data bit signal DATA1~DATAN is issued, bus is received with instruction one
The data of proxy server 120 are effective.It is as previously mentioned, the target of source synchronous data system 100 is by data-strobe signal
DSTROBE indicates data bit signal in a time point (the usually midway of data bit signal DATA1~DATAN valid period)
The validity of DATA1~DATAN, this is optimum for reception device 120 receives data bit signal DATA1~DATAN
's.
Those skilled in the art it will be appreciated that under very high transmission speed, one group of data bit signal DATA1~
The transmission path of the entity and electric parameter of DATAN and corresponding data-strobe signal DSTROBE and boundary are in two devices
110, other group of signal (not shown) in a bus 130 between other possible device (not shown) in 120
One of the advantages of possible comparable difference of transmission path, this is point-to-point source synchronous communications protocol.That is, specific number
Only two devices 110,120 are coupled against each other according to position signal DATA1~DATAN and relevant data-strobe signal DSTROBE, such as
This many problem that shared-bus system can be prevented intrinsic, the specifically transmission delay of transmission path, bus impedance and electrical
Characteristic influences to receive the stabilization of the received data bit signal DATA1~DATAN of bus agent device 120 or effective time.Due to
This reason, source synchronous bus protocol are fairly common on the market.In typical state sample implementation, interrogated with one group of data bit
Number relevant data-strobe signal DSTROBE of DATA1~DATAN will be along identical as this group of data bit signal DATA1~DATAN
Transmission path transmit, such data-strobe signal DSTROBE would indicate that and data bit signal DATA1~DATAN itself
Identical transmission characteristic.If the data strobe during data that data bit signal DATA1~DATAN is included are effective
Signal DSTROBE is set, and when reception bus agent device 120 detects that data-strobe signal DSTROBE is effective, then data
Position signal DATA1~DATAN is also undoubtedly effective.
Even if there is above advantages, present invention contemplates that still there is other factors to negatively affect the complete of source synchronous interface
Property, the i.e. mode that data-strobe signal DSTROBE is transmitted in device B 120 after point 13S enters device B 120.As schemed
Show, when data bit signal DATA1~DATAN and data-strobe signal DSTROBE along intimate identical transmission path from device A
110 are transmitted to device B 120, must be in device B once data-strobe signal DSTROBE enters device B 120 from point 13S
N number of different synchronous receiver 122 is transmitted in 120.And although a synchronous receiver 122 is desirably placed at closely
Corresponding data bit signal DATA1~DATAN is input at the chip layout of device B 120, to data-strobe signal
Be not the same for DSTROBE, this is because data-strobe signal DSTROBE must distribute to data bit signal DATA1~
The corresponding all synchronous receivers 122 of DATAN.Although therefore the present invention, which observes, may arrange synchronous receiver 122 wherein
One, so that its data bit signal DATA1~DATAN and data-strobe signal DSTROBE are transmitted to synchronize and connect from device A 110
The transmission path for receiving the input of device 122 is nearly identical, and the associated transport path of remaining data bit signal DATA1~DATAN will
Different from the transmission path of data-strobe signal DSTROBE (as observed by corresponding 122 input terminal of synchronous receiver).This
It is because the physical path of data-strobe signal DSTROBE is longer than or shorter than remaining data bit signal DATA1~DATAN
Physical path, and the buffering also comprising the data-strobe signal DSTROBE for distribution.Therefore, data-strobe signal DSTROBE
Conversion be likely in a period of the data validity of remaining data bit signal DATA1~DATAN earlier than or be later than device A
110 arrangers.In fact, the present invention is the data-strobe signal in device B 120 in view of a kind of extreme example
The transmission of DSTROBE can not be controlled via the designer of device A 110, be transmitted to corresponding synchronous receiver configured in this way
122 one or more transmission paths, so that when data-strobe signal DSTROBE changes state to indicate data bit signal
DATA1~DATAN be it is effective, at the time of data-strobe signal DSTROBE changes state, it may occur however that correspond to one or
One or more of data bit signal DATA1~DATAN of multiple transmission paths is not effective.
Further, since data strobe timing relevant to data bit signal DATA1~DATAN of synchronous bus 130 is passed through
Signal DSCLK and data timing signal DCLK is usually by the analog circuit (i.e. phase-locked loop) in core clock generator 111
Produced, the present inventor emphasizes by the caused signal trembling of the design and manufacture of core clock generator 111 itself, work week
Phase and inaccuracy, it will data-strobe signal DSTROBE is made to show the Usefulness Pair dress of data bit signal DATA1~DATAN
Set the synchronous receiver 122 in B 120 reception be it is undesirable so that the data-strobe signal in device B 120
The non-alignment of DSTROBE and data bit signal DATA1~DATAN more deteriorate.As observed by synchronous receiver 122 relative to
The problem of non-ideal switching of the data-strobe signal DSTROBE of data bit signal DATA1~DATAN, can refer to the explanation of Fig. 2
Make discussion more specifically.
Fig. 2 is to describe two source synchronous signal situations possibly being present in the source synchronous data system 100 of Fig. 1
210,220 timing diagram 200.In the first situation 210, data-strobe signal 212 in reception device and relevant signal
211 be synchronous, and 220 in the second situation, and data-strobe signal 222 is asynchronous to relevant signal 221.Due to upper
The inaccuracy or the inaccuracy in transmitting device or reception device of transmission, buffering, assignment latency or the clock generator stated
Property or error and cause the difference of transmission path so that generate data-strobe signal 212,222 and corresponding signal 211,
221 relative phase.
Timing diagram 200 describes bus timing signal BCLK 201, and thus signal derives data timing signal DCLK
202 and data strobe timing signal DSCLK 203.As shown in connection with fig. 1, data timing signal DCLK 202 and data strobe timing
Signal DSCLK 203 distributed in transmitting device to synchrodata driver related with data bit signal DATA1~DATAN and
Data strobe driver.Driver is existed using timing signal 202,203 come accurately arrangement data position signal DATA1~DATAN
On one synchronous bus, the validity of data bit signal DATA1~DATAN is also shown, so that number can be correctly received in reception device
According to position signal DATA1~DATAN.It is noted that data timing signal DCLK 202 and data strobe timing signal DSCLK
203 frequency is twice of the frequency of bus timing signal BCLK 201, this is for particularly shown clear intention, with religion
Show the related problem of the intelligible prior art of those skilled in the art, i.e., the timing signal 202,203 in present-day devices
According to its accurate purpose, skew and its opposite frequency range are from 2 times to 64 of 201 frequency of bus timing signal BCLK
Times, and frequency is as shown in timing diagram 200, is the limit for more clearly showing technology today.
Timing diagram 200 is also shown, in the first situation 210, in the first receiver about data bit signal DATA1 one
Data input 211 and data strobe input 212 are synchronous, and in the second situation 220, about data in the n-th receiver
The data input 221 and data strobe input 222 of position signal DATAN is asynchronous.As for data bit signal DATA1
Other all data bit signal DATA2~DATA (N-1) related data-strobe signal DSTROBE, Ke Nengxian in~DATAN
Show compared to the more or fewer alignments of input as shown in timing diagram 200.
Therefore, in time T1, the transmission of data bit signal DATA1~DATAN is generally effective on synchronous bus
The midway of period (V), as shown, being fallen at the drop edge of data timing signal DCLK 202.It is noted that bus
On data bit signal DATA1~DATAN setting (assertion) can occur data timing signal DCLK 202 other
At edge or phase.At this time point, data strobe timing signal DSCLK 203 is also switched over, therefore data are arranged and select
Communication DSTROBE.According to the first situation 210, the input 212 of the first receiver receives data-strobe signal DSTROBE's
Time, the substantially midway in the valid period of data bit signal DATA1, and DATA1 is the input 211 by the first receiver
It is received.For the reception of data bit signal DATA1, this is an optimal cases, and shows the effect of transmission line, especially
Be input 211 and 212 display data bit signal DATA1 and data-strobe signal DSTROBE transmission time it is almost equal.It is defeated
Enter 211,212 and shows same optimal reception condition in time T2.
However, the second situation 220 is really not so, because input 222 is to detect data-strobe signal in time T3 and T4
The state of DSTROBE changes the time, but at this time data bit signal DATAN be regarded as in input 221 it is invalid.Namely
It says, due to aforementioned mentioned reason, data-strobe signal DSTROBE lags behind data bit signal in the phase of input 222
Phase of the DATAN in input 221.This phenomenon is caused the possible reason is data-strobe signal DSTROBE has to pass through a length
Path, this path are input to reception device by one, to reach the receiver of data bit signal DATAN.Another possible reason
It is the inaccuracy in transmitting device.It can also be that other reasons cause.
Therefore, the inventor have observed that, once a device complete design and manufacture, i.e., do not exist reasonable manner come
Correct these problems, including via motherboard transmission by transmission delay increase to one or more data bit signal DATA1~
DATAN or data-strobe signal DSTROBE, with compensation transmission or the problem of reception device.
In addition, present invention contemplates that providing the data bit signal DATA1 in a kind of adjustable or modification source synchronous bus
The mechanism of phase difference between~DATAN and data-strobe signal DSTROBE has urgent need, and this mechanism does not need
The layout and wiring on motherboard are modified, does not also need to modify one or more receptions and transmission device.
The present invention provides the gating signal and one group corresponding of each receiver received data in a kind of pair of reception device
Relative phase difference between data bit signal makees the device and method finely tuned, to overcome problem of the prior art above-mentioned.It connects down
Come, will illustrate the present invention with reference to Fig. 3 to Fig. 7.
Referring to FIG. 3, for the block diagram of an embodiment of synchronous selection pass transmission device 300 in advance according to the present invention.It mentions
Preamble gated transmission equipment 300 shifts to an earlier date gated transmission device 310 including one, and it is total to be coupled to one for gated transmission device 310 in advance
Line timing signal BCLK, and the device A 110 of data-strobe signal a DSTROBE, substantially similar Fig. 1 is generated, in addition to this
The gated transmission device 310 in advance of invention by a ratio signal RAT, relative to its relevant data bit signal, (do not draw by figure
Show) carry out the transmission of data-strobe signal DSTROBE in advance.Ratio signal RAT is coupled to resistance R1 and R2.Resistance R1 is coupled to one
Reference voltage VDD, reference voltage VDD are also coupled to gated transmission device 310 in advance.Resistance R2 is further coupled to a common ground connection ginseng
Examine voltage.
Gated transmission device 310 includes a core clock generator 311 and a synchronous gate driver 312 in advance.It is synchronous
312 output data strobe signal DSTROBE of gate driver.Core clock generator 311 includes phase-locked loop element forward
331, a frequency divider 332 and a delay locked loop 333.Element 331 as is known to the person skilled in the art may be used forward for phase-locked loop
Generate a data strobe timing signal DSCLK.Core clock generator 311 also includes a frequency divider 332, receives one with reference to news
Number REF, reference signal REF are a feedback signal of data strobe timing signal DSCLK.Core clock generator 311 also includes
One delay locked loop 333 is coupled to frequency divider 332, and delay locked loop 333 receives ratio signal RAT.Postpone locking phase
Circuit 333 provides a delay reference signal DREF and is fed back to phase-locked loop element 331 forward.
When operation, the generation data strobe timing signal DSCLK of core clock generator 311, and data strobe timing signal
The frequency of DSCLK is the multiple of the frequency of bus timing signal BCLK, medium multiple be by phase-locked loop forward element 331 and
Any means known of the configuration of frequency divider 332 is determined.In addition, core clock generator 311 by ratio signal RAT with relative to
Bus timing signal BCLK carrys out the phase of the signal of data strobe timing in advance DSCLK.According to an embodiment, ratio signal RAT is used
With specify data strobe timing signal DSCLK in advance be its period more than half.According to another embodiment, resistance R2 ratio
The ratio of resistance R1 determines that a voltage value of ratio signal RAT, the voltage value are detected by delay locked loop 333,
Size is the percentage of reference voltage VDD.Delay locked loop 333 is by the delay proportional to the voltage value of ratio signal RAT
Introduce frequency divider 332 output, with generate postpone reference signal DREF so that phase-locked loop forward element 331 with same
Retardation carry out the signal of data strobe timing in advance DSCLK.According to an embodiment, if the ratio pole of resistance R2 specific resistance R1
Small, i.e. resistance R2 is equal to 0 ohm, then delay locked loop 333 will not generate delay, and the effect of core clock generator 311
Substantially like the core clock generator 111 of Fig. 1.If the ratio of resistance R2 specific resistance R1 is very big, i.e. resistance R1 is equal to 0 Europe
Nurse, the then retardation that delay locked loop 333 generates are similar to the half in the period of data strobe timing signal DSCLK, so
The lead of data strobe timing signal DSCLK is caused to be similar to same retardation.If the ratio of resistance R2 specific resistance R1
Equal to 1, i.e. resistance R1 is equal to resistance R2, then the delay that delay locked loop 333 generates is similar to data strobe timing signal
The a quarter in the period of DSCLK so causes the lead of data strobe timing signal DSCLK to be similar to identical delay
Amount.Other mechanism are also considered, and delay locked loop 333 generates biggish delay, so cause data strobe timing signal
The half for being greater than its period in advance of DSCLK.Other embodiments then consider the scheme of nonlinear lead.
According to another embodiment, core clock generator 311 by delay locked loop 333 be configured at frequency divider 332 it
Before, it is a feedback circuit for data strobe timing signal DSCLK.That is, the present embodiment is derivative by ratio signal RAT
Then delayed data gating timing signal DSCLK is divided out and is postponed by the retardation of delayed data gating timing signal DSCLK out
Reference signal DREF, rather than feedback signal delay is approximately equal to data strobe timing signal DSCLK, then by ratio signal
RAT derives the retardation for postponing the feedback signal.
Gated transmission device 310 in advance of the invention is as described above to the function of executing and operation.Gated transmission in advance
Device 310 includes logic, circuit, device or microcode (microcode), wherein microcode, that is, microcommand (micro
Instruction) or presumptive instruction (native instruction), or by the combination of logic, circuit, device or microcode,
Or the equivalence element to execute function same as the present invention and operation.It is used to realize this in gated transmission device 310 in advance
The element of a little operations and function may be shared with other circuits or microcode etc., other circuits or microcode are gated transmissions in advance
It is used to execute the element of other function and/or operation in device 310.Range described in the specification, microcode are according to the present invention
One is used to the term (term) with reference to multiple microcommands, and a microcommand (also can refer to as a presumptive instruction) is a unit
(unit) instruction performed under standard.For example, multiple microcommands are by a Reduced Instruction Set Computer (reduce
Instruction set computer, RISC) microprocessor directly execute.Complex Instruction Set Computer (complex
Instruction set computer, CISC) microprocessor, x86 instruction translation is by such as the processor that x86 is compatible
Relevant microcommand, and relevant microcommand is by a unit or the microprocessor of a Complex Instruction Set Computer
Multiple units directly execute.
Whereby, gated transmission device 310 in advance of the invention can be mentioned relative to the transmission of its relevant data bit signal
The transmission of preceding data-strobe signal DSTROBE, with compensate reception device received signal phase be misaligned.
Then, referring to FIG. 4, gating distributing equipment 400 for radial direction synchronous (radial synchronous) of the invention
An embodiment block diagram.Radial synchronous selection pass distributing equipment 400 shifts to an earlier date synchronous selection pass transmission device 300 in combination with Fig. 3's
To use.Radial synchronous selection pass distributing equipment 400 includes a reception device 420 (following weighing device C), device C 420 and Fig. 1's
Device A 120 is similar, and the principle difference of the two is, the device of the invention C 420 includes a composite delay element 434, compound
Delay element 434 to be used to receive the data-strobe signal DSTROBE's from transmitting device (not shown) in device C 420
All delay paths are impartial.Device C 420 further includes multiple synchronous receivers 422, to receive one or more along with number
According to data bit signal DATA1~DATAN of gating signal DSTROBE.First in multiple data bit signal DATA1~DATAN
Data bit signal DATA1 is shown from 1: 431 to associated synchronous receiver from the 1: 431 input unit C 420
422 the first transmission delay.Last data bit signal DATAN in multiple data bit signal DATA1~DATAN is from last
433 input unit C 420 of point, and display is prolonged from last point 433 to the last transmission of associated synchronous receiver 422
Late.One or more data bit signal DATA1~DATAN are shown relative to remaining in multiple data bit signal DATA1~DATAN
A data bit signal longest transmission delay.
Data-strobe signal DSTROBE is sent to composite delay element 434 from 432 input unit C 420 of point.It is compound
Delay element 434 include multiple 434.1~434.N of delay element, 434.1~434.N of delay element each with it is corresponding
Synchronous receiver 422 is associated.One time delay is introduced data-strobe signal by each of 434.1~434.N of delay element
DSTROBE is sent to the transmitting path of corresponding synchronous receiver 422 from composite delay element 434.It is multiple according to an embodiment
The retardation of each of 434.1~434.N of delay element makes data-strobe signal DSTROBE from point 432 to multiple same
It walks when being transmitted in the transmission path of each of receiver 422 with the longest transmission delay.According to an embodiment, delay
Each of 434.1~434.N of element includes one or more pairs of reversers (inverter).Under the manufacturing process of 32 nanometers,
Each pair of reverser generates the gate delay (gate delay) of nearly 20 picoseconds (picoseconds), so will lead in data
Gate the delay that 20 picoseconds occur on the associated transport path of signal DSTROBE.
Whereby, the radial synchronous selection pass distributing equipment 400 in Fig. 4 makes 422 institute of receiver in device C 420 received
Data-strobe signal DSTROBE all has almost equal phase delay relative to each data bit signal DATA1~DATAN.
Therefore, in advance gated transmission device 310 the advantages of be, by selection resistance R1 and resistance R2 resistance value so that it is multiple together
Walk receiver 422 institute received multiple data-strobe signal DSTROBE1~DSTROBEN the phase of each, just shift to an earlier date
To the midway of the valid period of each of corresponding data bit signal DATA1~DATAN.For example, if in 32 nanometers
Under technology, longest delay is 10 picoseconds, then each of 434.1~434.N of delay element will be so that data strobe be interrogated
The transmission path that number DSTROBE is transmitted to corresponding synchronous receiver 422 generates additional delay, and then makes a little 432 to reception
All transmission delays of input are equal to 10 picoseconds, and the resistance value of resistance R1 and resistance R2 is selected to make data-strobe signal
The transmission of DSTROBE shifts to an earlier date 10 picoseconds relative to the transmission of data bit signal DATA1~DATAN.
The device of the invention C 420 is to execute above-mentioned function and operation.Device C 420 includes logic, circuit, device
Or microcode, the wherein combination of microcode, that is, microcommand or presumptive instruction or logic, circuit, device or microcode, or to hold
Row function same as the present invention and the equivalence element of operation.It is used to realize these operations and function in the device of the invention C 420
The element of energy may be shared with other circuits or microcode etc., other circuits or microcode are used in the device of the invention C 420
To execute the element of other function and/or operation.
Then, referring to FIG. 5, the block diagram of the embodiment for Lag synchronization data receiver 500 of the invention.Prolong
Slow synchrodata receiving device 500 includes a delayed data reception device 520, is similar to the reception device 120 of Fig. 1, and is connect
Unlike receiving apparatus 120, in order to by the valid period of one or more data bit signals of synchronous receiver 522 with it is corresponding
Data-strobe signal DSTROBE be aligned, delayed data reception device 520 can make one or more numbers of a data group
Delay is generated according to the transmission path of position signal.It is not to interrogate data strobe relative to data bit signal DATA in the present embodiment
The phase of number DSTROBE is shifted to an earlier date, but the phase of delayed data position signal DATA relative to data-strobe signal DSTROBE
Position.
Whereby, delayed data reception device 520 is coupled to ratio signal RAT and reference voltage VDD.First resistor R1 coupling
It is connected between ratio signal RAT and reference voltage VDD, and second resistance R2 is coupled to ratio signal RAT and ground reference.
Delayed data reception device 520 include a delay locked loop 533 and a synchronous receiver 522, delay locked loop 533 to
Data bit signal DATA is received, and generates a delayed data position signal DDATA, delayed data position signal DDATA includes and R2
A delay more proportional than the ratio of R1.Delayed data position signal DDATA is inputted along with data-strobe signal DSTROBE and is synchronized
Receiver 522.
When practical operation, delay locked loop 533 carrys out delayed data position signal by numerical value pointed by ratio signal RAT
Phase of the DATA relative to data-strobe signal DSTROBE.According to an embodiment, ratio signal RAT makes data bit signal
The half in period of the delay no more than data-strobe signal DSTROBE of DATA.According to an embodiment, delay locked loop 533
The voltage value of the ratio signal RAT detected is determined by the ratio of resistance R2 specific resistance R1, wherein voltage value detected
It is proportional to reference voltage VDD, and delay locked loop 533 makes the delayed data position signal DDATA of output generate one and ratio
Signal RAT proportional delay, such synchronous receiver 522 can more appropriately receive data bit signal DATA.Implement according to one
Example, if the ratio of resistance R2 specific resistance R1 is minimum, i.e. resistance R2 is equal to 0 ohm, then delay locked loop 533 will not generate and prolong
Late, and the reception state of synchronous receiver 522 is substantially equal to the synchronous receiver 122 of Fig. 1.If resistance R2 specific resistance R1's
Ratio is very big, i.e. resistance R1 is equal to 0 ohm, then the delay that delay locked loop 533 generates is similar to data-strobe signal
The half in the period of DSTROBE so causes the retardation of data bit signal DATA to be similar to same retardation.If resistance
The ratio of R2 specific resistance R1 is equal to 1, i.e. resistance R1 is equal to resistance R2, then the delay that delay locked loop 533 generates is similar to count
According to a quarter in the period of gating signal DSTROBE, the retardation of data bit signal DATA is so caused to be similar to similarly
Retardation.Other mechanism are also considered, and delay locked loop 533 generates biggish delay, so cause data bit signal DATA
Delay be greater than its period half.Other embodiments then consider the nonlinear retardation generated by delay locked loop 533.
In order to clearly express, Fig. 5 only shows a synchronous receiver 522, however the present invention also considers multiple delays
Phase-locked loop 533 transmits the data bit signal DATA of a data group with multiple corresponding synchronous receivers 522, wherein ratio
Signal RAT is distributed to each of delay locked loop 533, so that identical retardation introduces each of data bit signal DATA
In a transmission path.
The delayed data reception device 520 of Fig. 5 to one or more data bit signal DATA in delayed data group,
Especially when delayed data reception device 520 includes the radial data gating distribution mechanism similar to Fig. 4.The device C of Fig. 4
420 increase the delay of the transmission path of multiple data-strobe signal DSTROBE1~DSTROBENs related with data group, make
Obtain all transmission paths all has a phase delay (phase lag) relative to most slow transmission path, must so incite somebody to action
The one or more of data bit signal DATA1~DATAN is realigned with data-strobe signal DSTROBE1~DSTROBEN
(realign).Whereby, the device C 420 that the delayed data reception mechanism of Fig. 5 is incorporated to Fig. 4 will be made to the alignment of these signals
Effect is preferable.
Delayed data reception device 520 of the invention is as described above to the function of executing and operation.Delayed data receives
Device 520 includes logic, circuit, device or microcode, wherein microcode, that is, microcommand or presumptive instruction or logic, circuit, dress
It sets or the combination of microcode, or the equivalence element to execute function same as the present invention and operation.Delayed data receives dress
It sets and is used to realize that the element of these operations and function may be shared with other circuits or microcode etc. in 520, other circuits or micro-
Code is the element for being used to execute other function and/or operation in delayed data reception device 520.
Then, referring to FIG. 6, the block diagram of its embodiment for showing delay locked loop 600 of the invention.Delay lock
Phase circuit 600 can be applied to Fig. 3 and 5 figures.Delay locked loop 600 includes an analog-to-digital converter (analog-to-
Digital converter) 603, analog-to-digital converter 603 is to receive ratio signal RAT, wherein ratio signal RAT
Value indicate a signal IN transmission path delay.When delay locked loop 600 applies to the gated transmission dress in advance of Fig. 3
310 are set, signal IN is the output of frequency divider 332, and signal OUT is delay reference signal DREF.When delay locked loop 600 is transported
For the delayed data reception device 520 of Fig. 5, signal IN is data bit signal DATA, and signal OUT is delayed data position signal
DDATA.Ratio signal RAT is converted to a digital signal by analog-to-digital converter 603, and digital signal is transmitted to delay
Encoder 601.Delayed encoder 601 generates the state of signal on a delayed selection culture bus DSEL [63:0], in order to clearly
It has been shown that, Fig. 6 only shows 64, however the invention is not limited thereto, and the running of the position of other different numbers is also identical.The delayed selection culture is total
Line DSEL [63:0] is coupled to a multiplexer 602, and the selection as multiplexer 602 inputs.Signal IN passes through multiple reversers pair
(inverter pair) U1A, U1B ..., U63A, U63B, each gate delay having the same.Postpone tap D0~D63
As the input of multiplexer 602, and the signal OUT that exports of multiplexer 602 is according to the value of the delayed selection culture bus DSEL [63:0],
Position in middle the delayed selection culture bus DSEL [63:0] only has one and (asserted) is individually set, to indicate multiplexer 602
The one delay tap D0~D63 issued.For example, if all positions are not set, the selection delay point of multiplexer 602
Connector D0, then all signal IN all do not postpone.If position 63 is arranged, the then selection of multiplexer 602 postpones tap D63,
Then signal IN generates maximum retardation.It is noted that size (the i.e. reverser pair of delay locked loop 600 of the present invention
U1A, U1B ..., the number of U63A, U63B, the number for postponing tap D0~D63 and the delayed selection culture bus DSEL [63:0]
Number) it is not limited to this, also it is contemplated that other different numbers.In addition, increasing anti-between delay tap D0~D63
The longer delay to match with design requirement can be increased to the number of device pair.
Delay locked loop 600 includes logic, circuit, device or microcode, wherein microcode, that is, microcommand or original finger
It enables or the combination of logic, circuit, device or microcode, or the equivalent member to execute function same as the present invention and operation
Part.It is used to realize that the element of these operations and function may be shared with other circuits or microcode etc. in delay locked loop 600,
Other circuits or microcode are the elements for being used to execute other function and/or operation in delay locked loop 600.
Then, referring to FIG. 7, it shows the embodiment for optimizing sync signal programmable device 700 of the invention
Block diagram.It optimizes sync signal programmable device 700 and shifts to an earlier date signal device 701 including one, to optimize sync signal.It mentions
Preceding signal device 701 includes a core clock generator 711, and core clock generator 711 is to receive bus timing signal
BCLK, and generate the synchronous gate driver 712 of a data strobe timing signal DSCLK to one.Synchronous selection pass driver 712 generates
One in multiple data-strobe signal DSTRPBEX, multiple data-strobe signal DSTRPBEX are and correspond to particular address group
The data bit signal (not shown) of group is related, as described above.
Signal device 701 further includes a delay locked loop 733 in advance, and delay locked loop 733 receives data bit news
Number DATA, and a delayed data position signal DDATA is generated, and be sent to synchronous receiver 722.Synchronous receiver 722 also receives
One other data-strobe signal DSTROBEY, data-strobe signal DSTROBEY are related with data bit signal DATA.
In addition, signal device 701 further includes a testing action united organization interface (Joint Test Action in advance
Group, JTAG) 731, jtag interface 731 receives the control letter in standard testing action united organization interface JTAG [N:0]
Breath, and transmit one and be applied to the information of data-strobe signal DSTRPBEX and delayed data position signal DATA in advance to one synchronous
Bus optimizer 732.Synchronous bus optimizer 732 generates a programmable gating Advanced information, and passes through ratio bus
ARAT is sent to core clock generator 711.And synchronous bus optimizer 732 generates a programmable data position and postpones information,
And delay locked loop 733 is sent to by ratio bus DRAT.
When practical operation, well known JTAG programming technique is used to be one or more data strobes (in order to clearly show
Show, only show a data-strobe signal DSTRPBEX in advance) one accurate lead of design, and be one or more data bit
Signal DATA (in order to clearly illustrate, only showing a data bit signal DATA) one accurate retardation of design.Programming operation
It can be performed in signal device 701 in advance when JTAG programs the state being allowed to, such as under resetting (RESET) state.It is compiling
When journey is executed into, the function of bus ARAT, DRAT is substantially similar to the bus RAT of Fig. 3 and Fig. 5, to provide control letter
It ceases to device 310,520.In addition, the radial distribution element of the device C 420 such as Fig. 4 also can be used in signal device 701 in advance
434。
According to an embodiment, bus ARAT is distributed to multiple core clock generators 711, each core clock generator
711 generate one it is corresponding and only one data strobe timing signal DSCLK.Different leads is by corresponding to data group
Jtag interface 731 arrange.Similarly, bus DRAT is distributed to multiple delay locked loops 733, each delay locking phase is returned
Road 733 generate one it is corresponding and only one delayed data position signal DDATA.Different retardations is by corresponding to data group
Jtag interface 731 arrange.
Therefore, the programmable signal device 701 in advance of Fig. 7 can enable asking for system designer compensation synchronous bus misalignment
Topic, without modifying motherboard.
Signal device 701 includes logic, circuit, device or microcode in advance, wherein microcode, that is, microcommand or original finger
It enables or the combination of logic, circuit, device or microcode, or the equivalent member to execute function same as the present invention and operation
Part.It is used to realize that the element of these operations and function may be shared with other circuits or microcode etc. in signal device 701 in advance,
Other circuits or microcode are the elements for being used to execute other function and/or operation in signal device 701 in advance.
Embodiments multiple and different according to the present invention described above, wherein various features can single or different combinations it is real
It applies.Therefore, the specific embodiment for being disclosed as illustrating principle of the present invention of embodiment of the present invention should be regardless of the limit present invention in being taken off
The embodiment shown.Furthermore, above narration and its attached drawing is only that present invention demonstration is used, and is not intended to be limited thereto.Other
The variation or combination of element are all possible, and are not contrary in spirit and scope of the invention.
The bibliography of related application
The application of present application priority is integrally all included in this according to following U.S. Provisional Patent Application case, Reference Number, the case
Case reference.
Claims (21)
1. a kind of Lag synchronization data receiver, to compensate the misalignment on synchronous data bus, the Lag synchronization data
Receiving device includes:
One resistance circuit, to provide a ratio signal, which indicates a retardation, has to delay with a data group
The data bit signal closed, wherein the data bit signal is sent by a transmitting device together with a data-strobe signal；And
One synchronous receiver is arranged in a reception device, is configured as receiving the data bit signal and the data-strobe signal,
The synchronous receiver includes:
One delay locked loop is coupled to the ratio signal, and the delay locked loop is to add to the data bit for the retardation
Signal, to generate a delayed data position signal, wherein the delayed data position signal is relative to the data-strobe signal with the delay
Amount delay, so that the synchronous receiver can be properly received the data bit signal.
2. Lag synchronization data receiver as described in claim 1, wherein the resistance circuit includes two resistance, this two
The resistance ratio of resistance indicates the retardation.
3. Lag synchronization data receiver as claimed in claim 2, wherein two resistance include a first resistor and one
Second resistance, the first resistor are coupled to a ground reference, which is coupled to a reference voltage, and two electricity
Resistance is coupled against each other in a node, which exports the ratio signal.
4. Lag synchronization data receiver as described in claim 1, wherein the phase of the data bit signal delays the delay
Amount, and the range of the retardation is that never phase was delayed to the half period of a data-strobe signal.
5. Lag synchronization data receiver as claimed in claim 4, wherein the delayed data position signal and the data strobe
Signal is transmitted to a synchronous receiver, state of the synchronous receiver to detect the delayed data position signal.
6. Lag synchronization data receiver as claimed in claim 5, the wherein delay locked loop and the synchronous receiver
It is arranged in a device, which is coupled to a motherboard, which is coupled to the motherboard, which passes through one
Additional pin inputs the device.
7. Lag synchronization data receiver as described in claim 1, wherein the ratio signal is distributed to multiple delay locking phases
Circuit, each delay locked loop correspond to the relevant data bit signal in the data group.
8. a kind of Lag synchronization data receiver, to compensate the misalignment on synchronous data bus, the Lag synchronization data
Receiving device includes:
One resistance circuit, to provide a ratio signal, which indicates a retardation, has with delay with a data group
The data bit signal closed, wherein the data bit signal is sent by a transmitting device together with a data-strobe signal；And
One synchronous receiver is arranged in a microprocessor, is configured as receiving the data bit signal and the data-strobe signal,
The synchronous receiver includes:
One delay locked loop is coupled to the ratio signal, and the delay locked loop is to add to the data bit for the retardation
Signal, to generate a delayed data position signal, wherein the delayed data position signal is relative to the data-strobe signal with the delay
Amount delay, so that the synchronous receiver can be properly received the data bit signal.
9. Lag synchronization data receiver as claimed in claim 8, wherein the resistance circuit includes two resistance, this two
The resistance ratio of resistance indicates the retardation.
10. Lag synchronization data receiver as claimed in claim 9, wherein two resistance include a first resistor and one
Second resistance, the first resistor are coupled to a ground reference, which is coupled to a reference voltage, and two electricity
Resistance is coupled against each other in a node, which exports the ratio signal.
11. Lag synchronization data receiver as claimed in claim 8, the wherein phase delay of data bit signal delay
Amount, and the range of the retardation is the half period of never phase delay a to data-strobe signal.
12. Lag synchronization data receiver as claimed in claim 11, wherein the delayed data position signal and data choosing
Communication number is transmitted to a synchronous receiver, state of the synchronous receiver to detect the delayed data position signal.
13. Lag synchronization data receiver as claimed in claim 12, wherein microprocessor is coupled to a motherboard, the electricity
Resistance circuit is coupled to the motherboard, which inputs the microprocessor by an additional pin.
14. Lag synchronization data receiver as claimed in claim 8, wherein the ratio signal is distributed into the microprocessor
Multiple delay locked loops, each delay locked loop correspond to the data group in relevant data bit signal.
15. a kind of method of the misalignment on compensation synchronous data bus, comprising:
A ratio signal is provided by a resistance circuit, which indicates a retardation, have to delay with a data group
The data bit signal closed, wherein the data bit signal is sent by a transmitting device together with a data-strobe signal；And
The data bit signal and the data-strobe signal are received in a synchronous receiver, the reception includes:
A delay locked loop is coupled to the ratio signal, makes the delay locked loop that the retardation is added to data bit news
Number, to generate a delayed data position signal, wherein the delayed data position signal is relative to the data-strobe signal with the retardation
Delay, so that the synchronous receiver can be properly received the data bit signal.
16. as claimed in claim 15 compensation synchronous data bus on misalignment method, wherein the resistance circuit include
Two resistance, the resistance ratio of two resistance indicate the retardation.
17. as claimed in claim 16 compensation synchronous data bus on misalignment method, wherein two resistance include
One first resistor and a second resistance, the first resistor are coupled to a ground reference, which is coupled to a reference
Voltage, and two resistance are coupled against each other in a node, which exports the ratio signal.
18. the method for the misalignment on compensation synchronous data bus as claimed in claim 15, the wherein data bit signal
The phase delay retardation, and the range of the retardation is the half period of never phase delay a to data-strobe signal.
19. the method for the misalignment on compensation synchronous data bus as claimed in claim 18, wherein the delayed data position is interrogated
Number and the data-strobe signal be transmitted to a synchronous receiver, shape of the synchronous receiver to detect the delayed data position signal
State.
20. the method for the misalignment on compensation synchronous data bus as claimed in claim 19, the wherein delay locked loop
And the synchronous receiver is arranged in a device, which is coupled to a motherboard, which is coupled to the motherboard, should
Ratio signal inputs the device by an additional pin.
21. the method for the misalignment on compensation synchronous data bus as claimed in claim 15, wherein the ratio signal is distributed
To multiple delay locked loops, each delay locked loop corresponds to the relevant data bit signal in the data group.
Applications Claiming Priority (15)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/165,679 US8839018B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for optimizing a synchronous data bus |
| US13/165,665 | 2011-06-21 | ||
| US13/165,659 US8782460B2 (en) | 2011-06-21 | 2011-06-21 | Apparatus and method for delayed synchronous data reception |
| US13/165,659 | 2011-06-21 | ||
| US13/165,650 | 2011-06-21 | ||
| US13/165,664 US8751850B2 (en) | 2011-06-21 | 2011-06-21 | Optimized synchronous data reception mechanism |
| US13/165,665 US8751851B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for synchronous strobe advance |
| US13/165,671 US8751852B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for delayed synchronous data reception |
| US13/165,654 | 2011-06-21 | ||
| US13/165,679 | 2011-06-21 | ||
| US13/165,650 US8782459B2 (en) | 2011-06-21 | 2011-06-21 | Apparatus and method for advanced synchronous strobe transmission |
| US13/165,671 | 2011-06-21 | ||
| US13/165,654 US8683253B2 (en) | 2011-06-21 | 2011-06-21 | Optimized synchronous strobe transmission mechanism |
| US13/165,664 | 2011-06-21 | ||
| CN201210211885.0A CN102799551B (en) | 2011-06-21 | 2012-06-21 | The Apparatus for () and method therefor of synchronous selection pass transmission in advance |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210211885.0A Division CN102799551B (en) | 2011-06-21 | 2012-06-21 | The Apparatus for () and method therefor of synchronous selection pass transmission in advance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105868150A CN105868150A (en) | 2016-08-17 |
| CN105868150B true CN105868150B (en) | 2019-02-01 |
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ID=47198664
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610184151.6A Active CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610184153.5A Active CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182760.8A Active CN105868150B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data receiver and its method |
| CN201610182788.1A Active CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183487.0A Active CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182769.9A Active CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201210211885.0A Active CN102799551B (en) | 2011-06-21 | 2012-06-21 | The Apparatus for () and method therefor of synchronous selection pass transmission in advance |
| CN201610183496.XA Active CN105868152B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data bit transmission device and its method |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610184151.6A Active CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610184153.5A Active CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
Family Applications After (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610182788.1A Active CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183487.0A Active CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182769.9A Active CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
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| KR102455370B1 (en) * | 2018-04-17 | 2022-10-18 | 에스케이하이닉스 주식회사 | Transmitting circuit improving data eye, semiconductor apparatus and semiconductor system including the same |
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| TW201301048A (en) | 2013-01-01 |
| CN105808484A (en) | 2016-07-27 |
| CN105868152A (en) | 2016-08-17 |
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| CN105808483B (en) | 2018-11-02 |
| CN105868151B (en) | 2018-11-27 |
| CN105868152B (en) | 2018-11-27 |
| TWI482030B (en) | 2015-04-21 |
| CN102799551B (en) | 2016-04-20 |
| CN102799551A (en) | 2012-11-28 |
| CN105808484B (en) | 2019-02-01 |
| CN105893310B (en) | 2019-04-26 |
| CN105808485A (en) | 2016-07-27 |
| CN105868150A (en) | 2016-08-17 |
| CN105808483A (en) | 2016-07-27 |
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| CN105868151A (en) | 2016-08-17 |
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