CN105845570A - Fin-type field effect transistor and forming method therefor - Google Patents
Fin-type field effect transistor and forming method therefor Download PDFInfo
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- CN105845570A CN105845570A CN201510016784.1A CN201510016784A CN105845570A CN 105845570 A CN105845570 A CN 105845570A CN 201510016784 A CN201510016784 A CN 201510016784A CN 105845570 A CN105845570 A CN 105845570A
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin-type field effect transistor and a forming method therefor. The method comprises the steps: providing a semiconductor substrate which is provided with at least two separated bulged structures, wherein each bulged structure is provided with a pad oxidation layer and a mask layer located on the pad oxidation layer; forming blocking layers on side walls of the bulged structure, a side wall of the pad oxidation layer, and the side walls and tops of the mask layers; forming insulating layers on the blocking layers between the adjacent bulged structures, wherein the insulating layers are lower than the bulged structures; carrying out the channel cutoff ion injection of the mask layers, the pad oxidation layers and the bulged structures, and forming a channel cutoff ion injection layer. The method provided by the invention can improve the performance of the fin-type field effect transistor.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to fin formula field effect transistor and forming method thereof.
Background technology
Along with semiconductor industry is to the development of lower technology node, gradually start from planar CMOS transistor
To three-dimensional fin formula field effect transistor (FinFET) transition.In FinFET, grid structure at least can be from
Raceway groove is controlled by both sides, has the grid more much better than than the planar MOSFET devices control energy to raceway groove
Power, it is possible to well suppress short-channel effect.And other device has more preferable and existing collection relatively
Become the compatibility of circuit production technology.
Referring to figs. 1 to Fig. 7, the forming method of fin field effect nmos pass transistor of the prior art is as follows:
With reference to Fig. 1 and Fig. 2, it is provided that silicon substrate 100, described silicon substrate has the projection that at least two is discrete
Structure 101, described bulge-structure has pad oxide 102 and the mask being positioned on described pad oxide 102
Layer 103.Wherein, the material of pad oxide 102 is silicon oxide, and the material of mask layer 103 is silicon nitride.
With reference to Fig. 3, the Semiconductor substrate 10 between adjacent bulge-structure 101 forms insulation material layer
104a, the material of insulating layer material layer 104a is silicon oxide.
Then, with reference to Fig. 4, the method for cmp is used to will be above the insulation material on mask layer 103
Bed of material 104a removes.
Then, with reference to Fig. 5, use the method for wet etching to carry out back insulation material layer 104a carving, formed
Insulating barrier 104, the height of described insulating barrier 104 is less than bulge-structure 101.Higher than described insulating barrier 104
Bulge-structure is fin 105.
Then, with reference to Fig. 6 and Fig. 7, fin 105 is carried out channel cutoff ion implanting, at described protruding knot
Structure 101 be internally formed channel cutoff ion implanted layer 106 (channel stop layer).
But, the performance using the fin formula field effect transistor of the method formation of prior art is the best.
Summary of the invention
The problem that the present invention solves is the property of the fin formula field effect transistor using the method for prior art to be formed
Can not be good.
For solving the problems referred to above, the present invention provides the forming method of a kind of fin formula field effect transistor, including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has the bulge-structure that at least two is discrete, described
There is on bulge-structure pad oxide and the mask layer being positioned on described pad oxide；
Sidewall, the sidewall of described pad oxide, the sidewall of described mask layer and top at described bulge-structure
Formation barrier layer, portion；
Forming insulating barrier on described barrier layer between adjacent protrusion structure, described insulating barrier is less than described
Bulge-structure；
Described mask layer, described pad oxide and described bulge-structure are carried out channel cutoff ion implanting,
Form channel cutoff ion implanted layer.
Optionally, the material on described barrier layer is silicon nitride.
Optionally, the method forming described barrier layer is ald or chemical gaseous phase deposition.
Optionally, the thickness on described barrier layer is more than or equal to 10 angstroms and less than or equal to 30 angstroms.
Optionally, before forming described insulating barrier, described barrier layer forms protective layer.
Optionally, the material of described protective layer is silicon oxide.
Optionally, before forming described barrier layer, at sidewall, the described pad oxide of described bulge-structure
Sidewall, the sidewall of described mask layer and top form stress-buffer layer.
Optionally, the material of described stress-buffer layer is silicon oxide.
Optionally, described bulge-structure have pad oxide and the mask layer being positioned on described pad oxide
Forming method include:
Form pad oxide material layer on the semiconductor substrate and be positioned on described pad oxide material layer
The mask layer of patterning；
With the mask layer of described patterning as mask, it is sequentially etched the half of described pad oxide and partial depth
Conductor substrate.
Optionally, the material of described pad oxide is silicon oxide.
Optionally, the material of described mask layer is silicon nitride.
Optionally, the material of described insulating barrier is silicon oxide.
The present invention also provides for a kind of fin formula field effect transistor, including:
There is the Semiconductor substrate of the discrete bulge-structure of at least two；
The insulating barrier in Semiconductor substrate between described adjacent bulge-structure, described insulating barrier is low
In described bulge-structure；
There is inside described bulge-structure channel cutoff ion implanted layer；
Between described insulating barrier and described bulge-structure, there is barrier layer.
Optionally, the material on described barrier layer is silicon nitride.
Optionally, between described bulge-structure and described barrier layer, there is stress-buffer layer.
Optionally, between described insulating barrier and described barrier layer, there is protective layer.
Compared with prior art, technical scheme has the advantage that
During forming insulating barrier, barrier layer is possible to prevent pad oxide to rupture, and then prevents from being positioned at pad
Mask layer on oxide layer falls to be formed on insulating barrier particulate matter (particles), it is to avoid this particulate matter shadow
Hole phenomenon occurs in ringing insulating barrier, thus improves the performance of the fin formula field effect transistor being subsequently formed.
It addition, just because of the protection on barrier layer, the pad oxide at fin top is just not damaged, and is positioned at pad
Mask layer on oxide layer does not falls out yet.To described mask layer, described pad oxide and described projection
When structure carries out channel cutoff ion implanting, due to the stop of mask layer, can avoid in bulge-structure
The channel cutoff ion concentration of channel region can be excessive, existing to reduce the scattering that channel cutoff ion produces
As, thus increase the mobility in electronics or hole, and then improve the fin formula field effect transistor being subsequently formed
The speed of service.
Further, the concentration that bulge-structure carries out channel cutoff ion implanting is certain, at ditch
Channel cutoff ion concentration in region, road is reduced, so, and the raceway groove in channel cutoff ion implanted layer
The concentration of cut-off ion will increase, and prevents from occurring break-through (punch through) effect more preferable bottom fin,
Further increase the performance of the fin formula field effect transistor being subsequently formed.
Accompanying drawing explanation
Fig. 1 is the vertical of the Semiconductor substrate with bulge-structure, pad oxide and mask layer of prior art
Body structural representation；
Fig. 2 is the Fig. 1 cross-sectional view along AA direction；
Fig. 3 to Fig. 7 is that the method for the employing prior art after the step of Fig. 2 forms fin field effect
The cross-sectional view of each step of transistor；
Fig. 8 includes Fig. 8 (a) and Fig. 8 (b), during wherein Fig. 8 (a) is prior art, through raceway groove
The bulge-structure of cut-off ion implanting and the cross-sectional view of the insulating barrier between bulge-structure,
Fig. 8 (b) is that the bulge-structure through channel cutoff ion implanting in Fig. 8 (a) is along BB directional profile
Interior channel cutoff ion concentration distribution schematic diagram；
Fig. 9 is the quasiconductor with bulge-structure, pad oxide and mask layer of the specific embodiment of the invention
The perspective view of substrate；
Figure 10 is the Fig. 9 cross-sectional view along CC direction；
Figure 11 to Figure 17 is that the method for the employing specific embodiment of the invention after the step of Figure 10 is formed
The cross-sectional view of each step of fin formula field effect transistor；
Figure 18 includes Figure 18 (a) and Figure 18 (b), and wherein Figure 18 (a) is the specific embodiment of the invention
In, through the bulge-structure of channel cutoff ion implanting and the section of the insulating barrier between bulge-structure
Structural representation, Figure 18 (b) is the bulge-structure through channel cutoff ion implanting in Figure 18 (a)
Channel cutoff ion concentration distribution schematic diagram along DD directional profile.
Detailed description of the invention
The reason that the performance of the fin formula field effect transistor that the method for employing prior art is formed is the best is as follows:
With reference to Fig. 5, the material of insulation material layer is silicon oxide.Wet etching is isotropic etching, uses
During insulation material layer 104a is carried out back carving by the method for wet etching, also can be by pad identical for material
Oxide layer 102 is corroded and is ruptured.So, it is positioned at the mask layer 103 on pad oxide 102 can drop
To by the insulation material layer 104a of wet etching, form particulate matter (particles), this particulate matter
Affect the formation quality of insulating barrier 104, such as, hole phenomenon can occur in insulating barrier 104, thus
Affect the isolation effect of insulating barrier 104, and then impact is subsequently formed the performance of fin formula field effect transistor.
It addition, with reference to Fig. 6 to Fig. 8, due to the dropping of mask layer 103 at fin 105 top, can be directly
The injection of channel cutoff ion is carried out to fin 105.So, channel region A in fin 105
Channel cutoff ion concentration can be excessive, has a following impact:
(1) scattering phenomenon that the channel cutoff ion that concentration is the biggest produces is the most, electronics or the migration in hole
Rate is the lowest, thus affects the speed of service of the fin formula field effect transistor being subsequently formed.
(2) refer to Fig. 8, Fig. 8 (a) is the partial schematic diagram of a bulge-structure 101 in Fig. 7.
Curve 81 in Fig. 8 (b) is the ditch in channel region A (bottom fin 105 top to fin 105)
Road cut-off ion concentration distribution curve.Curve 82 in Fig. 8 (b) is channel cutoff ion implanted layer 106
In channel cutoff ion concentration distribution curve.The value of each point on curve 81 is above 1018cm-3,
Maximum can reach 5 × 1018cm-3.Maximum on curve 82 is 5 × 1018cm-3.Therefore, to fin
105 concentration carrying out channel cutoff ion implanting are certain, if the raceway groove in channel region A cuts
Only ion concentration is excessive, so, in channel cutoff ion implanted layer 106 (with reference to Fig. 7 or Fig. 8 (a))
The concentration of channel cutoff ion will lack, thus prevent from occurring bottom fin 105 break-through (punch
Through) poor effect of phenomenon, affects the performance of the fin formula field effect transistor being subsequently formed further.
In order to solve above-mentioned technical problem, the present invention provides the forming method of a kind of fin formula field effect transistor,
The fin formula field effect transistor performance using the method for the present invention to be formed can increase.
Understandable, below in conjunction with the accompanying drawings to this for enabling the above object and advantages of the present invention to become apparent from
Bright specific embodiment is described in detail.
With reference to Fig. 9 and Figure 10, it is provided that Semiconductor substrate 200, described Semiconductor substrate 200 has at least
Two discrete bulge-structures 201.There is on described bulge-structure 201 pad oxide 202 and be positioned at described
Mask layer 203 on pad oxide 202.Concrete forming method is as follows:
In the present embodiment, Semiconductor substrate 200 is silicon substrate.In other embodiments, Semiconductor substrate is also
Can be germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its laminated construction, or gold
Hard rock substrate, or well known to a person skilled in the art other semiconductive material substrate.
Form pad layer of oxidized material on semiconductor substrate 200.The material of described pad layer of oxidized material is oxygen
SiClx.The method forming pad layer of oxidized material is furnace oxidation or insitu moisture generation oxidizing process (in-situ
Steam generation, ISSG).
After forming pad layer of oxidized material, pad layer of oxidized material forms the mask layer 203 of patterning.This reality
Executing in example, the material of the mask layer 203 of patterning is silicon nitride.
With the mask layer 203 of patterning as mask, it is sequentially etched the half of pad layer of oxidized material and partial depth
Conductor substrate.The bulge-structure 201 that at least two is discrete is formed in remaining Semiconductor substrate.Remaining pad
Layer of oxidized material is the pad oxide 202 on bulge-structure 201.
Then, with reference to Figure 11, at described Semiconductor substrate 200, the sidewall of bulge-structure 201, pad oxygen
Change the sidewall of layer 202, the sidewall of mask layer 203 and top and form stress-buffer layer 204.
In the present embodiment, the material of stress-buffer layer 204 is silicon oxide.Stress-buffer layer 204 main
It act as: in subsequent technique, need to be formed barrier layer, this stress-buffer layer on stress-buffer layer 204
204 is the stress-buffer layer on barrier layer.Existence without stress-buffer layer 204.Barrier layer can be to convex
Playing structure 201 and produce bigger stress, the size adding bulge-structure 201 is less, this bigger stress meeting
The silicon in bulge-structure 201 is made to produce dislocation.Furthermore, the barrier layer being subsequently formed also can be made in projection
The corner of structure cracks, and easily makes to form insulating barrier in subsequent technique and produces space etc. in this place,
Thus have a strong impact on the performance of the fin formula field effect transistor being subsequently formed.
In the present embodiment, the thickness of stress-buffer layer 204 is more than or equal to 25 angstroms and less than or equal to 40 angstroms,
If the thickness of stress-buffer layer 204 is too big, in subsequent process steps, adjacent bulge-structure 201 it
Between depth-to-width ratio too big, the inside of the insulation material layer filled between adjacent bulge-structure 201 has
Space.If the thickness of stress-buffer layer 204 is the least, the stress buffer poor effect to barrier layer, no
Can effectively avoid the dislocation defects produced in bulge-structure 201, can not be prevented effectively from and tie in projection
Structure 201 corner cracks defect.
The method forming stress-buffer layer 204 is that insitu moisture generates oxidizing process (in-situ steam
Generation, ISSG).Insitu moisture generates oxidizing process, it is possible to form the stress-buffer layer that thickness is the thinnest
204.It should be noted that formed at sidewall, the sidewall of mask layer 203 and the top of pad oxide 202
The thickness of stress-buffer layer less than the thickness of stress-buffer layer formed at bulge-structure 201 sidewall.
In other embodiments, it would however also be possible to employ chemical vapour deposition technique (CVD).
In other embodiments, it would however also be possible to employ atom deposition method (ALD) forms stress-buffer layer, simply
Cost is slightly higher.
In other embodiments, it would however also be possible to employ high-temperature oxidation (High Temperature Oxidation,
HTO) stress-buffer layer is formed.But the ion that the highest meeting of the temperature of this oxidizing process is to the well region in substrate
Distribution produces impact.
In the present embodiment, the method forming stress-buffer layer is preferably insitu moisture generation oxidizing process.On-the-spot
Steam generates oxidizing process, is not limited by the crystal orientation of the Semiconductor substrate between bulge-structure sidewall and bulge-structure
System, the stress-buffer layer that can be formed in the Semiconductor substrate between bulge-structure sidewall and bulge-structure
The thickness of 204 can be the most equal, and then can make the stress-buffer layer even action of formation.Furthermore, use
Insitu moisture generates oxidizing process, it is possible to form the stress-buffer layer 204 that thickness is the thinnest.
In other embodiments, it would however also be possible to employ chemical vapour deposition technique (CVD).But, use chemistry gas
The stress-buffer layer that phase sedimentation is formed Semiconductor substrate between the sidewall and bulge-structure of bulge-structure
Between variable thickness cause.Therefore, the buffering using the stress-buffer layer of chemical vapour deposition technique formation is made
With the most uniform.
In other embodiments, it would however also be possible to employ atom deposition method (ALD) forms stress-buffer layer, simply
Cost is slightly higher.
In other embodiments, it would however also be possible to employ high-temperature oxidation (HTO) forms stress-buffer layer.But
The highest meeting of temperature of this oxidizing process produces impact to the ion distribution of the well region in substrate.
In other embodiments, it is formed without stress-buffer layer and falls within protection scope of the present invention, follow-up
Form the poor performance of fin formula field effect transistor.
Then, with reference to Figure 12, described stress-buffer layer 204 forms barrier layer 205.
In the present embodiment, the material on barrier layer 205 is silicon nitride.
The method forming barrier layer 205 is ald.Because the method for ald can be protected
The thickness on card barrier layer 205 is sufficiently thin, and, under the thinnest depth information, moreover it is possible to ensure barrier layer
The uniformity of 205.
In the present embodiment, the thickness on barrier layer 205 is more than or equal to 10 angstroms and less than or equal to 30 angstroms.
Then, with continued reference to Figure 12, barrier layer 205 forms protective layer 206.
In the present embodiment, the material of protective layer 206 is silicon oxide.
Acting as of protective layer 206: in the technique being subsequently formed insulation material layer, protective layer 206 is protected
The thickness protecting barrier layer 205 will not be reduced.Particularly as follows: in subsequent technique, the material of insulation material layer
For silicon oxide.It is flowing chemistry in the method for fill insulant layer between adjacent bulge-structure 201
Vapour deposition process (Flowable Chemical Vapor Deposition, FCVD), the insulant of formation
Surfacing and the inside of layer do not have space.But, the insulation material layer of formation the most loose, it is impossible to
It is applied to fin formula field effect transistor.Accordingly, in order to increase the consistency of fill insulant layer to increase
Add the mechanical performance of insulation material layer, it is necessary to insulation material layer is made annealing treatment.If do not stopped
Forming protective layer 206 on layer 205, in described annealing process, the steam of release can make barrier layer 205
React, thus the barrier layer 205 that meeting attacking material is silicon nitride, make the thickness on barrier layer 205 reduce,
So, barrier layer 205 does not just have corresponding barrier effect.
In the present embodiment, the thickness of protective layer 206 is more than or equal to 10 angstroms and less than or equal to 20 angstroms, as
Really the thickness of protective layer 206 is too big, in subsequent process steps, and deep between adjacent bulge-structure 201
Wide bigger than too, the inside of the insulating barrier formed between adjacent bulge-structure 201 has space.If
The thickness of protective layer 206 is the least, can not be effectively protected the barrier layer under it.
In the present embodiment, the method forming protective layer 206 is that rapid heat chemical deposits (RTCVD).Formed
Protective layer 206 good evenness.And it is relatively thin.In other embodiments, it would however also be possible to employ ALD oxidizing process,
Simply cost is high, but falls within protection scope of the present invention.
It should be noted that the method for thermal oxide growth can not be used to form protective layer 206, because protective layer
The bottom of 206 is silicon nitride.
Then, with reference to Figure 13, protective layer 206 forms insulation material layer 208a, insulation material layer 208a
Higher than bulge-structure 201.
In the present embodiment, the material of insulation material layer 208a is silicon oxide.Two adjacent bulge-structures 201
Between depth-to-width ratio the biggest.Insulation is filled between the adjacent bulge-structure 201 the biggest to depth-to-width ratio
The method of material layer 208a for flowing chemistry vapour deposition (Flowable Chemical Vapor Deposition,
FCVD).The surfacing and the inside that use the insulation material layer of flowing chemistry vapour deposition formation are not free
Gap.But, the insulation material layer of formation the most loose, it is impossible to be applied to fin formula field effect transistor.
Accordingly, in order to increase the consistency mechanical performance with increase insulation material layer of fill insulant layer,
Insulation material layer must be made annealing treatment.If not forming protective layer 206, institute on barrier layer 205
State the steam of release in annealing process to react with barrier layer, thus can attacking material be nitrogen
The barrier layer 205 of SiClx, makes the thickness on barrier layer 205 reduce, it is impossible to play the effect on barrier layer 205.
In other embodiments, the method forming insulation material layer can also fill out ditch technique (High for high depth ratio
Aspect Ratio Process, HARP), use high depth ratio to fill out ditch technique and form the process of insulation material layer
In, also damage can be caused in barrier layer so that it is thickness reduces.Therefore, it is also desirable to it is carried out by protective layer
Covering protection its formed during insulation material layer injury-free.
In other embodiments, if using high-density plasma (High Density Plasma, HDP)
Method form insulation material layer, the thickness on barrier layer will not be reduced.But, the insulant of formation
The inside of layer has space.Fall within protection scope of the present invention.
Then, with reference to Figure 14, the method for cmp is used to will be above the insulation material of mask layer 203
Bed of material 208a removes.
Then, with reference to Figure 15, return and carve insulation material layer 208a, form insulating barrier 208.Insulating barrier 208
Height less than bulge-structure 201.
In the present embodiment, the method returning insulation material layer 208a at quarter includes: initially with the side of wet etching
Insulation material layer 208a etching removal height H1, this height H1 are accounted for by method to be needed to remove total height
20%～40%.Then, use Siconi lithographic method to continue etching and remove the insulation material layer of height H2
208a, this height H2 account for be needed to remove the 60%～80% of total height, forms insulating barrier 208.Wherein, wet
The wet etching agent of method corrosion is diluted hydrofluoric acid.
If it should be noted that all using the method for wet etching to perform etching insulation material layer 208a
Form insulating barrier, then, on full wafer wafer, the densely distributed district of device can etch the insulant of less thickness
Layer 208a.Device distribution rarefaction can etch the insulation material layer 208a of more thickness.Therefore, full wafer is brilliant
On circle, etching is removed after portions of insulating material layer 208a, the insulating barrier 208 of formation in uneven thickness,
Thus affect the performance of the fin formula field effect transistor being subsequently formed.
If insulation material layer 208a uses Siconi lithographic method etching form insulating barrier 208, then
Process costs is the highest.
Therefore, the etching bar that the wet etching method of the present embodiment combines is used with Siconi lithographic method
The thickness of the insulating barrier 208 that part is formed is uniform, surfacing, and technique production cost is minimum.
In the present embodiment, during above-mentioned etching condition removes the insulation material layer 208a of Partial Height,
Protective layer 206 also can be removed substantially simultaneously, and remaining protective layer 206 is equal to the height of insulating barrier 208.
After forming insulating barrier 208, it is fin 209 higher than the bulge-structure 201 of insulating barrier.
Then, with reference to Figure 16, to described mask layer 203, described pad oxide 202 and described protruding knot
Structure 201 carries out channel cutoff ion implanting, forms channel cutoff ion implanted layer 210.
In the present embodiment, bulge-structure 201 is carried out ion implanting in order to be formed in the bottom of fin 209
Channel cutoff ion implanted layer 210.The transistor being subsequently formed is fin field effect nmos pass transistor,
The injection ion of described ion implanting is boron ion.
In the present embodiment, why form channel cutoff ion implanted layer 210 in the bottom of fin 209, former
Because of as follows: the size of fin 209 is the least, therefore, except fin part above bottom fin 209
All it is completely depleted.But, the bottom of fin 209 is closest with substrate, therefore, at fin 209
Bottom cannot be formed completely depleted.Accordingly, it would be desirable to form channel cutoff ion in the bottom of fin 209
Implanted layer 210, is otherwise very easy to make to wear bottom the fin of the fin formula field effect transistor being subsequently formed
Logical (punch through) phenomenon.Thus have a strong impact on the performance of the fin formula field effect transistor being subsequently formed.
In the present embodiment, the effect on barrier layer 205 is as follows:
In conjunction with reference to Figure 14 and Figure 15, the material of insulation material layer 208a is silicon oxide.Wet etching is
Isotropic etching, during using the method for wet etching to carry out back insulation material layer 208a carving,
Without the existence on barrier layer 205, this wet corrosion technique can be by pad oxide 202 identical for material
Corrode and rupture.Therefore, barrier layer 205 is possible to prevent the mask layer 203 being positioned on pad oxide 202
Because the fracture of pad oxide 202 can fall to be formed on the insulation material layer 208a of wet etching
Particulate matter (particles), it is to avoid this particulate matter affects the formation quality of insulating barrier 208, such as, it is to avoid meeting
Hole phenomenon occurs in insulating barrier 208, thus improves the property of the fin formula field effect transistor being subsequently formed
Energy.
It addition, with reference to Figure 16, just because of the protection on barrier layer 205, the pad oxide at fin 209 top
202 are just not damaged, and are positioned at the mask layer 203 on pad oxide 202 and also do not fall out.The present embodiment
In, with reference to Figure 18, to described mask layer 203, described pad oxide 202 and described bulge-structure 201
Carrying out channel cutoff ion implanting, the reason forming channel cutoff ion implanted layer 210 is as follows:
(1) due to the stop of mask layer 203, the ditch of channel region A in fin 209 can be avoided
Road cut-off ion concentration can be excessive, to reduce the scattering phenomenon that channel cutoff ion produces, thus increases electricity
Son or the mobility in hole, and then improve the speed of service of the fin formula field effect transistor being subsequently formed.
(2) concentration that fin 209 is carried out channel cutoff ion implanting is certain, at channel region B
In channel cutoff ion concentration be reduced, so, channel cutoff ion implanted layer 210 (with reference to Figure 16)
The concentration of interior channel cutoff ion will increase, and prevents from occurring bottom fin 209 break-through (punch
Through) effect is more preferable, further increases the performance of the fin formula field effect transistor being subsequently formed.
Specifically refer to Figure 18, Figure 18 (a) is the partially schematic of a bulge-structure 201 in Figure 16
Figure.Curve 181 in Figure 18 (b) is channel region B (bottom fin 209 top to fin 209)
In channel cutoff ion concentration distribution curve.Curve 182 in Figure 18 (b) is noted for channel cutoff ion
Enter the channel cutoff ion concentration distribution curve in layer 210.The numerical value of each point on curve 181 is basic
It is all 1018cm-3, much smaller than the numerical value on the curve 181 in Fig. 8 (b) of the prior art.Figure 18
B the greatest measure on curve 182 in () can be 1019cm-3, much larger than Fig. 8 (b) of the prior art
In curve 82 on greatest measure.
(3) for fin field effect nmos pass transistor, the injection ion of channel cutoff ion implanting
For boron ion, boron ion is high in the solid solubility of insulating barrier 208, and boron ion is very easy to diffuse to surrounding
In insulating barrier 208.But, in the present embodiment, barrier layer 205 can stop channel cutoff ion implanting
Substantial amounts of boron ion in layer 210 diffuses in the insulating barrier 208 of surrounding, thus is further ensured that raceway groove
The ion concentration of cut-off ion implanted layer 210, is further ensured that the fin field effect NMOS being subsequently formed
Punch through, the fin field effect NMOS crystal being subsequently formed with raising is there is bottom the fin of transistor
The performance of pipe.
It should be noted that in the present embodiment, the thickness on barrier layer 205 is more than or equal to 10 angstroms and to be less than
Equal to 30 angstroms.If the thickness on barrier layer 205 is too big, in subsequent process steps, adjacent bulge-structure
Depth-to-width ratio between 205 is too big, though the method using flowing chemistry vapour deposition, at adjacent protruding knot
The inside of the insulating barrier formed between structure 201 has space.If the thickness on barrier layer 205 is the least, right
The blocking effect of boron ion is the best.
In other embodiments, if the type of fin field-effect transistor is p-type, then formed channel cutoff from
The injection ion of sub-implanted layer is arsenic ion.Although arsenic ion is less in the solid solubility of insulating barrier, but resistance
Barrier also can stop the diffusion of arsenic ion, beneficially improves the property of the fin formula field effect transistor being subsequently formed
Can, fall within protection scope of the present invention.
Then, with reference to Figure 17, after forming channel cutoff ion implanted layer 210, mask layer 203 He is removed
Barrier layer 205 higher than insulating barrier 208.So, the height on remaining barrier layer 205 is equal to insulating barrier
The height of 208.
After removing mask layer 203 and barrier layer 205, removal pad oxide layer 202 (with reference to Figure 16) and
Stress-buffer layer 204 higher than insulating barrier 208.So, the height of remaining stress-buffer layer 204 is equal to
The height of insulating barrier 208.
With reference to Figure 17, the present invention also provides for a kind of fin formula field effect transistor, including:
There is the Semiconductor substrate 200 of the discrete bulge-structure of at least two 201；
The insulating barrier 208 in Semiconductor substrate between described adjacent bulge-structure 201, described absolutely
Edge layer 208 is less than described bulge-structure 201；
Described bulge-structure 201 is internal has channel cutoff ion implanted layer 210,
Between described insulating barrier 208 and described bulge-structure 201, there is barrier layer 205.
In the present embodiment, the material on described barrier layer 205 is silicon nitride.
In the present embodiment, between described bulge-structure 201 and described barrier layer 205, there is stress-buffer layer
204。
In the present embodiment, between described insulating barrier 208 and described barrier layer 205, there is protective layer 206.
In the present embodiment, the injection ion of described ion implanting includes boron ion, and described fin field effect is brilliant
The type of body pipe is N-type.
In other embodiments, the injection ion of described ion implanting includes arsenic ion, described fin field effect
The type of transistor is p-type.
Specifically refer to embodiment of the method.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (16)
1. the forming method of a fin formula field effect transistor, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has the bulge-structure that at least two is discrete, described convex
Rise and there is in structure pad oxide and the mask layer being positioned on described pad oxide；
Sidewall, the sidewall of described pad oxide, the sidewall of described mask layer and top at described bulge-structure
Form barrier layer；
Forming insulating barrier on described barrier layer between adjacent protrusion structure, described insulating barrier is less than described convex
Play structure；
Described mask layer, described pad oxide and described bulge-structure are carried out channel cutoff ion implanting, shape
Become channel cutoff ion implanted layer.
2. the method for claim 1, it is characterised in that the material on described barrier layer is silicon nitride.
3. method as claimed in claim 2, it is characterised in that the method forming described barrier layer is atomic layer
Deposition or chemical gaseous phase deposition.
4. the method for claim 1, it is characterised in that the thickness on described barrier layer is more than or equal to 10
Angstrom and less than or equal to 30 angstroms.
5. the method for claim 1, it is characterised in that before forming described insulating barrier, in described resistance
Protective layer is formed in barrier.
6. method as claimed in claim 5, it is characterised in that the material of described protective layer is silicon oxide.
7. the method for claim 1, it is characterised in that before forming described barrier layer, described convex
Play the sidewall of structure, the sidewall of described pad oxide, the sidewall of described mask layer and top and form stress
Cushion.
8. method as claimed in claim 7, it is characterised in that the material of described stress-buffer layer is silicon oxide.
9. the method for claim 1, it is characterised in that have on described bulge-structure pad oxide and
The forming method being positioned at the mask layer on described pad oxide includes:
Form pad oxide material layer and the figure being positioned on described pad oxide material layer on the semiconductor substrate
The mask layer of case；
With the mask layer of described patterning as mask, it is sequentially etched the quasiconductor of described pad oxide and partial depth
Substrate.
10. the method for claim 1, it is characterised in that the material of described pad oxide is silicon oxide.
11. the method for claim 1, it is characterised in that the material of described mask layer is silicon nitride.
12. the method for claim 1, it is characterised in that the material of described insulating barrier is silicon oxide.
13. 1 kinds of fin formula field effect transistors, including:
There is the Semiconductor substrate of the discrete bulge-structure of at least two；
The insulating barrier in Semiconductor substrate between described adjacent bulge-structure, described insulating barrier is less than institute
State bulge-structure；
There is inside described bulge-structure channel cutoff ion implanted layer；
It is characterized in that, between described insulating barrier and described bulge-structure, there is barrier layer.
14. transistors as claimed in claim 13, it is characterised in that the material on described barrier layer is silicon nitride.
15. transistors as claimed in claim 13, it is characterised in that described bulge-structure and described barrier layer it
Between there is stress-buffer layer.
16. transistors as claimed in claim 13, it is characterised in that between described insulating barrier and described barrier layer
There is protective layer.
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| US20040256683A1 (en) * | 2003-06-20 | 2004-12-23 | Deok-Hyung Lee | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations and methods of fabricating same |
| US20050269629A1 (en) * | 2004-03-23 | 2005-12-08 | Chul Lee | Fin field effect transistors and methods of fabricating the same |
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| US20090111239A1 (en) * | 2007-10-29 | 2009-04-30 | Kyu Sung Kim | Method for manufacturing semiconductor device |
| CN103137542A (en) * | 2011-11-30 | 2013-06-05 | 台湾积体电路制造股份有限公司 | Uniform shallow trench isolation regions and the method of forming the same |
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| US7214991B2 (en) * | 2002-12-06 | 2007-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS inverters configured using multiple-gate transistors |
| US20040256683A1 (en) * | 2003-06-20 | 2004-12-23 | Deok-Hyung Lee | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations and methods of fabricating same |
| US20050269629A1 (en) * | 2004-03-23 | 2005-12-08 | Chul Lee | Fin field effect transistors and methods of fabricating the same |
| US20090111239A1 (en) * | 2007-10-29 | 2009-04-30 | Kyu Sung Kim | Method for manufacturing semiconductor device |
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