CN105843986A - FPGA-based control system capable of automatically extending address - Google Patents
FPGA-based control system capable of automatically extending address Download PDFInfo
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- CN105843986A CN105843986A CN201610143865.2A CN201610143865A CN105843986A CN 105843986 A CN105843986 A CN 105843986A CN 201610143865 A CN201610143865 A CN 201610143865A CN 105843986 A CN105843986 A CN 105843986A
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- address
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- fpga
- control system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The invention relates to a FPGA-based control system capable of automatically extending the address. The system includes an address generation module, multiple address decoding modules and multiple address control modules. Each column corresponds to one address decoding module, and each row corresponds to one address control module. The address generation module generates one address, and the address is transmitted to each address decoding module via a first bus. The address decoding module receives the address, and then compares the received address with the address of the address decoding module to decode an address open Word Line, and finally returns a signal to the address control module. The address control module judges whether the current line has a signal or not, and transmits the signal to the address generation module via a second bus, and the address generation module resets or add 1 to a corresponding part of the address according to the signal. The control system is used for configuring data to the modules of the FPGA, the address can be extended freely and is adaptive to the FPGAs of various types. The reliability is high and the tape-out risk is low.
Description
Technical field
The invention belongs to the technical field of PLD, relate to a kind of control system, especially one can based on FPGA
Automatically the control system of extended address.
Background technology
PLD FPGA, by software tool, exploitation, emulates and tests, rapidly by design programming to device
In, save substantial amounts of non-repeatability engineering cost and circuit R&D cycle, PLD is based on repeating configuration simultaneously
Memory technology, it is only necessary to re-download programming, can complete the amendment of circuit.It is short that PLD has the construction cycle,
Low cost, risk is little, and integrated level is high, and motility is big, and is easy to the advantages such as electronic system maintenance and upgrading, has therefore suffered from wide
The favor of big end product user, becomes the main flow of IC chip, and is widely used in various field such as communication, control
System, video, information processing, electronics, the Internet, automobile and Aero-Space etc..
PLD FPGA, mainly comprises control system, programmable logic cells CLB, Digital Signal Processing DSP,
Memory element BRAM and some high-speed interfaces, clock module and IP kernel etc., and control system is in PLD
Most important structure, is the interface of software download programming, is to configure the control system of each module in whole FPGA, only controls
The bitstream of system accurate Software Create of energy downloads to configure SRAM, could normally work in FPGA.Want real
Now corresponding bitstream is downloaded to, in the configuration SRAM of correspondence, be necessary for wanting address control system.Because exploitation is not now
FPGA with scale, it is necessary to redesign the address control system of a set of correspondence, for the FPGA of different scales size, no
A set of address control system can be shared, need human cost, and address control newly developed owing to often designing a set of address control system
Certain risk can be there is in system processed.Would not deposit if all sharing a set of control system regardless of the FPGA of different scales size
Risk in flow.
Summary of the invention
The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of can the control of extended address automatically based on FPGA
System processed, its address can be with arbitrary extension, the most convenient FPGA adapting to each scale.
In order to solve above-mentioned technical problem, the invention provides following technical scheme:
The present invention a kind of based on FPGA can the control system of extended address automatically, including an address generating module, multiple addresses
Decoder module and multiple addresses control module, the corresponding address decoder module of every string, the corresponding address of every a line controls mould
Block, address generating module produces an address, and address passes to each address decoder module by the first bus, and address decodes
After module receives address, compare according to the address of self, decode out address and open Word Line, after terminating, return a letter
Number to address control module, address control module judges that current line, either with or without signal occur, and is passed to address by the second bus and produced
Raw module, the appropriate section of address is reset or adds one according to signal by address generating module.
Further, the address that address generating module produces is divided into 3 parts: RowAddress, ColumnAddress, Minor
Address, and the bit wide of address can be increased.
Further, FPGA includes input/output port, memory element, programmable logic cells and Digital Signal Processing, and can
Arbitrarily to increase module, increase line number.
Further, the corresponding address decoder module of each module, the MinorAddress address of each module in FPGA
Different, in the address decoder module that each module is corresponding, the MinorAddress for comparing is in different size.
Further, each address decoder module of every a line, it is used for returning COLUMN_CNT_EN signal.
Further, last address decoder module of the every a line in addition to last column, it is used for returning ROW_CNT_EN
Signal.
Further, last address decoder module of last column, it is used for returning ROW_CNT_EN, ROW_END
Signal.
Further, address control module, be used for judge current line either with or without occur ROW_CNT_EN,
COLUMN_CNT_EN, ADDR_END signal, and pass to address generating module.
Further, address generating module is an enumerator producing address.
Beneficial effects of the present invention: this control system is for the modules assignment configuration data in FPGA, to reach FPGA
Meeting the function that user wants, therefore, this control system configurability is strong, address can spread, be applicable to each scale
FPGA in, reliability is high, and flow risk is little.
Accompanying drawing explanation
Fig. 1 is the module diagram in FPGA of the present invention；
Fig. 2 is that the present invention is a kind of can the address structure figure of the control system of extended address automatically based on FPGA；
Fig. 3 is that the present invention is a kind of can the Organization Chart of the control system of extended address automatically based on FPGA.
Detailed description of the invention
Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the limit to scope
Fixed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to the present invention
Making improvements and modifications, these improve and modification also falls in the range of the claims in the present invention protection.
As it is shown in figure 1, the module in FPGA includes: input/output port IOB, memory element BRAM, FPGA list
Unit CLB, Digital Signal Processing DSP, can arbitrarily increase module according to design requirement, increase line number.
As in figure 2 it is shown, be the address structure of 32, it is segmented into 3 parts: RowAddress: represent which row,
ColumnAddress: represent which module in current line, MinorAddress: represent the specific address in current block,
Need to increase the bit wide of address according to design.
The present invention is a kind of can the description of the control system of extended address automatically based on FPGA:
As it is shown in figure 1, the module in FPGA includes input/output port IOB, memory element BRAM, programmable logic cells
CLB, Digital Signal Processing DSP, the corresponding address decoder module Addr_decoder of each module, due to each mould
The MinorAddress address of block is different, therefore is used for comparing in address decoder module Addr_decoder corresponding to each module
MinorAddress size the most different.
As it is shown on figure 3, every a line (except last column ROW Last) last address decoder module, corresponding
Addr_decoder (5), is used for returning ROW_CNT_EN signal, namely line feed enables signal.
As it is shown on figure 3, last address decoder module of last column ROW Last, corresponding A ddr_decoder (6), use
In returning ROW_CNT_EN, ROW_END signal, namely end of address (EOA) enables signal.
As it is shown on figure 3, corresponding address control module Addr_ctrl (3) of every a line, it is used for judging that current line is either with or without appearance
ROW_CNT_EN, COLUMN_CNT_EN, ADDR_END signal, and pass to address generation by the second bus (2)
Modules A ddr_gen (7).
As it is shown on figure 3, address generating module Addr_gen (7) is to produce an enumerator of address, MinorAddress is always
Cumulative, only receiving COLUMN_CNT_EN signal, MinorAddress can reset, and Column_Address just adds one；
When receiving ROW_CNT_EN signal, MinorAddress can reset, and Column_Address can reset, RowAddress
Add one；When receiving ADDR_EN signal, MinorAddress can reset, and Column_Address can reset, RowAddress
Can reset, address generating module Addr_gen (7) terminates.
The present invention is a kind of can the principle of the control system of extended address automatically based on FPGA:
As it is shown on figure 3, produced an address by address generating module Addr_gen (7), this address includes (as shown in Figure 2)
RowAddress, ColumnAddress, MinorAddress.Address passes to each address by the first bus (1) and decodes
Modules A ddr_decoder (4,5,6).Address decoder module Addr_decoder (4,5,6) can be according to self after receiving address
Address compare, decode out address and open Word Line.
Address decoder module Addr_decoder (4) terminates to return a COLUMN_CNT_EN signal, tells that is produced from address
The address of raw modules A ddr_gen (7) this module is over, and address generating module Addr_gen (7) will be Minor
Address resets, and ColumnAddress adds one.
Address decoder module Addr_decoder (5) is corresponding in (except last column) every last module of a line, in order to return
Returning ROW_CNT_EN end signal, tell that the address of address generating module Addr_gen (7) this line is over, is produced from address
Raw modules A ddr_gen (7) will reset MinorAddress, and ColumnAddress resets, and RowAddress adds one.
Address decoder module Addr_decoder (6) is corresponding last module of last column, in order to return ADD_END knot
Bundle signal, tells that address generating module Addr_gen (7) all addresses have counted and terminates, address generating module Addr_gen (7)
MinorAddress will be reset, ColumnAddress resets, and RowAddress resets.
Module in FPGA can arbitrarily increase module according to design requirement, increases line number, the address that address generating module produces
Its bit wide can be increased according to design needs, therefore, its address can any spread, facilitate flexibly and be applicable to each scale
In FPGA, reliability is high, and flow risk is little；This control system is used for the modules assignment configuration data in FPGA,
Meeting the function that user wants reaching FPGA, therefore, this control system configurability is strong, no matter different scales size
FPGA shares a set of control system, and human cost reduces, and development risk is little.
Claims (9)
1. one kind can the control system of extended address automatically based on FPGA, it is characterised in that: include an address generating module,
Multiple addresses decoder module and multiple addresses control module, the corresponding address decoder module of every string, the corresponding ground of every a line
Location control module, address generating module produces an address, and address passes to each address decoder module by the first bus,
After address decoder module receives address, compare according to the address of self, decode out address and open Word Line, return after terminating
Return a signal to address control module, address control module judge current line either with or without signal occurs, and by second bus biography
To address generating module, the appropriate section of address is reset or adds one according to signal by address generating module.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: describedly
The address that location generation module produces is divided into 3 parts: Row Address, Column Address, Minor Address, and can increase
Add the bit wide of address.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: described
FPGA includes input/output port, memory element, programmable logic cells and Digital Signal Processing, and can arbitrarily increase module,
Increase line number.
The most according to claim 3 can the control system of extended address automatically based on FPGA, it is characterised in that: described
The corresponding address decoder module of each module in FPGA, the Minor Address address of each module is different, Mei Gemo
In the address decoder module that block is corresponding, the Minor Address for comparing is in different size.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: described often
Each address decoder module of a line, is used for returning COLUMN_CNT_EN signal.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: described remove
Last address decoder module of the every a line outside last column, is used for returning ROW_CNT_EN signal.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: described
Last address decoder module of rear a line, is used for returning ROW_CNT_EN, ROW_END signal.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: describedly
Location control module, is used for judging that current line is either with or without ROW_CNT_EN, COLUMN_CNT_EN, ADDR_END occur
Signal, and pass to address generating module.
The most according to claim 1 can the control system of extended address automatically based on FPGA, it is characterised in that: describedly
Location generation module is an enumerator producing address.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755436A (en) * | 2020-07-01 | 2020-10-09 | 无锡中微亿芯有限公司 | Multi-die FPGA with real-time monitoring and configuration information correcting functions |
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| EP1202165A2 (en) * | 2000-10-30 | 2002-05-02 | Hewlett-Packard Company (a Delaware corporation) | Generation of cryptographically strong random numbers using MISR registers |
| CN102789190A (en) * | 2011-05-20 | 2012-11-21 | 中国科学院微电子研究所 | Column address distributor circuit suitable for different types of FPGA (field programmable gate array) circuit programming |
| WO2013002574A2 (en) * | 2011-06-28 | 2013-01-03 | 에스케이플래닛 주식회사 | System, server apparatus, terminal apparatus, and recording medium for generating a user affinity-based address book, and method for generating a user affinity-based address book |
| CN104598405A (en) * | 2015-02-03 | 2015-05-06 | 杭州士兰控股有限公司 | Expansion chip and expandable chip system and control method |
| CN104881373A (en) * | 2014-12-05 | 2015-09-02 | 中国航空工业集团公司第六三一研究所 | Method for expanding access spaces of memories |
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2016
- 2016-03-14 CN CN201610143865.2A patent/CN105843986B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1202165A2 (en) * | 2000-10-30 | 2002-05-02 | Hewlett-Packard Company (a Delaware corporation) | Generation of cryptographically strong random numbers using MISR registers |
| CN102789190A (en) * | 2011-05-20 | 2012-11-21 | 中国科学院微电子研究所 | Column address distributor circuit suitable for different types of FPGA (field programmable gate array) circuit programming |
| WO2013002574A2 (en) * | 2011-06-28 | 2013-01-03 | 에스케이플래닛 주식회사 | System, server apparatus, terminal apparatus, and recording medium for generating a user affinity-based address book, and method for generating a user affinity-based address book |
| CN104881373A (en) * | 2014-12-05 | 2015-09-02 | 中国航空工业集团公司第六三一研究所 | Method for expanding access spaces of memories |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111755436A (en) * | 2020-07-01 | 2020-10-09 | 无锡中微亿芯有限公司 | Multi-die FPGA with real-time monitoring and configuration information correcting functions |
| CN111755436B (en) * | 2020-07-01 | 2021-12-07 | 无锡中微亿芯有限公司 | Multi-die FPGA with real-time monitoring and configuration information correcting functions |
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| CN105843986B (en) | 2019-03-19 |
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Effective date of registration: 20201217 Address after: 2 / F, building B1, No. 777, Jianzhu West Road, Binhu District, Wuxi City, Jiangsu Province, 214000 Patentee after: WUXI ZHONGWEI YIXIN Co.,Ltd. Address before: Hui Road Binhu District 214035 Jiangsu city of Wuxi province No. 5 Patentee before: The 58th Research Institute of China Electronics Technology Group Corp. |
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