CN105843588A - MIC based random number generator segmented parallelizing method - Google Patents

Abstract

The present invention discloses an MIC based random number generator segmented parallelizing method, so as to perform parallelizing by a method of segmenting a periodic sequence and splice random numbers generated by threads to form a final sequence. Compared with a CPU single thread, a speedup ratio under an MIC platform has a significant advantage.

Description

A kind of randomizer stagewise parallel method based on MIC

Technical field

The present invention relates to a kind of stagewise parallel method of general type randomizer, espespecially for Intel The hardware of MIC framework carries out the method for random number sequence output.

Background technology

Randomizer is used to produce the device of random number, is generally divided into real random number generator and pseudo random number is sent out Raw device.Scientific research at present and engineering simulation are growing, by parallel computation to performance and the rate requirement of randomizer Technology is applied to randomizer can quickly improve generation efficiency.Additionally the parallelization resarch work of randomizer is main Concentrate on multi-core central processing unit (Central Processing Unit, CPU) platform, lack based on Intel last word The correlation theory foundation of MIC (Many Integrated Core) platform parallelization and performance evaluation.

Intel MIC (Many Integrated Core) framework has less kernel and more hardware thread, with And broader vector units, it is to improve overall performance, meet the choosing of the ideal of highly-parallel application demand, it is based on x86 frame Structure, supports the parallel programming models such as OpenMP, pThread.Xeon Phi based on MIC framework calculates accelerator card by 57～61 Physical treatment core is constituted, and each physical core comprises 4 hardware threads, and accelerator card memory on board size is 6GB～8GB, double Accuracy computation peak computational ability reaches 1TFlops.It compares CPU advantageously in terms of parallel computation, solves the most also Row computational problem.

Summary of the invention

The problem that invention is to be solved

It is an object of the present invention to overcome deficiency of the prior art, it is provided that a kind of random number based on MIC occurs Device stagewise parallel method.

For solving the scheme of problem

A kind of randomizer stagewise parallel method based on MIC, comprises the following steps:

Step A, acquisition partiting step, including

Step A1, the cycle ρ of acquisition original random number sequence；

Step A2, obtain supported maximum thread N, every thread producible random number number

Step B, main thread read parameter, calculate each thread original state seed [id], including

Random number quantity random_num required for the reading of step B1, main thread, the Thread Count threads_num of distribution And seed seed, wherein 0 ＜ random_num ＜ ρ, 0 ＜ threads_num ＜ N；

Step B2, set up internal memory interval result；

Step B3, calculate each thread need produce random number num=random_num/threads_num；

Step B4, the value arranging id are 1；

Step B5, calculating seed [id]；

If step B6 id ＞ threads_num, then forward step C to；

Step B7, id value, from increasing 1, are then back to step B5；

Step C, MIC thread calculate, including

Step C1, the initial value arranging i are 0, and the initial value of U is 0；

Step C2, by random number serial algorithm calculate U；

Step C3, result [id*num+i]=U；

If step C4 i ＞ num, then terminate this thread；

Step C5, i value, from increasing 1, are then back to step C3.

The effect of invention

The present invention utilizes the method to periodic sequence segmentation to carry out parallelization, and the random number finally generated by each thread is spelled Pick up and form final sequence.Single-threaded relative to CPU, the speed-up ratio under MIC platform has clear superiority.

Accompanying drawing explanation

Fig. 1 is randomizer stagewise parallelization schematic diagram；

Fig. 2 is the calculation flow chart realizing randomizer parallelization based on MIC；

Fig. 3 a and Fig. 3 b is that MRG32k3a is based on the speed-up ratio trendgram after CPU and MIC parallelization.

Detailed description of the invention

Various exemplary embodiments, feature and the aspect of the present invention is described in detail below with reference to embodiment.In order to more preferably The explanation present invention, detailed description of the invention below gives numerous details.Those skilled in the art should manage Solving, do not have these details, the present invention equally implements.In other example, for known method, hands Section, material are not described in detail, in order to highlight the purport of the present invention.

As it is shown in figure 1, the present invention utilizes the method to periodic sequence segmentation to carry out parallelization.First it is the former of ρ by the cycle Beginning random number sequence is divided equally into N section (N is maximum supported Thread Count), and every section comprisesNumber, the most each line Journey starts recursion generation random number from the starting point of each section.Assume the total amount that random_num is the random number needing generation, Threads_num is the Thread Count of distribution, and the most each thread produces random_num/threads_num random number.Finally will The random number that each thread generates is stitched together and forms final sequence.

Comprise the following steps:

Step A, acquisition partiting step, including

Step A1, the cycle ρ of acquisition original random number sequence；

Step A2, obtain supported maximum thread N, every thread producible random number number

Step B, main thread read parameter, calculate each thread original state seed [id], including

Random number quantity random_num required for the reading of step B1, main thread, the Thread Count threads_num of distribution And seed seed, wherein 0 ＜ random_num ＜ ρ, 0 ＜ threads_num ＜ N；

Step B2, set up internal memory interval result；

Step B3, calculate each thread need produce random number num=random_num/threads_num；

Step B4, the value arranging id are 1；

Step B5, calculating seed [id]；

If step B6 id ＞ threads_num, then forward step C to；

Step B7, id value, from increasing 1, are then back to step B5；

Step C, MIC thread calculate, including

Step C1, the initial value arranging i are 0, and the initial value of U is 0；

Step C2, by random number serial algorithm calculate U；

Step C3, result [id*num+i]=U；

If step C4 i ＞ num, then terminate this thread；

Step C5, i value, from increasing 1, are then back to step C3.

In a kind of possible embodiment, the present invention comprises the following steps:

1. preparation

A) research randomizer serial algorithm, and obtain its cycle ρ；

B) cycle division rule is determined: supported Thread Count N, every thread producible random number number

2. main thread: read relevant parameter, calculate each thread original state seed [id]

A) random number quantity random_num, the Thread Count threads_num of distribution and the seed required for reading Seed, wherein 0 ＜ random_num ＜ ρ, 0 ＜ threads_num ＜ N；

B) internal memory interval result is set up；

C) the random number num=random_num/threads_num that each thread needs to produce is calculated；

D) id=1；

E) seed [id] is calculated；

If f) id ＞ threads_num, then turn 3；

G) id++, turns e).

3.MIC thread: control MIC equipment by modes such as native, offload, each thread synchronization works, and carries out following Identical calculations, as in figure 2 it is shown,

A) i=0, U=0；

B) U is calculated by random number serial algorithm；

C) result [id*num+i]=U；

If d) i ＞ num, then terminate；

E) i++, turns c).

In a kind of possible embodiment, the step of the present invention is

Control MIC equipment by native mode, use C++ to realize randomizer MRG32k3a stagewise parallelization As a example by, MRG32k3a recurrence formula is:

$\left\{\begin{array}{c}{x}_{1,n}=(a_{1,2}{x}_{1,n-2}+a_{1,3}{x}_{1,n-3})\mathrm{mod}{m}_1\\ x_{2,n}=(a_{2,1}{x}_{2,n-1}+a_{2,3}{x}_{2,n-3})\mathrm{mod}{m}_2\end{array}\right.$

Wherein n >=3,

a_1,2=1403580 a_1,3=-810728

a_2,1=527612 a_2,3=-1370589

m₁=2³²-209 m₂=2³²-22853

Produce [0,1) between uniform random number U_n。

z_n=(x_{1, n}+x_{2, n})mod m₁

$U_n=\left\{\begin{array}{cc}{z}_n/m_1& z_n>0\\ (m_1-1)/m_1& z_n=0\end{array}\right.$

Its cycle ρ=2¹⁹², set and at most run N=2⁶⁴Individual thread, each thread at most produces L=2¹²⁷Individual random number.

MRG32k3a recurrence formula is converted into vector form:

X_{I, n+1}=A_iX_{I, n}mod m_i, i=1,2

$A_1=\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ a_{1,3}& a_{1,2}& 0\end{array}\right],A_2=\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ a_{2,3}& 0& a_{2,1}\end{array}\right]$

Before each thread generates random number, need first to calculate the initial value of each thread, if the initial value of No. 0 thread is s₀, then the initial value of Line 1 journey is s₁, its computational methods are as follows:

According to formula (xyz) mod p=(((xy) mod p) z) mod p

It is easy to get:

s₁=(A^LS₀) mod m=(((A^L)mod m)·s₀)mod m

Wherein, A^LMod m can be calculated by algorithm of dividing and ruling, and recurrence formula is:

A^LMod m=((A^L/2mod m)·(A^L/2mod m))mod m

Each thread original state s can be calculated by that analogy_id, wherein 0≤id ＜ threads_num.

In sum, MRG32k3a stagewise Parallel Algorithm is as follows:

Algorithm MRG32k3a stagewise Parallel Algorithm

Input: seed seed [6], Thread Count threads_num,

Task amount random_num

Output: random_hum random number U

Begin

(1) main thread

(2) MIC equipment, native pattern

Based on above-described embodiment, test data: respectively MRG32k3a is produced under 1,2,4,8 and 16 threads of CPU platform Raw 1,000,000,10,000,000,100,000,000,1,000,000,000 and 10,000,000,000 random number, and Produce 1,000,000 under MIC platform 1,2,4,8,16,32,56,112,168 and 224 thread thread respectively, 10,000,000, 100,000,000, the time of 1,000,000,000 and 10,000,000,000 randoms number tests.Relative to CPU single line Journey, the optimum speed-up ratio under MIC platform is 17.73.

Test result is as shown in Figure 3 a and Figure 3 b shows.

Wherein hardware environment is as follows:

The present invention utilizes the method to periodic sequence segmentation to carry out parallelization, is spliced by the random number that each thread generates Form final sequence.Single-threaded relative to CPU, the speed-up ratio under MIC platform has clear superiority.

Although illustrating the present invention with reference to embodiment of above, it will be appreciated, however, that the invention is not restricted to institute Disclosed embodiment.The scope of the appended claims should explain in broadest scope, with contain all modification, Equivalent structure and function.

Claims (1)

1. a randomizer stagewise parallel method based on MIC, it is characterised in that comprise the following steps:

Step A, acquisition partiting step, including

Step A1, the cycle ρ of acquisition original random number sequence；

Step A2, obtain supported maximum thread N, every thread producible random number number

Step B, main thread read parameter, calculate each thread original state 8eed [id], including

Step B1, main thread read required for random number quantity random_num, the Thread Count threads_num of distribution and Seed seed, wherein 0 ＜ random_num ＜ ρ, 0 ＜ threads_num ＜ N；

Step B2, set up internal memory interval result；

Step B3, calculate each thread need produce random number num=random_num/threads_num；

Step B4, the value arranging id are 1；

Step B5, calculating seed [id]；

If step B6 id ＞ threads_num, then forward step C to；

Step B7, id value, from increasing 1, are then back to step B5；

Step C, MIC thread calculate, including

Step C1, the initial value arranging i are 0, and the initial value of U is 0；

Step C2, by random number serial algorithm calculate U；

Step C3, result [id*num+i]=U；

If step C4 i ＞ num, then terminate this thread；

Step C5, i value, from increasing 1, are then back to step C3.