CN105828084A - HEVC inter-frame encoding processing method and device - Google Patents
HEVC inter-frame encoding processing method and device Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
- H04N19/147—Data rate or code amount at the encoder output according to rate distortion criteria
Abstract
The present invention provides a HEVC inter-frame encoding processing method. The HEVC inter-frame encoding processing method is configured to speed up the decision speed of a skipping mode and improve the HEVC encoding efficiency. In the feasible embodiments of the invention, the method comprises: obtaining the predicted value and the original value of a current prediction unit (PU); calculating the error sum of squares of the predicted value and the original value of the PU; and comparing the error sum of squares and a threshold, and determining whether the prediction mode of the PU is the skipping mode or not according to the comparison result. The embodiment of the invention further provides a corresponding device.
Description
Technical field
The present invention relates to technical field of video coding, be specifically related to a kind of HEVC interframe encode treating method and apparatus.
Background technology
Efficient video coding (HighEfficiencyVideoCoding, HEVC) it is new video compression standard of future generation, its target is that video compression efficiency is than existing H.264/AVC (AdvancedVideoCoding, advanced video coding) HighProfile (high-end specification) improves more than 30%, for substituting H.264/AVC coding standard.
CU (CodingUnit, coding unit) is the most basic unit of HEVC interframe and intraframe coding, and size can be 64 × 64,32 × 32,16 × 16 and 8 × 8, and unit is pixel.Each CU can be divided into multiple PU (PredictionUnit, it was predicted that unit).PU is by the elementary cell of infra-frame prediction and inter prediction, and size can be from 4 × 4 to 64 × 64, and the shape of PU can be square such as 4 × 4, or rectangular block such as 4 × 8, etc..
In HEVC encoder, the judgement of P frame (Predictionframe, interframe encode) the inside skip mode is the biggest to the performance impact of encoder.Once the predictive mode of current PU is selected as skip mode, then the process such as Further Division and motion search can be avoided.Judge whether PU is respectively necessary for calculating the rate distortion costs under skip mode and general mode as skip mode.The rate distortion costs of general mode needs just can be calculated through complete cataloged procedure, and complete cataloged procedure is very time-consuming, and the judgement speed resulting in skipped pattern reduces, and has a strong impact on HEVC code efficiency.
Summary of the invention
The embodiment of the present invention provides a kind of HEVC interframe encode treating method and apparatus, for accelerating the judgement speed of skip mode, improves HEVC code efficiency.
First aspect present invention provides a kind of HEVC interframe encode processing method, including: obtain predictive value and the original value of current predicting unit PU；Calculate the predictive value of described PU and the error sum of squares of original value；Described error sum of squares is compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
Second aspect present invention provides a kind of HEVC interframe encode processing means, including: the first computing module, for obtaining predictive value and the original value of current predicting unit PU；Calculate the predictive value of described PU and the error sum of squares of original value；First processing module, for described error sum of squares being compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
Third aspect present invention provides a kind of computer equipment, including processor, memorizer, bus and communication interface；Described memorizer is used for storing program, described processor is connected by described bus with described memorizer, when described computer equipment runs, described processor performs the described program of described memorizer storage, so that described computer equipment performs HEVC interframe encode processing method as described in relation to the first aspect.
Fourth aspect present invention provides a kind of computer-readable recording medium storing one or more program, the one or more program includes instruction, described instruction, when the computer equipment being included one or more processor performs, makes computer equipment perform HEVC interframe encode processing method as described in relation to the first aspect.
Therefore, in some feasible embodiments of the present invention, the error sum of squares of predictive value with original value by calculating current PU；Described error sum of squares can be compared with threshold value, whether the predictive mode judging described PU according to comparative result is skip mode, thus, complete cataloged procedure can be skipped for part PU, such that it is able to reduce the judgement speed improving skip mode, it is favorably improved HEVC code efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly that embodiment of the present invention technical scheme, the accompanying drawing used required in embodiment and description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the judgement schematic flow sheet of the predictive mode of conventional PU；
Fig. 2 is the schematic flow sheet of the HEVC interframe encode processing method that one embodiment of the invention provides；
Fig. 3 is the schematic flow sheet of the HEVC interframe encode processing method that another embodiment of the present invention provides；
Fig. 4 is the structural representation of the HEVC interframe encode processing means that one embodiment of the invention provides；
Fig. 5 is the structural representation of the computer equipment that one embodiment of the invention provides.
Detailed description of the invention
In order to make those skilled in the art be more fully understood that the present invention program, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the embodiment of a present invention part rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, all should belong to the scope of protection of the invention.
Term " first " in description and claims of this specification and above-mentioned accompanying drawing, " second ", " the 3rd " etc. are for distinguishing different objects rather than for describing particular order.Additionally, term " includes " and " having " and their any deformation, it is intended that cover non-exclusive comprising.Such as contain series of steps or the process of unit, method, system, product or equipment are not limited to step or the unit listed, but the most also include step or the unit do not listed, or the most also include other step intrinsic for these processes, method, product or equipment or unit.
Technical solution of the present invention is applied to technical field of video coding.The index weighing video encoding standard performance is mainly encoder bit rate and coding distortion.Wherein, encoder bit rate refers to the residual error that encoding block obtains, then the coding information finally obtained through conversion, quantization through predictive coding.Image fault refers to the difference of the image of reconstructed block and original block.Less number of coded bits is conducive to storage or network transmission, but reconstructing video coding distortion is bigger；Otherwise, number of coded bits will be increased.The two index is that mutually restriction is with conflicting.
In Video coding, In-commission Rate aberration optimizing (Rate-DistortionOptimization, RDO) technology realizes the compromise between code check and distortion.RDO is a kind of video coding technique, under the least encoder bit rate, reduces image fault degree so that code efficiency reaches the highest.The purpose of RDO is: under certain bit rate, and the distortion how making reconstruction image is minimum；Or under conditions of allowing certain distortion, carry out coded image with minimum bit number.
Video compression standard HEVC of future generation contains the encryption algorithm of numerous high complexity, and code efficiency is restricted, thus improving HEVC video coding efficiency is the most real demand.In HEVC coding techniques, each two field picture of video is divided into CTU (Codingtreeunit, code tree unit), CTU is that HEVC encodes elementary cell, macro zone block (Macroblock) in being similar to H.264/AVC, the size of CTU can be from 16x16 to 64x64, and unit is pixel.Each CTU can be a CU, it is also possible to be further divided into multiple CU.CU is the most basic unit of HEVC interframe and intraframe coding, and size can be 64 × 64,32 × 32,16 × 16 and 8 × 8, and unit is pixel.
Each CU can be divided into again multiple PU.PU is by the elementary cell of infra-frame prediction and inter prediction, and size can be from 4 × 4 to 64 × 64, and the shape of PU can be square such as 4 × 4 or 8 × 4 etc., it is also possible to be rectangular block such as 4 × 8 or 8 × 16 etc..
In HEVC interframe encode, in other words in P frame coding, PU can use skip mode, merging patterns and other patterns to encode.Merging patterns and other patterns are referred to as general mode by the present invention.Skip mode is only to send to skip mark and reference key, and does not send the pattern of predictive mode, partition size, prediction direction, motion vector difference and residual information.The model selection of HEVC encoder can select according to rate distortion costs (Rate-DistortionCost, RDCost), and rate distortion costs can be calculated by RDO.
As it is shown in figure 1, be the judgement flow process of the predictive mode of PU.Determining whether to be that a PU selects skip mode, concrete judgement flow process may include that
First, calculate the predictive value of current PU, this PU is encoded according to skip mode, calculate rate distortion costs RDCostC0 of skip mode；
Then, carry out complete cataloged procedure according to general mode, calculate rate distortion costs RDCostC1 of general mode；
If cost RDCostC0 of skip mode is less than cost RDCostC1 of general mode, then judges that the predictive mode of current PU is skip mode, be otherwise general mode.
Therefore, rate distortion costs RDCostC1 of general mode needs just can be calculated through complete cataloged procedure, and complete cataloged procedure is very time-consuming, and the judgement speed resulting in skipped pattern reduces, and has a strong impact on HEVC code efficiency.
To this end, the embodiment of the present invention provides a kind of HEVC interframe encode treating method and apparatus, for accelerating the judgement speed of skip mode, improve HEVC code efficiency.
Below by specific embodiment, it is described in detail respectively.
Refer to Fig. 2, the embodiment of the present invention provides a kind of HEVC interframe encode processing method.
Embodiment of the present invention method is applied in HEVC interframe encode, in the judging process of PU pattern.
HEVC Video coding can use inter prediction, i.e. in video flowing, each frame is not required to each frame is a secondary complete image, because picture exists temporal dependency before and after each, picture below can be by plus a motion vector on the basis of picture above, it was predicted that out.In typical IPB frame coding structure, only I frame is only complete picture, P frame on the basis of I frame reference prediction out, and B frame is bi-directional predicted, it is also desirable to reference to I frame or P frame, construct, by calculating control information, the picture that a width is complete.As can be seen here, video is not that playing continuously of simple figure is formed.Owing to there is temporal dependency in video, it is possible to use temporal correlation, eliminates time redundancy information, completes interframe encode.
PU is by the elementary cell of infra-frame prediction and inter prediction, size can be from 4 × 4 to 64 × 64, in H.265, in addition to the similar dividing method H.264 of 2N × 2N, N × N, 2N × N and the N × 2N of symmetric pattern (symmetricmotionpartition), H.265 asymmetrical pattern (asymmetricmotionpartition is additionally provided, AMP), contain 2N × nU, 2N × nD, nL × 2N and nR × 2N, the English alphabet of capitalization represents the position of the length of side shorter segmentation block, wherein, N is the power exponent of 2.Therefore, the shape of PU can be square block such as 4 × 4, or rectangular block such as 4 × 8, etc..
In HEVC encoder, inside P frame, the judgement of skip mode is the biggest to the performance impact of encoder.Once the predictive mode of current PU is selected as skip mode, then the process such as Further Division and motion search can be avoided.
Refer to Fig. 2, the HEVC interframe encode processing method that the embodiment of the present invention provides, for the judgement of PU pattern, the method comprises the steps that
201, predictive value and the original value of current predicting unit PU are obtained；
PU in P frame out, for given current PU, can obtain its original value and predictive value by reference prediction on the basis of I frame.Wherein, original value is the content that current PU is to be encoded, refers to input picture value on current PU position；After predictive value refers to given motion vector, by interpolation calculation value out inside reference frame；Reference frame is the reconstructed value of the most encoded frame.
It should be noted that in some embodiments of the invention, YUV colour coding method can be used to represent each two field picture value, YUV signal includes luminance signal Y and two colour difference signal B-Y (i.e. U), R-Y (i.e. V).Above-mentioned original value and predictive value can refer to the YUV value of image.Certainly, other embodiments can also use other colour coding method, not limit herein.
202, the predictive value of described PU and the error sum of squares of original value are calculated；
In this step, calculate the predictive value of described PU and the error sum of squares (sumofthesquarederrors, SSE) of original value.Error sum of squares is at identical conditions, and each time measured value is sued for peace to after the deviation square of actual value again.SSE can be used to the inclined extent representing predictive value with actual value, and SSE is the least, represents that predictive value is closer to original value.
Assuming that a PU includes m*n pixel, m and n is positive integer, wherein the predictive value a of the i-th j pixel of *ijRepresent, original value bijRepresenting, i is the positive integer of no more than m, and j is the positive integer of no more than n, then the predictive value of this PU can represent by below equation with the error sum of squares of original value:
203, described error sum of squares is compared with threshold value, judge according to comparative result whether the predictive mode of described PU is skip mode.
This step, first by error sum of squares as the decision rule of PU pattern, by relative error quadratic sum and threshold value, judges whether to select skip mode according to comparative result.If the comparison show that, it was predicted that it is worth less with the deviation of actual value, then can select skip mode.
Concrete, it can be determined that whether error sum of squares is less than threshold value Threshold set in advance, if less than threshold value Threshold, then think that SSE is sufficiently small, the sufficiently close together original value of predictive value, then can select skip mode, and the mode adjudging terminating this PU selects flow process.
In some embodiments, threshold value Threshold corresponding to described PU can be calculated previously according to the size of described PU with quantization parameter (Quantizationparameter, QP).QP is the quantization parameter in HEVC, and legal range is 0-51, and the biggest compression ratio of numerical value is the highest, and distortion is the most serious.Threshold value Threshold is the function of PU and QP, can be expressed as Threshold=f (QP, PU).
During one implements, can use below equation calculate Threshold:
Wherein N is the width of PU.
In the embodiment of the present invention, if described error sum of squares SSE not less than described threshold value Threshold, then can continue executing with following judgement flow process:
S1, calculate the first rate distortion costs of the skip mode of described PU, and, described CU is encoded according to general mode, calculates the second rate distortion costs of described general mode；
Described first rate distortion costs can be represented with RDCostC0, represent described second rate distortion costs with RDCostC1.Wherein it is possible to described PU is used skip mode coding, to be calculated RDCostC0；And, to described PU according to encoded normal mode, it is calculated RDCostC1.It may be noted that general mode is the abbreviation of common inter-frame mode.
S2, described first rate distortion costs is compared with described second rate distortion costs, judge according to comparative result whether the predictive mode of described PU is skip mode.
Concrete, step S2 may include that and judges that whether described first rate distortion costs is less than described second rate distortion costs；The predictive mode the most then judging described PU is skip mode, otherwise, it is judged that the predictive mode of described PU is general mode.
In this step, if cost RDCostC0 of skip mode is less than cost RDCostC1 of general mode, then judges that the predictive mode of current PU is skip mode, be otherwise general mode.
Therefore, including two stages before and after embodiment of the present invention method, the first stage uses error sum of squares SSE as decision rule, it may be judged whether use skip mode, if selecting skip mode, then terminates whole judgement flow process, otherwise, enters second stage；Second stage uses rate distortion costs RDCost as decision rule, it may be judged whether using skip mode, the rate distortion costs under any predictive mode is little, then use any predictive mode.
Being appreciated that embodiment of the present invention such scheme such as can be at personal computer, panel computer, mobile phone, server, television set, the various equipment such as game machine are embodied as.
For ease of being better understood from the technical scheme that the embodiment of the present invention provides, it is introduced below by as a example by the embodiment under a concrete scene.
Refer to Fig. 3, the another kind of HEVC interframe encode processing method of the embodiment of the present invention, it may include:
301, the predictive value of current PU is calculated；
302, the predictive value of described PU and error sum of squares SSE of original value are calculated；
303, whether error in judgement quadratic sum SSE is less than threshold value Threshold, if so, enters step 308, otherwise, enters step 304；
304, the first rate distortion costs RDCostC0 of skip mode is calculated；
305, encode according to general mode；
306, the second rate distortion costs RDCostC1 of general mode is calculated；
307, judge whether RDCostC0 < RDCostC1 sets up, if so, enter step 308, otherwise, enter step 309；
308, judge that current PU is skip mode；
309, judge that current PU is general mode.
Therefore, if error sum of squares SSE is less than threshold value Threshold, then it is assumed that SSE is sufficiently small, it was predicted that is worth sufficiently close together original value, then can select skip mode, the mode adjudging terminating this PU selects flow process.Same, if RDCostC0 is less than RDCostC1, then it is assumed that the sufficiently close together original value of predictive value, it can be determined that the predictive mode of current PU is skip mode.
Above, in HEVC interframe encode handling process, the logic flow of PU mode adjudging is described.Relative to prior art, the method is before calculating the rate distortion costs of skip mode and general mode, first calculate the predictive value of PU and the error sum of squares of original value, when error sum of squares is less than threshold value, directly judge that the predictive mode of PU, as skip mode, and no longer calculates the rate distortion costs of skip mode and general mode, owing to having skipped the calculating of rate distortion costs, and then also PU need not be encoded, the processing speed of interframe encode can be greatly improved.
Herein, successively employing error sum of squares and rate distortion costs RDCost are as judgement standard, but it should be recognized that rate distortion costs can also replace with the criterion that other are similar.
Therefore, in some feasible embodiments of the present invention, by calculating the predictive value of current PU；And, calculate the predictive value of described PU and the error sum of squares of original value；Described error sum of squares can be compared with threshold value, whether the predictive mode judging described PU according to comparative result is skip mode, thus, complete cataloged procedure can be skipped for part PU, such that it is able to reduce the judgement speed improving skip mode, it is favorably improved HEVC code efficiency.
In order to preferably implement the such scheme of the embodiment of the present invention, it is also provided below for coordinating the relevant apparatus implementing such scheme.
Refer to Fig. 4, the embodiment of the present invention provides HEVC interframe encode processing means 400.
Embodiment of the present invention method is applied to HEVC encoder.
Inter prediction can be used when HEVC encoder carries out Video coding, i.e. in video flowing, each frame is not required to each frame is a secondary complete image, because before and after each there is temporal dependency in picture, picture below can be by plus a motion vector on the basis of picture above, it was predicted that out.In typical IPB frame coding structure, only I frame is only complete picture, P frame on the basis of I frame reference prediction out, and B frame is bi-directional predicted, it is also desirable to reference to I frame or P frame, construct, by calculating control information, the picture that a width is complete.As can be seen here, video is not that playing continuously of simple figure is formed.Owing to there is temporal dependency in video, it is possible to use temporal correlation, eliminates time redundancy information, completes interframe encode.
PU is by the elementary cell of infra-frame prediction and inter prediction, size can be from 4 × 4 to 64 × 64, in H.265, in addition to the similar dividing method H.264 of 2N × 2N, N × N, 2N × N and the N × 2N of symmetric pattern (symmetricmotionpartition), H.265 asymmetrical pattern (asymmetricmotionpartition is additionally provided, AMP), contain 2N × nU, 2N × nD, nL × 2N and nR × 2N, the English alphabet of capitalization represents the position of the length of side shorter segmentation block, wherein, N is the power exponent of 2.Therefore, the shape of PU can be square block such as 4 × 4, or rectangular block such as 4 × 8.
In HEVC encoder, inside P frame, the judgement of skip mode is the biggest to the performance impact of encoder.Once the predictive mode of current PU is selected as skip mode, then the process such as Further Division and motion search can be avoided.
As shown in Figure 4, the HEVC interframe encode processing means 400 of the embodiment of the present invention comprises the steps that
First computing module 401, for calculating the predictive value of current predicting unit PU；Calculate the predictive value of described PU and the error sum of squares of original value；
First processing module 402, for described error sum of squares being compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
In some embodiments of the invention, described first processing module 402, specifically for judging that described error sum of squares whether less than described threshold value, the most then judges that the predictive mode of described PU is skip mode.
In some embodiments of the invention, device 400 also includes:
Second computing module 403, if judging that described error sum of squares, not less than described threshold value, calculates the first rate distortion costs of the skip mode of described PU for described first processing module, and, described CU is encoded according to general mode, calculates the second rate distortion costs of described general mode；
Second processing module 404, is additionally operable to compare described first rate distortion costs with described second rate distortion costs, judges according to comparative result whether the predictive mode of described PU is skip mode.
In some embodiments of the invention, described second processing module 404, specifically for judging that whether described first rate distortion costs is less than described second rate distortion costs；The predictive mode the most then judging described PU is skip mode, otherwise, it is judged that the predictive mode of described PU is general mode.
In some embodiments of the invention, device 400 also includes:
3rd computing module 405, calculates the threshold value corresponding to described PU for the size according to described PU with quantization parameter QP.
The equipment such as the HEVC interframe encode processing means of the embodiment of the present invention can be such as server, personal computer, panel computer, mobile phone, television set, game machine.
Being appreciated that the function of each functional module of the HEVC interframe encode processing means of the embodiment of the present invention can implement according to the method in said method embodiment, it implements process and can refer to the associated description in said method embodiment, and here is omitted.
Therefore, in some feasible embodiments of the present invention, by calculating the predictive value of current PU；And, calculate the predictive value of described PU and the error sum of squares of original value；Described error sum of squares can be compared with threshold value, whether the predictive mode judging described PU according to comparative result is skip mode, thus, complete cataloged procedure can be skipped for part PU, such that it is able to reduce the judgement speed improving skip mode, it is favorably improved HEVC code efficiency.
Refer to Fig. 5, the embodiment of the present invention also provides for a kind of computer equipment 500, it may include:
Processor 501, memorizer 502, bus 503 and communication interface 504；Described memorizer 502 is used for the program that stores 505, described processor 501 is connected by described bus 503 with described memorizer 502, when described computer equipment 500 runs, described processor 501 performs the described program 505 of described memorizer 502 storage, so that described computer equipment 500 performs the HEVC interframe encode processing method as described in embodiment of the method above.
This computer equipment 500 can be micro-process computer.Such as: the one in the equipment such as this computer equipment 500 can be general purpose computer, server, personal computer, mobile phone terminal, panel computer, television set, game machine.
Described bus 503 can be industry standard architecture (IndustryStandardArchitecture, referred to as ISA) bus or external equipment interconnection (PeripheralComponent, referred to as PCI) bus or extended industry-standard architecture (ExtendedIndustryStandardArchitecture, referred to as EISA) bus etc..Described bus can be divided into one or more in address bus, data/address bus, control bus.For ease of representing, figure only represents with a thick line, it is not intended that an only bus or a type of bus.
Described memorizer 502 is used for storing program code, and this program code includes computer-managed instruction.Described memorizer 502 can comprise high-speed RAM (RamdomAccessMemory) memorizer.Alternatively, described memorizer 502 can also also include nonvolatile memory (non-volatilememory).The most described memorizer 502 can include disk memory.
Described processor 501 can be a central processing unit (CentralProcessingUnit, referred to as CPU), or described processor 501 can be specific integrated circuit (ApplicationSpecificIntegratedCircuit, referred to as ASIC), or described processor 501 can be arranged to implement one or more integrated circuits of the embodiment of the present invention.
Described processor 501, is used for performing following steps: obtain predictive value and the original value of current predicting unit PU；Calculate the predictive value of described PU and the error sum of squares of original value；Described error sum of squares is compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
Optionally, described processor 501 performs described described error sum of squares to be compared with threshold value, judge that whether the predictive mode of described PU is that skip mode may include that and judges that whether described error sum of squares is less than described threshold value according to comparative result, the predictive mode the most then judging described PU is skip mode.
Optionally, described processor 501 performs described to judge that described error sum of squares is whether less than after described threshold value, can also carry out following steps: if described error sum of squares is not less than described threshold value, calculate the first rate distortion costs of the skip mode of described PU, and, described CU is encoded according to general mode, calculates the second rate distortion costs of described general mode；Described first rate distortion costs is compared with described second rate distortion costs, judges according to comparative result whether the predictive mode of described PU is skip mode.
Optionally, described processor 501 performs described described first rate distortion costs to be compared with described second rate distortion costs, judges that whether the predictive mode of described PU is that skip mode may include that and judges that whether described first rate distortion costs is less than described second rate distortion costs according to comparative result；The predictive mode the most then judging described PU is skip mode, otherwise, it is judged that the predictive mode of described PU is general mode.
Optionally, described processor 501 is additionally operable to perform following steps: before described error sum of squares and threshold value being compared, and calculates the threshold value corresponding to described PU according to the size of described PU with quantization parameter QP.
Being appreciated that the function of the computer equipment 500 of the embodiment of the present invention can implement according to the method in said method embodiment, it implements process and can refer to the associated description in said method embodiment, and here is omitted.
Therefore, in some feasible embodiments of the present invention, by calculating the predictive value of current PU；And, calculate the predictive value of described PU and the error sum of squares of original value；Described error sum of squares can be compared with threshold value, whether the predictive mode judging described PU according to comparative result is skip mode, thus, complete cataloged procedure can be skipped for part PU, such that it is able to reduce the judgement speed improving skip mode, it is favorably improved HEVC code efficiency.
The embodiment of the present invention also provides for a kind of computer-readable recording medium storing one or more program, the one or more program includes instruction, described instruction, when the computer equipment being included one or more processor performs, makes described computer equipment perform the HEVC interframe encode processing method as described in embodiment of the method above.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and the part being not described in certain embodiment may refer to the associated description of other embodiments.
It should be noted that, for aforesaid each method embodiment, in order to be briefly described, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement, because according to the present invention, some step can use other order or carry out simultaneously.Secondly, those skilled in the art also should know, embodiment described in this description belongs to preferred embodiment, necessary to involved action and the module not necessarily present invention.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, the system of foregoing description, the specific works process of device and unit, it is referred to the corresponding process in preceding method embodiment, does not repeats them here.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method, can realize by another way.Such as, device embodiment described above is only schematically, such as, the division of unit, be only a kind of logic function to divide, actual can have when realizing other dividing mode, the most multiple unit or assembly can in conjunction with or be desirably integrated into another system, or some features can ignore, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, device or unit or communication connection, can be electrical, machinery or other form.
The unit illustrated as separating component can be or may not be physically separate, and the parts shown as unit can be or may not be physical location, i.e. may be located at a place, or can also be distributed on multiple NE.Some or all of unit therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it is also possible to be that unit is individually physically present, it is also possible to two or more unit are integrated in a unit.Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ the form of SFU software functional unit realizes.
If integrated unit is using the form realization of SFU software functional unit and as independent production marketing or use, can be stored in a computer read/write memory medium.Based on such understanding, completely or partially can embodying with the form of software product of part that prior art is contributed by technical scheme the most in other words or this technical scheme, this computer software product is stored in a storage medium, including some instructions with so that a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of each embodiment method of the present invention.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-OnlyMemory), the various media that can store program code such as random access memory (RAM, RandomAccessMemory), magnetic disc or CD.
The HEVC interframe encode treating method and apparatus provided the embodiment of the present invention above is described in detail, principle and the embodiment of the present invention are set forth by specific case used herein, and the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, the most all will change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (10)
1. an efficient video coding HEVC interframe encode processing method, it is characterised in that including:
Obtain predictive value and the original value of current predicting unit PU；
Calculate the predictive value of described PU and the error sum of squares of original value；
Described error sum of squares is compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
Method the most according to claim 1, it is characterised in that described described error sum of squares compared with threshold value, judges according to comparative result whether the predictive mode of described PU is that skip mode includes:
Judge that described error sum of squares whether less than described threshold value, the most then judges that the predictive mode of described PU is skip mode.
Method the most according to claim 2, it is characterised in that described judge that described error sum of squares, whether less than after described threshold value, also includes:
If described error sum of squares is not less than described threshold value, calculate the first rate distortion costs of the skip mode of described PU, and, described CU is encoded according to general mode, calculates the second rate distortion costs of described general mode；
Described first rate distortion costs is compared with described second rate distortion costs, judges according to comparative result whether the predictive mode of described PU is skip mode.
Method the most according to claim 3, it is characterised in that described described first rate distortion costs compared with described second rate distortion costs, judges according to comparative result whether the predictive mode of described PU is that skip mode includes:
Judge that whether described first rate distortion costs is less than described second rate distortion costs；
The predictive mode the most then judging described PU is skip mode, otherwise, it is judged that the predictive mode of described PU is general mode.
5. according to described method arbitrary in claim 1 to 5, it is characterised in that described described error sum of squares and threshold value are compared before, also include；
Size according to described PU calculates the threshold value corresponding to described PU with quantization parameter QP.
6. an efficient video coding HEVC interframe encode processing means, it is characterised in that including:
First computing module, for obtaining predictive value and the original value of current predicting unit PU；Calculate the predictive value of described PU and the error sum of squares of original value；
First processing module, for described error sum of squares being compared with threshold value, judges according to comparative result whether the predictive mode of described PU is skip mode.
Device the most according to claim 6, it is characterised in that
Described first processing module, specifically for judging that described error sum of squares whether less than described threshold value, the most then judges that the predictive mode of described PU is skip mode.
Device the most according to claim 7, it is characterised in that also include:
Second computing module, if judging that described error sum of squares, not less than described threshold value, calculates the first rate distortion costs of the skip mode of described PU for described first processing module, and, described CU is encoded according to general mode, calculates the second rate distortion costs of described general mode；
Second processing module, is additionally operable to compare described first rate distortion costs with described second rate distortion costs, judges according to comparative result whether the predictive mode of described PU is skip mode.
Device the most according to claim 8, it is characterised in that
Described second processing module, specifically for judging that whether described first rate distortion costs is less than described second rate distortion costs；The predictive mode the most then judging described PU is skip mode, otherwise, it is judged that the predictive mode of described PU is general mode.
10. according to described device arbitrary in claim 6 to 9, it is characterised in that also include:
3rd computing module, calculates the threshold value corresponding to described PU for the size according to described PU with quantization parameter QP.
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