CN105828066A - Detection method and system of transmission signals - Google Patents
Detection method and system of transmission signals Download PDFInfo
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- CN105828066A CN105828066A CN201610244163.3A CN201610244163A CN105828066A CN 105828066 A CN105828066 A CN 105828066A CN 201610244163 A CN201610244163 A CN 201610244163A CN 105828066 A CN105828066 A CN 105828066A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
- H04N19/89—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
Abstract
The embodiments of the invention disclose a detection method and system of transmission signals. The objective of the invention is to decrease the bit error rate of video signals in a transmission process and improve an image display effect. According to one embodiment of the invention, the method includes the following steps that: video source signals are acquired, signal encoding is performed on the video source signals, so that first encoded data are obtained; check encoding processing is performed on the first encoded data, so that second encoded data can be obtained, wherein the second encoded data include check codes and the first encoded data; the second encoded data are converted into serial low voltage differential signals (LVDS), and the serial low voltage differential signals are transmitted; and the serial low voltage differential signals are received, and are converted into the second encoded data; whether the first encoded data in the second encoded data contain error codes is checked according to the second encoded data; and if the first encoded data do not contain error codes, the first encoded data are decoded, and the video source signals can be obtained.
Description
Technical field
The present invention relates to signal processing technology field, be specifically related to a kind of detection method transmitting signal and system.
Background technology
Low-voltage differential signal (Low-VoltageDifferentialSignaling, it is called for short LVDS) it is a kind of digital video transmission mode, for overcoming transistor-transistor logic level (TransistorTransistorLogic, be called for short TTL) transmission broadband high code rate data time the shortcoming such as big, the electromagnetic interference (ElectromagneticInterference is called for short EMI) of power consumption.LVDS interface utilizes low-down voltage swing (about 350mV) at two printed circuit board (PrintedCircuitBoard, it is called for short PCB) upward wiring or carried out the transmission of data on a pair balanced cable by difference, i.e. low-voltage differential signal transmission.
Owing to LVDS interface uses low pressure and low current type of drive, it is achieved that low noise and low-power consumption, the display interface and the internal display that are widely used in liquid crystal display process on circuit.In liquid crystal display, first by encoding video signal to be shown, and the parallel video data after encoding are converted into the transmission of LVDS differential serial signals.Before display, LVDS differential serial signals is converted into parallel video data, then the decoding of parallel video data is obtained original video signal.If in liquid crystal display systems, if transmission line design is bad, or there is external interference, be easy for occurring error code in transmitting procedure, cause image unstable, occur that image flicker, Hua Ping etc. affect the phenomenon of Consumer's Experience.
Summary of the invention
Because above-mentioned introduction, embodiments provide detection method and the system of a kind of video signal, for reducing the bit error rate that video signal occurs in transmitting procedure, improve image display effect.
First aspect present invention provides the detection method of a kind of video signal, and the detection method of described video signal is applied to the detecting system of video signal, and the detecting system of described video signal includes signal processing circuit and control circuit, it may include:
Described signal processing circuit obtains video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Described signal processing circuit carries out check code process and obtains the second coded data described first coding data, and described second coded data includes check code and described first coding data；
Described second coded data is converted into serial low-voltage differential signal LVDS differential signal by described signal processing circuit, sends described serial LVDS differential signal；
Described control circuit receives serial low-voltage differential signal LVDS differential signal, and described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Whether described control circuit includes error code according to described second coded data, the first coding data verified in described second coded data；
If described first coding data does not comprises error code, described first coding data is decoded, obtains video source signal by described control circuit.
Can be seen that, in the embodiment of the present invention, signal processing circuit first carries out data encoding to the video source signal got, obtain first coding data, the most again first coding data is carried out check code process, obtain the second coded data, the second coded data is carried out the conversion of serial LVDS differential signal the most again, obtains serial LVDS differential signal.This serial LVDS differential signal is received by control circuit, is then converted into the second coded data, then according to the second coded data, verify whether the first coding data in the second coded data has error code, if there is no error code, then first coding data being decoded, obtaining video source signal.In embodiments of the present invention by first coding data being carried out check code process, thus improving the identification ability to error code by increasing check code, efficiently identifying out error code to carry out error code correction in time, improving the stability of image.
Alternatively, in some embodiments of the invention, if described first coding data includes error code, the error code in described first coding data carrying out recovery process, decoding recovers the first coding data after error code, obtains video source signal.
Alternatively, in some embodiments of the invention, described check code is exclusive or check code, parity check code, Hamming checking code and CRC.
Alternatively, in some embodiments of the invention, when described check code is exclusive or check code, described signal processing circuit carries out check code and processes and obtain the second coded data and include described first coding data: described signal processing circuit carries out XOR to every one-dimensional row vector successively, obtain N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively each dimensional vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, described first coding data includes N-dimensional row vector and M dimensional vector；Described signal processing circuit adds the row check code of correspondence in every one-dimensional row vector, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1.
Alternatively, in some embodiments of the invention, described control circuit is according to described second coded data, verify the first coding data in described second coded data whether to include error code and include: described control circuit carries out XOR to the every one-dimensional row vector in described second coded data successively, obtain N+1 the second row operation result, one corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, one corresponding dimensional vector of secondary series operation result；Described control circuit detects i-th the second row operation result and jth secondary series operation result successively, and described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；If described i-th the second row operation result is the first preset value, described jth secondary series operation result is described first preset value or the second preset value, described control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code, or when if described i-th row operation result is described second preset value, described jth column operations result is described first preset value, and described control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code.
Alternatively, in some embodiments of the invention, described control circuit detects i-th the second row operation result and jth secondary series operation result successively, if described i-th the second row operation result is described first preset value, and described jth secondary series operation result is described first preset value, it is determined that the element that the i-th dimension row vector of described first coding data intersects with described jth dimensional vector is error code；Described control circuit negates computing to described error code, and the described first coding data after negating computing is decoded, and obtains video source signal.
Second aspect present invention provides the detecting system of a kind of video signal, including signal processing circuit and control circuit；Wherein, described signal processing circuit includes:
Data coding module, is used for obtaining video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Check code module, obtains the second coded data for described first coding data carries out check code process, and described second coded data includes check code and described first coding data；
Low-voltage differential signal LVDS parallel serial conversion module, for described second coded data is converted into serial low-voltage differential signal LVDS differential signal, sends described serial LVDS differential signal；
Described control circuit includes:
LVDS serioparallel exchange module, is used for receiving serial low-voltage differential signal LVDS differential signal, described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Verification correction module, for according to described second coded data, whether the first coding data verified in described second coded data includes error code；
Decoder module, for when described first coding data does not comprises error code, is decoded described first coding data, obtains video source signal.
Alternatively, in some embodiments of the invention, if described decoder module is additionally operable to described first coding data and includes error code, the error code in described first coding data carrying out recovery process, decoding recovers the first coding data after error code, obtains video source signal.
Alternatively, in some embodiments of the invention, described check code module specifically for, successively every one-dimensional row vector is carried out XOR, obtains N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively each dimensional vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, and described first coding data includes N-dimensional row vector and M dimensional vector；Every one-dimensional row vector is added the row check code of correspondence, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1.
Alternatively, in some embodiments of the invention, described verification correction module further specifically for, successively the every one-dimensional row vector in described second coded data is carried out XOR, obtain N+1 the second row operation result, a corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, a corresponding dimensional vector of secondary series operation result；Detection i-th the second row operation result and jth secondary series operation result successively, described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；If described i-th the second row operation result is the first preset value, described jth secondary series operation result is described first preset value or the second preset value, determine that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code, or when if described i-th row operation result is described second preset value, described jth column operations result is described first preset value, determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code.
Alternatively, in some embodiments of the invention, described verification correction module is additionally operable to, detection i-th the second row operation result and jth secondary series operation result successively, if described i-th the second row operation result is described first preset value, and described jth secondary series operation result is described first preset value, it is determined that the element that the i-th dimension row vector of described first coding data intersects with described jth dimensional vector is error code；Above-mentioned decoder module negates computing to described error code, and the described first coding data after negating computing is decoded, and obtains video source signal.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, the accompanying drawing used required in the embodiment of the present invention will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The structural representation of the detecting system of the video signal that Fig. 1 provides for the embodiment of the present invention；
The schematic flow sheet of the detection method of the video signal that Fig. 2 provides for the embodiment of the present invention；
The schematic flow sheet of the detection method of the video signal that Fig. 3 provides for another embodiment of the present invention；
The check code processing procedure that Fig. 4 provides for the embodiment of the present invention；
The verification error correction process that Fig. 5 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing of the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
Embodiments provide the detection method of a kind of video signal, for effectively correcting error code, improve image display effect.The embodiment of the present invention further correspondingly provides the detecting system of a kind of video signal.
Refer to the structural representation of the detecting system of the video signal that Fig. 1, Fig. 1 provide for the embodiment of the present invention；As it is shown in figure 1, the detecting system of a kind of video signal can include signal processing circuit 10 and control circuit 20, wherein, signal processing circuit 10 includes data coding module 11, check code module 12 and LVDS parallel serial conversion module 13.And control circuit 20 includes LVDS serioparallel exchange module 21, verification correction module 22 and decoder module 23.
Detecting system based on the video signal shown in Fig. 1, refers to the schematic flow sheet of the detection method of the video signal that Fig. 2, Fig. 2 provide for the embodiment of the present invention；As in figure 2 it is shown, the detection method of a kind of video signal comprises the steps that
201, signal processing circuit 10 obtains video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Wherein, signal processing circuit 10 receives video source signal by rgb interface from external equipment.The data form of video source signal common in LCDs has 6bit, 8bit and 10bit.As a example by 8bit, video source signal includes control signal and video data, wherein, control signal includes clock signal (clock), field sync signal (VerticalSynchronization, be called for short VS), line synchronising signal (HorizontalSynchronization, it is called for short HS) and data effectively (DataEnable, vehicle economy), video data includes red component (Red), green component (Green) and blue component (Blue).
Then, signal processing circuit 10 carries out data encoding to video source signal, the control signal in video source signal is encoded together with video data, obtains first coding data.
202, signal processing circuit 10 carries out check code process and obtains the second coded data described first coding data, and described second coded data includes check code and described first coding data；
Signal processing circuit 10, by carrying out check code process, then increases check code, to obtain the second coded data in first coding data.By first coding data is carried out check code process, so that control circuit can identify error code in time, improve the stability that image shows.
It is to be appreciated that the second coded data that coding obtains shows, in the matrix form including N-dimensional row vector and M dimensional vector.
203, described second coded data is converted into serial low-voltage differential signal LVDS differential signal by signal processing circuit, sends described serial LVDS differential signal；
It is appreciated that signal processing circuit and control circuit are the process circuit within liquid crystal display, is connected by LVDS interface between the two, between the two transmission LVDS differential signal.Before being transmitted, the second coded data is first converted into the LVDS differential signal of serial by signal processing circuit.
204, control circuit receives serial low-voltage differential signal LVDS differential signal, and described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Wherein, signal processing circuit receives video source signal, mainly completes the data encoding to video source signal, check code and the conversion of LVDS differential signal.After control circuit receives the serial LVDS differential signal of signal processing circuit, first serial LVDS differential signal is converted into the second coded data, mainly serial LVDS differential signal is converted into the second parallel coded data.
205, whether control circuit includes error code according to described second coded data, the first coding data verified in described second coded data；
Control circuit, according to the second coded data, verifies whether the first coding data in the second coded data includes error code.
If 206 described first coding datas do not comprise error code, described first coding data is decoded by control circuit, obtains video source signal.
When determining that first coding data does not has error code, first coding data is decoded by control circuit, obtains video source signal, and video source signal carries out later stage process, such as controls it in liquid crystal display screen display.
Certainly, when determining that first coding data includes error code, first error code is carried out recovery process, then further decoding, will be described in detail follow-up, and not repeat them here.
Can be seen that, in the embodiment of the present invention, signal processing circuit first carries out data encoding to the video source signal got, obtain first coding data, the most again first coding data is carried out check code process, obtain the second coded data, the second coded data is carried out the conversion of serial LVDS differential signal the most again, obtains serial LVDS differential signal.This serial LVDS differential signal is received by control circuit, is then converted into the second coded data, then according to the second coded data, verify whether the first coding data in the second coded data has error code, if there is no error code, then first coding data being decoded, obtaining video source signal.In embodiments of the present invention by first coding data being carried out check code process, thus improving the identification ability to error code by increasing check code, efficiently identifying out error code to carry out error code correction in time, improving the stability of image.
Alternatively, in embodiments of the present invention, above-mentioned check code can be exclusive or check code, parity check code, Hamming checking code and CRC.
Technical solution of the present invention will be discussed in detail below as a example by check code is for exclusive or check code.Refer to the schematic flow sheet of the detection method of the video signal that Fig. 3, Fig. 3 provide for another embodiment of the present invention；As it is shown on figure 3, the detection method of a kind of video signal comprises the steps that
301, signal processing circuit obtains video source signal, described video source signal is carried out Signal coding and obtains first coding data；
302, signal processing circuit carries out XOR to every one-dimensional row vector successively, obtain N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively every one-dimensional first row vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, and described first coding data includes N-dimensional row vector and M dimensional vector；
303, signal processing circuit adds the row check code of correspondence in every one-dimensional row vector, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1；
Wherein, first coding data is a matrix including N-dimensional row vector and M dimensional vector, respectively every one-dimensional row vector is carried out XOR, obtain the first row operation result that every one-dimensional row vector is corresponding, wherein, if the first row operation result is 1, obtaining row check code corresponding to this dimension row vector is 0, if the first row operation result is 0, obtaining row check code corresponding to this dimension row vector is 1, then the row check code of its correspondence on increasing after every one-dimensional row vector, thus on first coding data, add a dimensional vector.Equally, respectively each dimensional vector is carried out XOR, obtain the first row operation result that each dimensional vector is corresponding, wherein, if first row operation result is 1, the row check code that this dimensional vector is corresponding is 0, if first row operation result is 0, the row check code that this dimensional vector is corresponding is 1, then the row check code of its correspondence on increasing after each dimensional vector, thus on first coding data, add one-dimensional row vector, therefore, the second coded data is one and includes N+1 dimension row vector and the matrix of M+1 dimensional vector.
304, control circuit receives serial LVDS signal, and serial LVDS signal is converted into the second coded data；
305, control circuit carries out XOR to the every one-dimensional row vector in the second coded data successively, obtain N+1 the second row operation result, one corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, a corresponding dimensional vector of secondary series operation result；
Whether control circuit verification first coding data has error code, specifically the every one-dimensional row vector of the second coded data is carried out XOR, obtain the second row operation result that every one-dimensional row vector is corresponding, equally, each dimensional vector is carried out XOR, obtains the secondary series operation result that each dimensional vector is corresponding.
Being appreciated that the second row operation result is 1 or 0, secondary series operation result is 1 or 0.
306, control circuit detects i-th the second row operation result and jth secondary series operation result successively, and described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；
If 307 described i-th the second row operation results are the first preset value, described jth secondary series operation result is described first preset value or the second preset value, and control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code；
After all of second row operation result and secondary series operation result are carried out step 307 process, turn to step 310.
If 308 described i-th the second row operation results are the second preset value, described jth secondary series operation result is described first preset value, and control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code；
After all of second row operation result and secondary series operation result are carried out step 308 process, turn to step 310.
If 309 described i-th the second row operation results are described first preset value, and described jth secondary series operation result is described first preset value, it is determined that the element that the i-th dimension row vector of described first coding data intersects with described jth dimensional vector is error code；
Wherein, the embodiment of the present invention judging, whether first coding data has error code to include following three kinds of situations:
Situation 1, if all second row operation results are 1, and all secondary series operation results are 1, illustrate not have in first coding data error code.
Situation 2, if all second row operation results are 1, and any one secondary series operation result is 0, say, that row vector is all correct, and column vector mistake, then explanation wrong data occurs on row identifying code, and first coding data does not has error code；Or, if all secondary series operation results are 1, and any one second row operation result is 0, say, that column vector is all correct, and row vector mistake, then explanation wrong data occurs being expert on identifying code, and first coding data does not has error code.
Situation 3, if any one second row operation result is 0, and any one secondary series operation result is 0, then illustrate that the row vector at this second row operation result place is error code with the element that intersects of the column vector at this secondary series operation result place.
Execution of step 309 turns to step 311.
310, first coding data is decoded by control circuit, obtains video source signal；
311, control circuit negates computing to described error code, and the described first coding data after negating computing is decoded, and obtains video source signal.
When having error code in first coding data, this error code is negated computing, obtain just data, thus get video source signal.Wherein, owing to first coding data is the signal represented with " 0 " and " 1 ", so negating computing is exactly to represent the inverse operation between 0 and 1, such as, when error code is 0, negates computing and obtain 1, when error code is 1, negates computing and obtain 0.
XOR by 8bitVESA data form and the above-mentioned two dimension of employing illustrates as a example by obtaining check code below.As shown in Figure 4, in signal processing circuit, video source signal is through data encoding, 4 groups of data Tx0 after being encoded, Tx1, Tx2, Tx3, wherein, Tx0 includes that R0, R1, R2, R3, R4, R5 and G0, Tx1 include G1, G2, G3, G4, G5, B0 and B1, Tx2 includes that B2, B3, B4, B5, HS, VS and DE, Tx3 include R6, R7, G6, G7, B6, B7 and 0.Then these 4 groups of data are made check code process, increase redundancy check bit, namely check code, obtain new coded data.Here XOR is used to obtain check code.The rule of XOR is that 0 XOR 1 is equal to 0 equal to 1,0 XOR 0 equal to 0,1 XOR 1, requires that data bit and check bit are 1 after XOR accordingly.As shown in Figure 4, data R0 former to Tx0 in row vector, R1, R2, R3, R4, R5, G0 carry out XOR, if operation result is 1, then increasing check bit H0 is 0, if operation result is 0, then increasing check bit H0 is 1, in like manner increases other check bit H1 to H3.To the 1st column data R0 in column vector, G1, B2, R2 carry out XOR, if operation result is 1, then increasing check bit V0 is 0, if operation result is 0, then increasing check bit V0 is 1, in like manner increases check bit V1 to V6.So through increasing after check bit, 4 groups of coded data Tx0, Tx1, Tx2, Tx3 be converted into 5 groups of coded data VTx0, VTx1, VTx2, VTx3, VTx4, and then reconvert becomes serial LVDS differential signal to be transmitted.
In control circuit, first serial LVDS differential signal is converted into parallel data VRx0, VRx1, VRx2, VRx3, VRx4, then carries out verifying error correction.The method of verification is each data R0 in row vector to VRx0, and R1, R2, R3, R4, R5, G0, H0 carry out XOR, if operation result is 1, then explanation the row data are correct, if operation result is 0, then explanation the row data are made mistakes.In like manner to VRx1, VRx2, VRx3 are also carried out verification.To the 1st each data R0 arranged in column vector, G1, B2, R2, V0 carry out XOR, if operation result is 1, then illustrates that this column data is correct, if operation result is 0, then illustrate that this column data is made mistakes.In like manner the 2nd to the 7th row are also carried out verification.Three kinds of situations can be divided to verify according to check results:
1, number of lines and columns are according to all makeing mistakes, then the element of joining is error code, wrong data is negated and obtains just data；
2, certain data line is made mistakes, and column data is correct, illustrates that wrong data is expert on check bit H0 to H3, does not has error code；
3, a certain column data is made mistakes, and row data are correct, illustrate that wrong data, on row check bit V0 to V6, does not has error code.
As it is shown in figure 5, after carrying out data check according to three cases above, remove check bit, thus obtain correct data Rx0, Rx1, Rx2, Rx3.Then to decoding data, video source signal is recovered.
Incorporated by reference to Fig. 1, data coding module 11 that the signal processing circuit 10 that the embodiment of the present invention provides includes, check code module 12 and LVDS parallel serial conversion module 13 are mainly used in realizing following functions:
Data coding module 11, is used for obtaining video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Check code module 12, obtains the second coded data for described first coding data carries out check code process, and described second coded data includes check code and described first coding data；
LVDS parallel serial conversion module 13, for described second coded data is converted into serial low-voltage differential signal LVDS differential signal, sends described serial LVDS differential signal.
And LVDS serioparallel exchange module 21 in control circuit 20, verification correction module 22 and decoder module 23 realize following functions:
LVDS serioparallel exchange module 21, is used for receiving serial low-voltage differential signal LVDS differential signal, described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Verification correction module 22, for according to described second coded data, whether the first coding data verified in described second coded data includes error code；
Decoder module 23, for when described first coding data does not comprises error code, is decoded described first coding data, obtains video source signal.
Can be seen that, in the embodiment of the present invention, the data coding module 11 of signal processing circuit 10 first carries out data encoding to the video source signal got, obtain first coding data, check code module 12 carries out check code process to first coding data again, obtain the second coded data, then the second coded data is carried out the conversion of serial LVDS differential signal by LVDS parallel serial conversion module 13 again, obtains serial LVDS differential signal.This serial LVDS differential signal is received by the LVDS serioparallel exchange module 21 of control circuit 20, it is then converted into the second coded data, verification correction module 22 is according to the second coded data, verify whether the first coding data in the second coded data has error code, if there is no error code, first coding data is then decoded by decoder module 23, obtains video source signal.In embodiments of the present invention by first coding data being carried out check code process, thus improving the identification ability to error code by increasing check code, efficiently identifying out error code to carry out error code correction in time, improving the stability of image.
Alternatively, in some embodiments of the invention, if above-mentioned decoder module 23 is additionally operable to described first coding data and includes error code, the error code in described first coding data carrying out recovery process, decoding recovers the first coding data after error code, obtains video source signal.
Alternatively, in some embodiments of the invention, above-mentioned check code module 12 further specifically for, successively every one-dimensional row vector is carried out XOR, obtain N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively each dimensional vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, and described first coding data includes N-dimensional row vector and M dimensional vector；Every one-dimensional row vector is added the row check code of correspondence, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1.
Alternatively, in some embodiments of the invention, above-mentioned check code module 22 further specifically for, successively the every one-dimensional row vector in described second coded data is carried out XOR, obtain N+1 the second row operation result, a corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, a corresponding dimensional vector of secondary series operation result；Detection i-th the second row operation result and jth secondary series operation result successively, described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；If described i-th the second row operation result is the first preset value, described jth secondary series operation result is described first preset value or the second preset value, determine that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code, or when if described i-th row operation result is described second preset value, described jth column operations result is described first preset value, determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code.
Alternatively, in some embodiments of the invention, above-mentioned verification correction module 22 is additionally operable to, detection i-th the second row operation result and jth secondary series operation result successively, if described i-th the second row operation result is described first preset value, and described jth secondary series operation result is described first preset value, it is determined that the element that the i-th dimension row vector of described first coding data intersects with described jth dimensional vector is error code.Determine that first coding data has error code, decoder module 23 that error code is negated computing in verification correction module 22, then the first coding data after negating computing is decoded, obtains video source signal.
Alternatively, above-mentioned check code is not limited only to exclusive or check code, it is also possible to be parity check code, Hamming checking code and CRC.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not has the part described in detail, may refer to the associated description of other embodiments in certain embodiment.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, the system of foregoing description, the specific works process of device and unit, it is referred to the corresponding process in preceding method embodiment, does not repeats them here.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method, can realize by another way.Such as, device embodiment described above is only schematically, such as, the division of described unit, be only a kind of logic function to divide, actual can have when realizing other dividing mode, the most multiple unit or assembly can in conjunction with or be desirably integrated into another system, or some features can ignore, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, device or unit or communication connection, can be electrical, machinery or other form.
The described unit illustrated as separating component can be or may not be physically separate, and the parts shown as unit can be or may not be physical location, i.e. may be located at a place, or can also be distributed on multiple NE.Some or all of unit therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it is also possible to be that unit is individually physically present, it is also possible to two or more unit are integrated in a unit.Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ the form of SFU software functional unit realizes.
If described integrated unit is using the form realization of SFU software functional unit and as independent production marketing or use, can be stored in a computer read/write memory medium.Based on such understanding, completely or partially can embodying with the form of software product of part that prior art is contributed by technical scheme the most in other words or this technical scheme, this computer software product is stored in a storage medium, including some instructions with so that a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-OnlyMemory), the various media that can store program code such as random access memory (RAM, RandomAccessMemory), magnetic disc or CD.
Above a kind of detection method transmitting signal provided by the present invention and system are described in detail, for one of ordinary skill in the art, thought according to the embodiment of the present invention, the most all will change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (10)
1. the detection method of a video signal, it is characterised in that the detection method of described video signal is applied to the detecting system of video signal, the detecting system of described video signal includes that signal processing circuit and control circuit, described method include:
Described signal processing circuit obtains video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Described signal processing circuit carries out check code process and obtains the second coded data described first coding data, and described second coded data includes check code and described first coding data；
Described second coded data is converted into serial low-voltage differential signal LVDS differential signal by described signal processing circuit, sends described serial LVDS differential signal；
Described control circuit receives serial low-voltage differential signal LVDS differential signal, and described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Whether described control circuit includes error code according to described second coded data, the first coding data verified in described second coded data；
If described first coding data does not comprises error code, described first coding data is decoded, obtains video source signal by described control circuit.
Method the most according to claim 1, it is characterised in that described method also includes:
If described first coding data includes error code, the error code in described first coding data carrying out recovery process, decoding recovers the first coding data after error code, obtains video source signal.
Method the most according to claim 1, it is characterised in that described check code is exclusive or check code, parity check code, Hamming checking code and CRC.
Method the most according to claim 3, it is characterised in that when described check code is exclusive or check code, described signal processing circuit carries out check code and processes and obtain the second coded data and include described first coding data:
Described signal processing circuit carries out XOR to every one-dimensional row vector successively, obtain N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively each dimensional vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, and described first coding data includes N-dimensional row vector and M dimensional vector；
Described signal processing circuit adds the row check code of correspondence in every one-dimensional row vector, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1.
Method the most according to claim 4, it is characterised in that described control circuit, according to described second coded data, verifies the first coding data in described second coded data and whether includes error code and include:
Described control circuit carries out XOR to the every one-dimensional row vector in described second coded data successively, obtain N+1 the second row operation result, one corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, a corresponding dimensional vector of secondary series operation result；
Described control circuit detects i-th the second row operation result and jth secondary series operation result successively, and described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；
If described i-th the second row operation result is the first preset value, described jth secondary series operation result is described first preset value or the second preset value, described control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code, or when if described i-th row operation result is described second preset value, described jth column operations result is described first preset value, and described control circuit then determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code.
6. according to the method described in claim 4 or 5, it is characterised in that described method also includes:
Described control circuit detects i-th the second row operation result and jth secondary series operation result successively, if described i-th the second row operation result is described first preset value, and described jth secondary series operation result is described first preset value, it is determined that the element that the i-th dimension row vector of described first coding data intersects with described jth dimensional vector is error code；
Described control circuit negates computing to described error code, and the described first coding data after negating computing is decoded, and obtains video source signal.
7. the detecting system of a video signal, it is characterised in that include signal processing circuit and control circuit；Wherein, described signal processing circuit includes:
Data coding module, is used for obtaining video source signal, described video source signal is carried out Signal coding and obtains first coding data；
Check code module, obtains the second coded data for described first coding data carries out check code process, and described second coded data includes check code and described first coding data；
Low-voltage differential signal LVDS parallel serial conversion module, for described second coded data is converted into serial low-voltage differential signal LVDS differential signal, sends described serial LVDS differential signal；
Described control circuit includes:
LVDS serioparallel exchange module, is used for receiving serial low-voltage differential signal LVDS differential signal, described serial LVDS differential signal is converted into the second coded data, and described second coded data includes check code and first coding data；
Verification correction module, for according to described second coded data, whether the first coding data verified in described second coded data includes error code；
Decoder module, for when described first coding data does not comprises error code, is decoded described first coding data, obtains video source signal.
System the most according to claim 7, it is characterised in that
If described decoder module is additionally operable to described first coding data includes error code, the error code in described first coding data carrying out recovery process, decoding recovers the first coding data after error code, obtains video source signal.
9. according to the system described in claim 7 or 8, it is characterised in that
Described check code module specifically for, successively every one-dimensional row vector is carried out XOR, obtain N number of the first row operation result, the corresponding one-dimensional row vector of each the first row operation result, and successively each dimensional vector is carried out XOR, obtain M first row operation result, the corresponding dimensional vector of each first row operation result, described N and described M is positive integer, and described first coding data includes N-dimensional row vector and M dimensional vector；Every one-dimensional row vector is added the row check code of correspondence, and on each dimensional vector, add the row check code of correspondence, obtain described second coded data, described second coded data includes N+1 dimension row vector and M+1 dimensional vector, wherein, if described the first row operation result is 1, the row check code of the row vector that described the first row operation result is corresponding is 0, if described the first row operation result is 0, the row check code of the row vector that described the first row operation result is corresponding is 1；If described first row operation result is 1, the row check code of the column vector that described first row operation result is corresponding is 0, if described first row operation result is 0, the row check code of the column vector that described first row operation result is corresponding is 1.
System the most according to claim 9, it is characterised in that
Described verification correction module further specifically for, successively the every one-dimensional row vector in described second coded data is carried out XOR, obtain N+1 the second row operation result, one corresponding one-dimensional row vector of the second row operation result, and successively each dimensional vector in described second coded data is carried out XOR, obtain M+1 secondary series operation result, a corresponding dimensional vector of secondary series operation result；Detection i-th the second row operation result and jth secondary series operation result successively, described i is the positive integer more than or equal to 1 and less than or equal to described N, and described j is the positive integer being more than or equal to and being less than or equal to described M；If described i-th the second row operation result is the first preset value, described jth secondary series operation result is described first preset value or the second preset value, determine that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code, or when if described i-th row operation result is described second preset value, described jth column operations result is described first preset value, determines that the element that the i-th dimension row vector of described first coding data and jth dimensional vector intersect is not error code.
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