CN105827392A

CN105827392A - Simplest series memristor circuit

Info

Publication number: CN105827392A
Application number: CN201610272443.5A
Authority: CN
Inventors: 李博雅
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-04-28
Filing date: 2016-04-28
Publication date: 2016-08-03

Abstract

The invention relates to a simplest series memristor circuit and belongs to the field of electric power system and electronic information. A memristor is a fourth basic element different from a resistor, a capacitor and an inductor, and is a circuit device for expressing the relationship between magnetic flux and electric charge. A memristor has a dimension of a resistor. The simplest series memristor circuit is composed of an inductor, a capacitor and a memristor which are in series connection. The circuit is composed of a three-way resistor, a capacitor and an operational amplifier (LF347BN) and a multiplying unit (AD633JN). The resistor and the operation amplifier (LF347BN) realize reverse-phase addition and reverse-phase operation. The capacitor and the operational amplifier realize integral operation. Multiplication is realized by the multiplying unit (AD633JN). The aforementioned configuration plays an important role in the application of the memristor to artificial neuron network synapses and chaotic circuit, so that the circuit is widely applied to secret communication.

Description

One the simplest series connection memristor circuit

Technical field

The present invention relates to one the simplest memristor circuit, belong to power system and electronic information field.

Background technology

Memristor (Memristor) is different from the 4th kind of primary element of resistance, electric capacity and inductance, it it is the circuit devcie representing magnetic flux with charge relationship, memristor has the dimension of resistance, but with unlike resistance, the resistance of resistance is to be determined by the electric current flowing through it, and the resistance of memristor is to be determined by the electric charge flowing through it, therefore, by measuring the resistance of memristor, just may know that the quantity of electric charge flowing through it, thus have the effect of memory electric charge.1971, the Cai Shaotang professor of Univ California-Berkeley pointed out from the viewpoint of logic and axiom, and nature should there is also a component, and it represents the relation of magnetic flux and electric charge；Memristor can be divided into 2 classes according to the difference of change object, a class is the memristor that curent change is controlled by magnetic flux, referred to as magnetic control memristor, and its electric current is represented by with the relational expression of voltageMagnetic flux is represented by with the relation of voltageAnother kind of be change in voltage by the memristor of Charge controlled, referred to as lotus control memristor, the relational expression of its voltage and electric current is represented by u_M=M (q, u_M)i_M, electric charge is represented by dq/dt=f (i with the relational expression of electric current_M,q)；

2008, the research worker of Hewlett-Packard made nanometer memory resistor first, started memristor research boom；The appearance of nanometer memory resistor, it is expected to realize non-volatile RAM, and, the integrated level of random access memory based on memristor, power consumption, read or write speed will be more superior than traditional random access memory, memristor is the best way that hardware realizes artificial neural network synapse, due to the non-linear nature of memristor, chaos circuit can be produced, thus in secret communication, also have a lot of application.

Summary of the invention

The technical problem to be solved in the present invention is to provide one the simplest memristor circuit:

1. the simplest series connection memristor circuit, it is characterised in that: the simplest series connection memristor circuit is composed in series by an inductance, an electric capacity and a memristor, and memristor model used is lotus control memristor, and its voltage is represented by V with the relational expression of electric current_M=M (q, u_M)i_M, electric charge is represented by dq/dt=f (i with the relational expression of electric current_M, q), Kirchhoff's second law obtain:

\{\begin{matrix} C \frac{{dV}_{C}}{d t} = i_{L} \\ L \frac{{di}_{L}}{d t} = - V_{c} - M (q) i_{L} \\ \frac{d q}{d t} = f (i_{L}) q - k \cdot i_{L} \end{matrix} - - - (i)

If V_c=x, i_L=y, q=z, 1/C=b, 1/L=c then system i can become:

\{\begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - M (z) y \\ \overset{\cdot}{z} = f (y) z - k y \end{matrix} - - - (i i)

If M (z)=β (z²-1), f (y)=y-α then system (ii) can become:

{\begin{matrix} \begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - β (z^{2} - 1) y \\ \overset{\cdot}{z} = (y - α) z - k y \end{matrix} & α = 0.6, β = 1 / 2, b = 1, c = 1 / 3, k = 1 \end{matrix} - - - (i i i)

(ii) and in (iii) formula, x, y, z are state variables, and α, β, b, c, k are parameters；

When α=0.6, β=1/2, when b=1, c=1/3, k=1, system produces chaotic signal, designing circuit according to system iii, circuit is made up of three road resistance, electric capacity and operational amplifier (LF347BN) and multiplier (AD633JN), and resistance and operational amplifier (LF347BN) realize anti-phase addition and anti-phase computing, electric capacity and operational amplifier (LF347BN) realize integral operation, and multiplication is realized by multiplier AD633JN；

The anti-phase addition input of the first via connects the anti-phase integration output on the second tunnel；The anti-phase addition input on the second tunnel connects the anti-phase integration output on the second tunnel, connect the anti-phase output of the first via, connect the output of multiplier (A1), the anti-phase output on the input of multiplier (A1) the second tunnel respectively and the output of multiplier (A3), the input of multiplier (A3) connects the anti-phase integration output on the 3rd tunnel respectively；The anti-phase addition input on the 3rd tunnel connects the anti-phase output on the second tunnel, connects the anti-phase output on the 3rd tunnel, connects the output of multiplier (A2), and the input of multiplier (A2) connects the anti-phase integration output on the second tunnel and the anti-phase integration output on the 3rd tunnel.

2, described a kind of lotus control memristor circuit is characterized in that: this electricity routing resistance, electric capacity and operational amplifier (AD712JN) and multiplier (AD633JN) composition, resistance and operational amplifier (AD712JN) realize anti-phase addition and anti-phase computing, electric capacity and operational amplifier (AD712JN) realize integral operation, and multiplication is realized by multiplier (AD633JN)；

nullThe negative input end of described operational amplifier (AD712JN) U3B connects one end of electric capacity C1 by resistance Rs2 and resistance Rs，The outfan of operational amplifier (AD712JN) U3B is connect by resistance Rs1，The positive input terminal of operational amplifier (AD712JN) U3B meets electric capacity C1 and by electronics Rs4 ground connection by resistance Rs3，1st pin of output termination multiplier (AD633JN) U4 of operational amplifier (AD712JN) U3B，The outfan of operational amplifier (AD712JN) U3B connects the negative input end of operational amplifier (AD712JN) U2A by resistance R8，The outfan of operational amplifier (AD712JN) U3B connects the negative input end of operational amplifier (AD712JN) U3A by resistance R6；The negative input end of described operational amplifier (AD712JN) U3A connects the outfan of operational amplifier (AD712JN) U3A, the positive input terminal ground connection of operational amplifier (AD712JN) U3A by resistance α 5kpot；The negative supply termination Vee of positive supply the termination Vcc, operational amplifier (AD712JN) U3A of operational amplifier (AD712JN) U3A；nullThe 2nd pin ground connection of described multiplier (AD633JN) U4，3rd pin of multiplier (AD633JN) U4 connects the outfan of operational amplifier (AD712JN) U2B，The 4th pin ground connection of multiplier (AD633JN) U4，Multiplier (AD633JN) U4 the 5th pin meet Vee，6th pin of multiplier (AD633JN) U4 passes through resistance R10kpot ground connection，7th pin of multiplier (AD633JN) U4 connects the 2nd pin of multiplier (AD633JN) U5，The negative input end of operational amplifier (AD712JN) U2B is connect by resistance Ra，The 6th pin of multiplier (AD633JN) U4 is connect by resistance R1，By resistance R1 and resistance R10kpot ground connection，8th pin of multiplier (AD633JN) U4 meets Vcc；nullThe 1st pin ground connection of described multiplier (AD633JN) U5，3rd pin of multiplier (AD633JN) U5 connects the outfan of operational amplifier (AD712JN) U2B，The 4th pin ground connection of multiplier (AD633JN) U5，5th pin of multiplier (AD633JN) U5 meets Vee，6th pin of multiplier (AD633JN) U5 passes through resistance R10kpot_2 ground connection，7th pin of multiplier (AD633JN) U5 connects the 6th pin of multiplier (AD633JN) U5 by resistance R1_2，By resistance R1_2 and resistance R10kpot_2 ground connection，The negative input end of operational amplifier (AD712JN) U3A is connect by resistance R5，8th pin of multiplier (AD633JN) U5 meets Vcc；The positive input terminal ground connection of described operational amplifier (AD712JN) U2A, the negative input end of operational amplifier (AD712JN) U2A connects the outfan of operational amplifier (AD712JN) U2A by resistance R7, the outfan of operational amplifier (AD712JN) U2A connects the negative input end of operational amplifier (AD712JN) U2B by resistance Rb, the positive supply of operational amplifier (AD712JN) U2A meets the negative supply termination Vcc of Vcc, operational amplifier (AD712JN) U2A；The negative input end of described operational amplifier (AD712JN) U2B connects the outfan of operational amplifier (AD712JN) U2B by resistance α 10kpot, the outfan of operational amplifier (AD712JN) U2B is connect by electric capacity Cf, 3rd pin of output termination multiplier (AD633JN) U4 of operational amplifier (AD712JN) U2B, connects the 3rd pin of multiplier (AD633JN) U5；One end of another termination inductance L of described electric capacity C1, the other end ground connection of inductance L.

Beneficial effect: the present invention proposes one and includes that electric capacity, inductance and four kinds of primary elements of memristor constitute a circuit, and propose 2 kinds of basic circuit forms of series connection, this circuit is achieved with analog circuit equivalence, this plays an important role for memristor application in realizing artificial neural network synapse and chaos circuit, thus also has a lot of application in secret communication.

Accompanying drawing explanation

Fig. 1 is the simplest series connection memristor circuit diagram.

Fig. 2 is the internal circuit diagram of the simplest series connection memristor.

Fig. 3 is the circuit diagram of the simplest series connection memristor circuit realized.

Detailed description of the invention

With preferred embodiment, the present invention is further described in detail below in conjunction with the accompanying drawings, sees Fig. 1-Fig. 3.

\{\begin{matrix} C \frac{{dV}_{C}}{d t} = i_{L} \\ L \frac{{di}_{L}}{d t} = - V_{c} - M (q) i_{L} \\ \frac{d q}{d t} = f (i_{L}) q - k \cdot i_{L} \end{matrix} - - - (i)

If V_c=x, i_L=y, q=z, 1/C=b, 1/L=c then system i can become:

\{\begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - M (z) y \\ \overset{\cdot}{z} = f (y) z - k y \end{matrix} - - - (i i)

If M (z)=β (z²-1), f (y)=y-α then system (ii) can become:

{\begin{matrix} \begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - β (z^{2} - 1) y \\ \overset{\cdot}{z} = (y - α) z - k y \end{matrix} & α = 0.6, β = 1 / 2, b = 1, c = 1 / 3, k = 1 \end{matrix} - - - (i i i)

Certainly, described above not restriction to invention, the present invention is also not limited to the example above, change that those skilled in the art are made in the essential scope of the present invention, retrofits, adds or replaces, and falls within protection scope of the present invention.

Claims

\{\begin{matrix} C \frac{{dV}_{C}}{d t} = i_{L} \\ L \frac{{di}_{L}}{d t} = - V_{c} - M (q) i_{L} \\ \frac{d q}{d t} = f (i_{L}) q - k \cdot i_{L} \end{matrix} - - - (i)

If V_c=x, i_L=y, q=z, 1/C=b, 1/L=c then system i can become:

\{\begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - M (z) y \\ \overset{\cdot}{z} = f (y) z - k y \end{matrix} - - - (i i)

If M (z)=β (z²-1), f (y)=y-α then system (ii) can become:

\begin{matrix} \{\begin{matrix} \overset{\cdot}{x} = b y \\ \overset{\cdot}{y} = - c x - β (z^{2} - 1) y \\ \overset{\cdot}{z} = (y - α) z - k y \end{matrix} & α = 0.6, β = 1 / 2, b = 1, c = 1 / 3, k = 1 & (i i i) \end{matrix}

2. described in, a kind of lotus control memristor circuit is characterized in that: this electricity routing resistance, electric capacity and operational amplifier (AD712JN) and multiplier (AD633JN) composition, resistance and operational amplifier (AD712JN) realize anti-phase addition and anti-phase computing, electric capacity and operational amplifier (AD712JN) realize integral operation, and multiplication is realized by multiplier (AD633JN)；