CN105826336A - Solid-state image pickup device and method for manufacturing a solid-state image pickup device - Google Patents
Solid-state image pickup device and method for manufacturing a solid-state image pickup device Download PDFInfo
- Publication number
- CN105826336A CN105826336A CN201610028492.4A CN201610028492A CN105826336A CN 105826336 A CN105826336 A CN 105826336A CN 201610028492 A CN201610028492 A CN 201610028492A CN 105826336 A CN105826336 A CN 105826336A
- Authority
- CN
- China
- Prior art keywords
- type
- floating diffusion
- semiconductor layer
- region
- solid photography
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 116
- 238000009792 diffusion process Methods 0.000 claims abstract description 77
- 238000007667 floating Methods 0.000 claims abstract description 77
- 238000006243 chemical reaction Methods 0.000 claims abstract description 71
- 239000007787 solid Substances 0.000 claims description 55
- 239000012535 impurity Substances 0.000 claims description 21
- 230000008859 change Effects 0.000 claims description 17
- 238000005286 illumination Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 241000206607 Porphyra umbilicalis Species 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 66
- 230000005540 biological transmission Effects 0.000 description 55
- 238000003860 storage Methods 0.000 description 33
- 101100243108 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PDI1 gene Proteins 0.000 description 17
- 238000010586 diagram Methods 0.000 description 17
- 239000000203 mixture Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 238000012545 processing Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 9
- IRLPACMLTUPBCL-KQYNXXCUSA-N 5'-adenylyl sulfate Chemical compound C1=NC=2C(N)=NC=NC=2N1[C@@H]1O[C@H](COP(O)(=O)OS(O)(=O)=O)[C@@H](O)[C@H]1O IRLPACMLTUPBCL-KQYNXXCUSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- UXFQFBNBSPQBJW-UHFFFAOYSA-N 2-amino-2-methylpropane-1,3-diol Chemical compound OCC(N)(C)CO UXFQFBNBSPQBJW-UHFFFAOYSA-N 0.000 description 6
- 101150035093 AMPD gene Proteins 0.000 description 6
- 230000000875 corresponding effect Effects 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000001629 suppression Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005693 optoelectronics Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000012163 sequencing technique Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 101100476641 Homo sapiens SAMM50 gene Proteins 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 102100035853 Sorting and assembly machinery component 50 homolog Human genes 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- -1 copper Chemical class 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14607—Geometry of the photosensitive area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Ceramic Engineering (AREA)
Abstract
The invention relates to a solid-state image pickup device and a method for manufacturing a solid-state image pickup device. The solid-state image pickup device includes a semiconductor layer, a photoelectric conversion element, floating diffusion, a plurality of gates, and a semiconductor region. The photoelectric conversion element is provided in the semiconductor laver. The floating diffusion is provided at a shallow position at a side of one surface of the semiconductor layer. The plurality of gates are each provided adjacent to the floating diffusion and extend toward the photoelectric conversion element in a direction of a depth of the semiconductor layer. The semiconductor region is provided between the gates to face the floating diffusion.
Description
[related application]
The application enjoys the interests of the priority of Japanese patent application No. 2015-011336 that on January 23rd, 2015 files an application, and the full content of this Japanese patent application is quoted in this application.
Technical field
Present embodiment usually relates to the manufacture method of a kind of device for solid photography and device for solid photography.
Background technology
In the past, device for solid photography possesses: photo-electric conversion element, is arranged on semiconductor layer, and incident illumination opto-electronic conversion is become signal charge；And floating diffusion region, temporarily keep the signal charge from photo-electric conversion element transmission.
As described device for solid photography, exist and possess photo-electric conversion element and the device for solid photography of a trench-gate, described photo-electric conversion element is arranged on the position that the ratio floating diffusion region of semiconductor layer is deep, and described trench-gate is adjacent with floating diffusion region and sets, and extends towards photo-electric conversion element.
Possess the device for solid photography of a trench-gate by the transmission voltage applying to specify to trench-gate, and form passage in the side of the side, floating diffusion region of trench-gate.And, signal charge is transmitted to floating diffusion region from photo-electric conversion element by device for solid photography through passage.But, described device for solid photography from photo-electric conversion element to the transmission characteristic of the signal charge of floating diffusion region insufficient.
Summary of the invention
Embodiments of the present invention provide a kind of can raising from photo-electric conversion element to device for solid photography and the manufacture method of device for solid photography of the transmission characteristic of the signal charge of floating diffusion region.
The device for solid photography of present embodiment possesses semiconductor layer, photo-electric conversion element, floating diffusion region, multiple grid and semiconductor regions.Photo-electric conversion element is arranged on described semiconductor layer.Floating diffusion region is arranged on the shallower position of a face side of described semiconductor layer.Multiple grids are adjacent with described floating diffusion region respectively and set, and extend towards described photo-electric conversion element toward the depth direction of described semiconductor layer.Semiconductor regions is arranged between described grid towards described floating diffusion region.
Accompanying drawing explanation
Fig. 1 is the block diagram of the schematic configuration of the digital camera representing the device for solid photography possessing embodiment.
Fig. 2 is the block diagram of the schematic configuration of the device for solid photography representing embodiment.
Fig. 3 is the explanatory diagram of the pixel cell from the side perspective embodiment contrary with sensitive surface.
Fig. 4 is cross section and the explanatory diagram transmitting path of signal charge of the pixel cell representing embodiment.
Fig. 5 is cross section and the explanatory diagram transmitting path of signal charge of the pixel cell representing embodiment.
Fig. 6 is cross section and the explanatory diagram transmitting path of signal charge of the pixel cell representing embodiment.
Fig. 7 is the explanatory diagram of the energy barrier under ON/OFF (on/off) state of the transmission transistor representing embodiment.
Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 9 A, Fig. 9 B, Fig. 9 C, Figure 10 A, Figure 10 B, Figure 10 C, Figure 11 A, Figure 11 B are the section view explanatory diagrams of the manufacturing step of the pixel cell representing embodiment.
Figure 12 A and Figure 12 B is the explanatory diagram of the pixel cell of the change case representing embodiment.
Detailed description of the invention
Hereinafter, referring to the drawings, the device for solid photography of embodiment and the manufacture method of device for solid photography are described in detail.It addition, the present invention is not limited by this embodiment institute.
Fig. 1 is the block diagram of the schematic configuration of the digital camera 1 of the device for solid photography 14 representing and possessing embodiment.As it is shown in figure 1, digital camera 1 possesses camera model 11 and back segment process portion 12.
Camera model 11 possesses image pickup optical system 13 and device for solid photography 14.Image pickup optical system 13 captures the light from subject, makes shot object image imaging.Device for solid photography 14 shooting utilizes image pickup optical system 13 and the shot object image of imaging, and the picture signal that will obtain by shooting exports back segment process portion 12.Described camera model 11 in addition to being applied to digital camera 1, the electronic equipment such as mobile terminal being also applied to such as band camera.
Back segment process portion 12 possesses ISP (ImageSignalProcessor, image processor) 15, storage part 16 and display part 17.ISP15 carries out signal processing to the picture signal inputted from device for solid photography 14.Described ISP15 carries out the higher image quality such as such as denoising, defect pixel correcting process, conversion of resolution process and processes.
And, the picture signal after signal processing is exported the following signal processing circuit 21 (with reference to Fig. 2) that the device for solid photography 14 in storage part 16, display part 17 and camera model 11 is possessed by ISP15.The picture signal of camera model 11 is fed back to for the adjustment of device for solid photography 14 or control from ISP15.
The picture signal inputted from ISP15 is stored by storage part 16 with pictorial form.And, the picture signal of stored image, according to the operation etc. of user, is exported display part 17 by storage part 16.Display part 17 shows image according to the picture signal inputted from ISP15 or storage part 16.Described display part 17 for example, liquid crystal display.
Secondly, with reference to Fig. 2, the device for solid photography 14 being possessed camera model 11 illustrates.Fig. 2 is the block diagram of the schematic configuration of the device for solid photography 14 representing embodiment.As in figure 2 it is shown, device for solid photography 14 possesses image sensor 20 and signal processing circuit 21.
Here, it is so-called rear surface irradiation type CMOS (ComplementaryMetalOxideSemiconductor for image sensor 20, complementary metal oxide semiconductors (CMOS)) situation of image sensor illustrates, the side, face that described rear surface irradiation type CMOS is contrary in the face incident with incident illumination of the photo-electric conversion element that incident illumination carries out opto-electronic conversion, is formed with wiring layer.It addition, the image sensor 20 of present embodiment is not limited to rear surface irradiation type CMOS, it is possible to for front illuminated type CMOS.
Image sensor 20 possesses peripheral circuit 22 and the pel array 23 being configured to analog circuit center.And, peripheral circuit 22 possesses vertical transfer register 24, sequencing contro portion 25, CDS (CorrelatedDoubleSampling, correlated double sampling portion) 26, ADC (AnalogtoDigitalConverter, Analog to Digital Converter section) 27 and line storage (linememory) 28.
Pel array 23 is arranged on the camera watch region of image sensor 20.At described pel array 23, along horizontal direction (line direction) and vertical direction (column direction)) it is configured with the multiple photo-electric conversion elements corresponding with each pixel shooting image in two-dimensional array shape (rectangular).
Each photo-electric conversion element for example, utilizes the photodiode that the PN junction of the semiconductor regions of the 1st i.e. p-type of conductivity type and the semiconductor regions of the 2nd i.e. N-type of conductivity type is formed, and produces and store signal charge corresponding with incident light quantity (such as electronics).
In the case of set in each photo-electric conversion element transmission grid applies the voltage specified, the signal charge being stored in photo-electric conversion element is transferred to floating diffusion region through territory, charge transport layers and is kept.
In pel array 23, by the composition near described transmission grid and transmission grid is improved, dark current is inhibited to be flowed into floating diffusion region, while improve from photo-electric conversion element to the transmission characteristic of the signal charge of floating diffusion region.It addition, about the details of the composition near transmission grid and transmission grid, hereafter describe with reference to later being shown in of Fig. 3.
Sequencing contro portion 25 is connected with vertical transfer register 24, CDS26, ADC27 and line storage 28, carries out the sequencing contro of the action of these vertical transfer registers 24, CDS26, ADC27 and line storage 28.
Vertical transfer register 24 is the process portion that signal will be selected to export pel array 23, described selection signal is used to, among multiple photo-electric conversion elements of (matrix) shape two-dimensional arrangements in array, select to want the photo-electric conversion element of read output signal electric charge successively with behavior unit.
Pel array 23, by according to signal charge stored each photo-electric conversion element selecting signal to select with behavior unit inputted from vertical transfer register 24, as the picture element signal of the brightness representing each pixel, exports CDS26 from photo-electric conversion element.
CDS26 is process portion as follows: utilize correlated double sampling, from from the picture element signal that pel array 23 inputs by noise removal, and the picture element signal after denoising is exported ADC27.ADC27 is process portion as follows: the analog pixel signal inputted from CDS26 is converted into digital pixel signal, and is input to line storage 28.Line storage 28 is process portion as follows: temporarily keeps the picture element signal from ADC27 input, for the often row photo-electric conversion element in pel array 23, line by line described picture element signal is exported signal processing circuit 21.
Signal processing circuit 21 is process portion as follows: be configured to digital circuit center, the signal processing specifying the picture element signal inputted from line storage 28, and as picture signal, the picture element signal after signal processing is exported back segment process portion 12.Described signal processing circuit 21, to picture element signal, carries out the signal processing such as the such as correction of lens shade, flaw correction, noise reduction process.
So, in image sensor 20, incident illumination opto-electronic conversion is become the signal charge of amount corresponding with light income and is stored by the multiple photo-electric conversion elements being arranged in pel array 23, the signal charge being stored in each photo-electric conversion element is read by peripheral circuit 22 as picture element signal, thus shoots.
Secondly, with reference to Fig. 3, the composition of the pixel cell of embodiment is illustrated.Fig. 3 is the explanatory diagram of the pixel cell 3 from the side perspective embodiment contrary with sensitive surface.It addition, in figure 3, the pixel cell 3 corresponding with a pixel of shooting image is indicated.
It addition, in figure 3, for the configuration of the element of clear and definite pixel cell 3, there is shown the state following multilayer wired layer and support substrate removed.Hereinafter, the normal direction of the sensitive surface of pixel cell is set to x direction, and both direction orthogonal in the face orthogonal with z direction is set to x direction and y direction and illustrates.
As it is shown on figure 3, pixel cell 3 possesses the territory, element separation area 4 of the side of centrally disposed photo-electric conversion element 30 and encirclement photo-electric conversion element 30.Photo-electric conversion element 30 possesses: the semiconductor regions 31 of p-type, for quadrangular shape, is arranged on the inside of semiconductor layer, and extends to-z direction；And the semiconductor regions 32 of N-type, it is L-shaped during vertical view, and adjacent two sides setting of the semiconductor regions 31 along p-type.
Described photo-electric conversion element 30 is the photodiode utilizing the semiconductor regions 31 of p-type to be formed with the PN junction of the semiconductor regions 32 of N-type, produce signal charge corresponding with incident light quantity (such as electronics), and described signal charge is stored in the semiconductor regions 32 of N-type.Therefore, below, the semiconductor regions 32 of N-type is denoted as charge storage region 32.
And, pixel cell 3 possesses floating diffusion region FD, transmission transistor TRS, reset transistor RST and amplifies transistor AMP.Floating diffusion region FD is the region doped with N-type impurity, is arranged on the shallower position of a face side of semiconductor layer.Such as, floating diffusion region FD is arranged on the position that the ratio charge storage region 32 of semiconductor layer is shallow, it is, than charge storage region 32 in z-axis more by the position of+side.
And, pixel cell 3 is at the depth location equal with floating diffusion region FD of semiconductor layer, the drain electrode RSTD possessing reset transistor RST, the source electrode AMPS amplifying transistor AMP and the drain electrode AMPD of amplification transistor AMP.
The drain electrode AMPD of the drain electrode RSTD of reset transistor RST, the source electrode AMPS amplifying transistor AMP and amplification transistor AMP is the region doped with N-type impurity.
Transmission transistor TRS possesses transmission grid TRG, in the case of transmission grid TRG applies given voltage, transmits signal charge from charge storage region 32 to floating diffusion region FD.
Amplify transistor AMP and possess the amplification grid AMPG being connected with floating diffusion region FD, by making picture element signal corresponding with the current potential of floating diffusion region FD circulate between source electrode AMPS and drain electrode AMPD, signal charge is amplified.This picture element signal is to CDS26 (with reference to Fig. 2) output.
Reset transistor RST possesses replacement grid RSTG, in the case of resetting grid RSTG applying given voltage, transmits signal charge from floating diffusion region FD to drain electrode RSTD, is reset by the current potential of floating diffusion region FD.
Here, the transmission grid TRG of embodiment possesses two grids that are adjacent with floating diffusion region FD respectively and that set, one of them is cylindrical, and extend (following toward the depth direction of semiconductor layer towards charge storage region 32, it is denoted as " the 1st trench-gate TRG1 "), another one is the most cylindrical, and extends (following, to be denoted as " the 2nd trench-gate TRG2 ") towards charge storage region 32 toward the depth direction of semiconductor layer.
And, pixel cell 3, between the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, possesses the passage area 5 of the p-type towards floating diffusion region FD.The passage area 5 of p-type is the semiconductor regions doped with p type impurity.In the case of applying given voltage to the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, the passage area 5 of p-type forms the passage of the path by becoming signal charge.
So, pixel cell 3, in the region of the passage for forming transmission transistor TRS, possesses the passage area 5 of the conductivity type p-type contrary with floating diffusion region FD.Thus, pixel cell 3 can suppress the electric charge independently produced with incident illumination near transmission transistor TRS become dark current and be flowed into floating diffusion region FD.
And, pixel cell 3 possesses the 1st trench-gate TRG1 and the 2nd trench-gate TRG2 of the passage area 5 clipping p-type from both sides.Thus, pixel cell 3 is by applying given voltage to the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, it is possible to make the energy barrier of the passage of transmission transistor TRS be reduced to be enough to transmit signal charge.Therefore, according to pixel cell 3, such as compared with other pixel cells that only one side in the passage area 5 of p-type exists trench-gate, it is possible to increase the transmission characteristic of signal charge.
Secondly, with reference to Fig. 4～Fig. 6, the cross-sectional configuration of the pixel cell 3 of comparison embodiment, the transmission path of the signal charge of transmission transistor TRS is illustrated.Fig. 4～Fig. 6 is cross section and the explanatory diagram transmitting path of signal charge of the pixel cell 3 representing embodiment.In Fig. 4～Fig. 6, for element identical with the element shown in Fig. 3 in the element of pixel cell 3, mark the symbol identical with the symbol shown in Fig. 3.
It addition, in the diagram, there is shown along the cross section of the pixel cell 3 that the A-A' line in Fig. 3 is cut open, in Figure 5, represent the cross section of the pixel cell 3 cut open along the B-B' line in Fig. 3, in figure 6, there is shown along the cross section of the pixel cell 3 that the C-C' line in Fig. 3 is cut open.And, the thick-line arrow shown in Fig. 5 and Fig. 6 represents the flowing of signal charge.
As shown in Figure 4, p-type or the inside of the semiconductor layer 33 of N-type that pixel cell 3 is surrounded by territory, element separation area 4 in side possess photo-electric conversion element 30, and the rear side at semiconductor layer 33 possesses anti-reflective film 61, colored filter 62 and lenticule 63.
Territory, element separation area 4 is DTI (DeepTrenchIsolation, deep trench isolation region), possesses: insulating element 41, be embedded to from the surface of semiconductor layer 33 to the depth direction of semiconductor layer 33 formed groove；And region 42, doped with p type impurity, and it is arranged on side and the bottom surface of insulating element 41.
And, as shown in Figure 4, photo-electric conversion element 30 possesses semiconductor regions 31 and the charge storage region 32 of N-type of that extend, adjacent p-type to the depth direction of semiconductor layer 33.Thus, photo-electric conversion element 30 can not make the area of sensitive surface increase, and by striving for PN junction area on the depth direction of semiconductor layer 33, improves light reception sensitivity with this.
And then, photo-electric conversion element 30 extends to the depth direction of semiconductor layer 33 by making charge storage region 32, it is possible to does not make light-receiving area increase, and makes the saturated electrons number of charge storage region 32 increase.The light opto-electronic conversion incident from the rear side of semiconductor layer 33 is become signal charge by described photo-electric conversion element 30, and described signal charge is stored in charge storage region 32.
Floating diffusion region FD is arranged on the position that the ratio photo-electric conversion element 30 of semiconductor layer 33 is shallow.Amplify grid AMPG and be arranged on the surface of semiconductor layer 33 across gate insulating film 34.
And, as it is shown in figure 5, the source electrode AMPS amplifying transistor AMP is arranged on the position that the ratio photo-electric conversion element 30 of semiconductor layer 33 is shallow.It addition, the drain electrode AMPD (with reference to Fig. 3) amplifying transistor AMP, also in the same manner as source electrode AMPS, is arranged on the position that the ratio photo-electric conversion element 30 of semiconductor layer 33 is shallow.
Transmission grid TRG is so-called pair of groove construction, it is, possess the 1st trench-gate TRG1 and the 2nd trench-gate TRG2 of the upper surface of the charge storage region 32 reaching up to photo-electric conversion element 30 from the surface of semiconductor layer 33.The passage area 5 of p-type is arranged between the 1st trench-gate TRG1 and the 2nd trench-gate TRG2.
And, in present embodiment, in manufacturing step, the 2nd trench-gate TRG2's and towards the side that side is opposition side of the 1st trench-gate TRG1 side, also form the passage area 51 of the p-type doped with p type impurity.It is to say, across the 2nd trench-gate TRG2 with the passage area 5 of p-type to position, also form the passage area 51 of p-type contiguously with the 2nd trench-gate TRG2.
It addition, the passage area 5 of p-type is alternatively following composition: comprise the region clipped by the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, and the position being embedded in semiconductor layer 33 surrounding transmission grid TRG is overall.
In other words, transmission grid TRG is alternatively following composition: the inside of the passage area of the p-type on the top layer being arranged at semiconductor layer 33, embedment has the 1st trench-gate TRG1 and the 2nd trench-gate TRG2.
And, as shown in Figure 6, the drain electrode RSTD of reset transistor RST is arranged on the depth location equal with floating diffusion region FD of semiconductor layer 33.Reset grid RSTG and be arranged on the surface of semiconductor layer 33 across gate insulating film 35.And, as shown in the drawing, the passage area 5 of p-type is arranged on the position that side contacts with floating diffusion region FD.
So, pixel cell 3, between the floating diffusion region FD and charge storage region 32 of N-type, possesses the passage area 5 of the p-type of opposite conductivity type.Thus, not in the case of transmission grid TRG applies voltage, it is, in the case of transmission transistor TRS is OFF (disconnection), pixel cell 3 can suppress the electric charge independently produced with incident illumination become dark current and be flowed into floating diffusion region FD.
And, transmitting in the case of signal charge from charge storage region 32 to floating diffusion region FD, pixel cell 3 applies the voltage specified to transmission grid TRG, and the passage area 5 in p-type forms passage, and making transmission transistor TRS is ON (connection).
Thus, as shown in the thick-line arrow in Fig. 5, signal charge is extracted the passage area 5 of p-type from charge storage region 32, and as shown in the thick-line arrow in Fig. 6, transmits to floating diffusion region FD.
At this moment, the passage area 5 of p-type is to be applied in voltage from both sides by the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, therefore execute alive situation with from one side compared with, the height of energy barrier is more greatly reduced.Thus, such as compared with other pixel cells that only one side in the passage area 5 of p-type exists trench-gate, pixel cell 3 can improve the transmission characteristic of signal charge.
And, as it is shown in figure 5, pixel cell 3 at the 2nd trench-gate TRG2 with to be provided with passage area 5 side of p-type be the side of opposition side, also possess the passage area 51 of the p-type doped with p type impurity.Therefore, pixel cell 3 is by applying electric charge to transmission grid TRG, it is possible to the passage area 51 in p-type also forms passage.
Thus, pixel cell 3 is passed through this passage at two of passage area 5,51 of p-type, transmits signal charge from charge storage region 32 to floating diffusion region FD, it is possible to improve further the transmission characteristic of signal charge.
Secondly, with reference to Fig. 7, the energy barrier of the transmission transistor TRS of embodiment is illustrated.Fig. 7 is the explanatory diagram of the energy barrier under the ON/OFF state of the transmission transistor TRS representing embodiment.
As it is shown in fig. 7, at transmission transistor TRS for not in the case of transmission grid TRG executes alive OFF state, as shown in 2 chain lines in this figure, the energy barrier of the passage area 5 of p-type is the highest.Thus, signal charge is stored in charge storage region 32.
Here, such as in the case of trench-gate is one, if applying voltage (making single-groove groove is ON) to trench-gate, then as shown in the one-dot chain line in this figure, it is impossible to make the energy barrier of the passage area 5 of p-type reduce fully.In this case, there is signal charge not to be transmitted and the situation that remains in charge storage region 32.And, the signal charge remaining in charge storage region 32 becomes the reason producing image retention on shooting image.
On the other hand, the transmission transistor TRS of embodiment applies voltage (making double groove is ON) to the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, therefore shown in solid as in this figure, it is possible to reduce the energy barrier of the passage area 5 of p-type fully.Therefore, pixel cell 3 can prevent from producing image retention on shooting image with this by preventing from occurring the residual of signal charge in charge storage region 32.
Secondly, with reference to Fig. 8 A～Figure 11 B, the manufacture method of the pixel cell 3 of embodiment is illustrated.Fig. 8 A～Figure 11 B is the section view explanatory diagram of the manufacturing step of the pixel cell 3 representing embodiment.It addition, here, the manufacturing step of part shown in Fig. 5 of pixel cell 3 is described in detail, part shown in Fig. 4 and Fig. 6 is illustrated simply.
When manufacturing pixel cell 3, first, as shown in Figure 8 A, such as, on the semiconductor substrates such as silicon wafer 100, make the silicon layer epitaxial growth of p-type or N-type, be consequently formed semiconductor layer 33.
Then, to semiconductor layer 33, the p type impurity such as ion implanting such as boron, and then, to semiconductor layer 33, the N-type impurity such as ion implanting such as phosphorus.Then, by making annealing treatment, make semiconductor regions 31 (with reference to Fig. 4) activation of the charge storage region 32 of N-type within semiconductor layer 33, p-type, and form photo-electric conversion element 30.
Then, to N-type impurity such as shallower position, such as shallow than photo-electric conversion element 30 position of a face side of semiconductor layer 33, ion implanting phosphorus, and make annealing treatment, be consequently formed the source electrode AMPS amplifying transistor AMP.
At this moment, similarly, amplifying the drain electrode AMPD of transistor AMP, the drain electrode RSTD of reset transistor RST and the forming position of floating diffusion region FD, also the N-type impurity such as ion implanting such as phosphorus, and making annealing treatment.
Thus, and amplify the source electrode AMPS of transistor AMP simultaneously, form the drain electrode RSTD and floating diffusion region FD (reference Fig. 3) amplifying the drain electrode AMPD of transistor AMP, reset transistor RST.
Then, as shown in Figure 8 B, form resist film 71 on the surface of semiconductor layer 33, and resist film 71 is patterned, thus make the surface of the forming position in the territory, element separation area 4 (with reference to Fig. 3) in semiconductor layer 33 expose.
Then, resist film 71 is used as mask, carry out such as RIE (ReactiveIonEtching, reactive ion etching), the most as shown in Figure 8 C, form the groove 72 for DTI extended from the face side rearwardly side of semiconductor layer 33.
Then, towards the inner peripheral surface of groove 72, from p type impurities such as incline direction ion implanting such as boron.At this moment, changing the direction of illumination of ion, repeatedly carrying out ion implanting while being divided into.Thereby, it is possible to the whole inner peripheral surface of groove 72, carry out the ion implanting of boron.
Then, by making annealing treatment, as shown in Figure 9 A, medial surface and bottom surface at groove 72 form the region 42 doped with p type impurity.Then, as shown in Figure 9 B, after resist film 71 is peeled off, utilize the insulating elements 41 such as such as CVD (ChemicalVaporDeposition, chemical vapour deposition technique), embedment silicon oxide, be consequently formed territory, element separation area 4.
Then, as shown in Figure 9 C, resist film 73 is formed on the surface of semiconductor layer 33.Then, by being patterned by resist film 73, make the surface of the forming position of the 1st trench-gate TRG1 and the 2nd trench-gate TRG2 (with reference to Fig. 3) of semiconductor layer 33 expose.At this moment, in the way of making the surface of the semiconductor layer 33 of exposed portion become circular shape, resist film 73 is patterned.
Then, resist film 73 is used as mask, carry out such as RIE.Thus, as shown in Figure 10 A, the groove 74 for the 1st trench-gate TRG1 extended from surface lateral photo-electric conversion element 30 side of semiconductor layer 33 and the groove 75 for the 2nd trench-gate TRG2 are formed.
Then, towards the region clipped by two grooves 74,75, from incline direction, change the direction of illumination of ion, while being divided into repeatedly the p type impurities such as ion implanting such as boron.At this moment, for the groove 75 not contacted with territory, element separation area 4 in two grooves 74,75, to the side that region the is opposition side also boron ion implantation clipped by two grooves 74,75.
Then, by making annealing treatment, as shown in Figure 10 B, between in generally cylindrical two grooves 74,75, the passage area 5 of p-type is formed.At this moment, the groove 75 not contacted with territory, element separation area 4 with and the passage area 5 of p-type contact the side that side is opposition side, also form the passage area 51 of the p-type doped with p type impurity.
Then, after resist film 73 is peeled off, on the surface of semiconductor layer 33, utilize the electroconductive components such as such as CVD, lamination polysilicon, and the electroconductive component of unnecessary part is removed.Thus, as illustrated in figure 10 c, formation possesses the transmission grid TRG of the 1st trench-gate TRG1 and the 2nd trench-gate TRG2.Meanwhile, form replacement grid RSTG and amplify grid AMPG (with reference to Fig. 3).
Then, as shown in Figure 11 A, form multilayer wired layer 8 on the surface of semiconductor layer 33, and the support substrates 101 such as such as silicon wafer are fitted in the surface of multilayer wired layer 8.Multilayer wired layer 8 is to be formed by repeating series of steps, described step for example, forms the interlayer dielectrics 81 such as silicon oxide, distribution is used on interlayer dielectric 81 channel patterns on the surface of semiconductor layer 33, and in groove, imbed the metals such as copper, thus form multilayer wired 82.
Then, when support support substrate 101, from rear side, semiconductor substrate 100 is carried out grinding and grinding, thus make the back side of semiconductor layer 33 expose.Then, as shown in Figure 11 B, at the back side of the semiconductor layer 33 exposed, after utilizing such as silicon nitride formation anti-reflective film 61, at the back side of anti-reflective film 61, sequentially form colored filter 62 and lenticule 63, thus complete pixel cell 3.
As it has been described above, the device for solid photography of embodiment possesses semiconductor layer, the photo-electric conversion element being arranged on semiconductor layer and is arranged on the floating diffusion region of shallower position of a face side of semiconductor layer.And, device for solid photography is on the side of floating diffusion region, possess the multiple trench-gates extended toward the depth direction of semiconductor layer towards photo-electric conversion element from the surface of semiconductor layer, and between trench-gate, possess the semiconductor regions that conductivity type is contrary with floating diffusion region.
In described device for solid photography, not in the case of trench-gate applies voltage, the conductivity type of the semiconductor regions being arranged between trench-gate is contrary with floating diffusion region, therefore becomes the barrier attempting the dark current to floating diffusion region inflow.
Therefore, according to the device for solid photography of embodiment, not in the case of trench-gate applies voltage, it is possible to the electric charge that suppression and incident illumination independently produce is flowed into floating diffusion region.
And, in device for solid photography, by applying voltage to multiple trench-gates, it is possible to the semiconductor regions between two lateral trench-gates applies voltage.Therefore, device for solid photography be enough to transmit signal charge from photo-electric conversion element to floating diffusion region by making the energy barrier of the semiconductor regions between trench-gate be reduced to, it is possible to increase the transmission characteristic of signal charge.
And, the semiconductor regions being arranged between the trench-gate of embodiment contacts with floating diffusion region.Thus, according to device for solid photography, by applying voltage to trench-gate, it is possible to passage is formed to the position being extremely close to floating diffusion region such that it is able to improve the transmission characteristic of signal charge further.
And, the trench-gate of embodiment is generally a cylindrical shape.Therefore, the forming position of the trench-gate that the mask used when making trench-gate is such as usable in semiconductor layer is patterned with the resist film in the hole of simple circular shape, it is not necessary to resist film imposes the patterning of complexity.
It addition, in said embodiment, it is that generally cylindrical situation is illustrated to the 1st trench-gate TRG1 and the 2nd trench-gate TRG2, but the shape of the 1st trench-gate TRG1 and the 2nd trench-gate TRG2 is not limited to this.
Hereinafter, with reference to Figure 12 A and Figure 12 B, the change case of embodiment is illustrated.Figure 12 A and Figure 12 B is the explanatory diagram of the pixel cell of the change case representing embodiment.In fig. 12, part near the transmission grid TRG3 of the pixel cell optionally representing change case 1.And, in Figure 12 B, there is shown the pixel cell 3a of change case 2.
Additionally, the pixel cell of change case 1 is in addition to the 1st trench-gate TRG4, the 2nd trench-gate TRG5 and the point different from transmission grid TRG shown in Fig. 3 doped with the shape of the passage area 52 of the p-type of p type impurity, other compositions identical with the pixel cell 3 shown in Fig. 3.
As illustrated in fig. 12, the transmission grid TRG3 of the pixel cell of change case 1 possesses adjacent with floating diffusion region FD and that set the 1st trench-gate TRG4 and the 2nd trench-gate TRG5 of tabular.
And, the pixel cell of change case 1, between the 1st trench-gate TRG4 and the 2nd trench-gate TRG5, possesses the passage area 52 of the p-type towards floating diffusion region FD.
1st trench-gate TRG4 and the 2nd trench-gate TRG5 all extends from the surface of semiconductor layer 33 to floating diffusion region FD, and interarea is opposite to one another.It addition, the most so-called interarea refers to the side that in the side of the 1st trench-gate TRG4 and the 2nd trench-gate TRG5, area is maximum.Here, in the side of the 1st trench-gate TRG4 and the 2nd trench-gate TRG5, face towards the passage area 52 of p-type is interarea.
Pixel cell according to change case 1, it is possible to expand the passage area 52 of p-type, therefore in the case of transmission transistor is OFF, it is possible to suppression dark current is flowed into floating diffusion region FD further.
And, according to the pixel cell of change case 1, in the case of the 1st trench-gate TRG4 and the 2nd trench-gate TRG5 applies voltage, the passage area 52 of the p-type expanded becomes passage, therefore, it is possible to improve the transmission characteristic of signal charge further.
Although it addition, be before this enumerate a floating diffusion region FD be set relative to a photo-electric conversion element 30 in case of, but the pixel cell of embodiment is alternatively multiple photo-electric conversion element 30 and has the composition of a floating diffusion region FD.
Such as, it is possible to as the pixel cell 3a of the change case 2 shown in Figure 12 B, it is four photo-electric conversion elements 30 compositions of having a floating diffusion region FD.It addition, each photo-electric conversion element 30 shown in Figure 12 B is the composition identical with the photo-electric conversion element 30 shown in Fig. 3.
In the case of being set as described composition, such as, as shown in Figure 12 B, in pixel cell 3a, four photo-electric conversion elements 30 are set in two row two row.Each photo-electric conversion element 30 is corner central authorities' configuration towards pixel cell 3a of the L word of the charge storage region 32 of L-shaped when being to make vertical view.It is to utilize territory, element separation area 4 electrically carrying out element separation between each photo-electric conversion element 30.
And, in central authorities and the shallower position of a face side of semiconductor layer, such as shallow than photo-electric conversion element 30 position of pixel cell 3a, floating diffusion region FD is set.And then, transmission grid TRG6, described transmission grid TRG6 are set and possess the 1st trench-gate TRG4 and the 2nd trench-gate TRG5 extended towards the corner of the L word of each charge storage region 32 from the surface of semiconductor layer.
And, between each 1st trench-gate TRG4 and the 2nd trench-gate TRG5, the passage area 52 of p-type is set.1st trench-gate TRG4, the 2nd trench-gate TRG5, the passage area 52 of p-type are the shape identical with parts shown in Figure 12 A.
Thus, in the pixel cell 3a of so-called four pixel one unit, it is also possible to suppression dark current is flowed into floating diffusion region FD, while improving from four each photo-electric conversion elements 30 to the transmission characteristic of the signal charge of floating diffusion region FD.
It addition, in the pixel cell 3a shown in Figure 12 B, the 1st trench-gate TRG4 and situation that the 2nd trench-gate TRG5 is tabular are illustrated, but the 1st trench-gate TRG4 and the 2nd trench-gate TRG5 is alternatively generally a cylindrical shape (with reference to Fig. 3).
It addition, in described embodiment and change case, enumerate in case of transmission grid possesses two trench-gates and be illustrated, but the transmission grid of embodiment alternatively possesses the composition of more than three trench-gates.
In this case, more than three trench-gate respective between, arranging the semiconductor regions of p-type doped with p type impurity, the semiconductor regions of the p-type between groove is all towards floating diffusion region or the position that is in contact with it, and configuration is the trench-gate of string when overlooking.
And, in said embodiment, the situation of the passage area that pixel cell possesses the conductivity type p-type contrary with floating diffusion region between a plurality of trench-gate is illustrated, but the conductivity type of passage area also can be identical with floating diffusion region.
Such as, there is the interface state between trench-gate and semiconductor layer good, the situation almost without crystal defect or the design according to the voltage applied to trench-gate on interface and without considering the situation of dark current.In this case, pixel cell is alternatively the semiconductor regions composition as passage area possessing N-type between a plurality of trench-gate.It addition, in the case of the conductivity type of semiconductor layer is N-type, the impurity concentration of the N-type of passage area is higher than the impurity concentration of the N-type of semiconductor layer.
Thus, pixel cell makes to improve from photo-electric conversion element to the transmission characteristic (easiness of transmission) of the signal charge of floating diffusion region.And, in pixel cell, in the case of making transmission transistor be ON, utilize two trench-gates, apply voltage from two lateral passage area, therefore the transmittability of the signal charge of transmission transistor increases.
That is, even if the device for solid photography passage area of embodiment 5,51,52 becomes N-type, the ability with reference to the potentialswing (current potential swing) brought by doublegate (bigrid) change illustrated by Fig. 7 that also can produce improves effect.
Therefore, according to described pixel cell, in the case of making transmission transistor be ON, it is possible to suppression signal charge remains in photo-electric conversion element, therefore, it is possible to suppression produces image retention on shooting image.
Some embodiments of the present invention are illustrated, but these embodiments are to propose as an example, be not intended to limit the scope of invention.The embodiment of these novelties can be implemented by other various modes, and can carry out various omission within a range not departing from the gist of the invention, replace, change.These embodiments and change thereof are included in scope or the purport of invention, and are included in the scope of the invention described in claims and equalization thereof.
Claims (20)
1. a device for solid photography, it is characterised in that possess:
Semiconductor layer；
Photo-electric conversion element, is arranged on described semiconductor layer；
Floating diffusion region；It is arranged on the shallower position of a face side of described semiconductor layer；
Multiple grids, adjacent with described floating diffusion region respectively and set, and extend towards described photo-electric conversion element toward the depth direction of described semiconductor layer；And
Semiconductor regions, is arranged between described grid towards described floating diffusion region.
Device for solid photography the most according to claim 1, it is characterised in that
Described semiconductor regions is:
Conductivity type is contrary with described floating diffusion region.
Device for solid photography the most according to claim 1, it is characterised in that
Described semiconductor regions is:
Conductivity type is identical with described floating diffusion region.
Device for solid photography the most according to claim 1, it is characterised in that
The plurality of grid is
Generally a cylindrical shape.
Device for solid photography the most according to claim 1, it is characterised in that
The plurality of grid is tabular, and
Interarea is opposite to one another.
Device for solid photography the most according to claim 1, it is characterised in that
Described photo-electric conversion element possesses:
Conductivity type is the region of p-type, for quadrangular shape, and is arranged on the inside of described semiconductor layer；And
Conductivity type is the region of N-type, is L-shaped during vertical view, and along adjacent two sides setting in the region that described conductivity type is p-type.
Device for solid photography the most according to claim 6, it is characterised in that
Described floating diffusion region is:
It is arranged on the region that described conductivity type is N-type.
Device for solid photography the most according to claim 6, it is characterised in that
Described grid is:
The upper surface in the region that described conductivity type is N-type is reached up to from the surface of described semiconductor layer.
Device for solid photography the most according to claim 1, it is characterised in that be also equipped with semiconductor regions,
This semiconductor regions be arranged on across described grid and described semiconductor regions to position.
Device for solid photography the most according to claim 1, it is characterised in that
Described grid is:
It is embedded to be arranged at the inside of the described semiconductor regions on the top layer of described semiconductor layer.
11. device for solid photography according to claim 1, it is characterised in that
Described semiconductor regions is arranged on the position that side contacts with described floating diffusion region.
12. device for solid photography according to claim 6, it is characterised in that
Described photo-electric conversion element is:
In pixel cell, two row two row are provided with four, and are to make to be that the corner of the L word in L-shaped and region that conductivity type is N-type is towards central authorities' configuration of described pixel cell during described vertical view respectively；
Described floating diffusion region is:
The position that photo-electric conversion element described in the ratio of the central and described semiconductor layer being arranged on described pixel cell is shallow；And
Described grid is:
Extend from the surface of described semiconductor layer towards the corner of the L word in the region that each described conductivity type is N-type.
The manufacture method of 13. 1 kinds of device for solid photography, it is characterised in that comprise the steps:
Photo-electric conversion element is formed at semiconductor layer；
Formation floating diffusion region, shallower position in a face side of described semiconductor layer；
On the side of described floating diffusion region, form multiple grooves that the depth direction towards described photo-electric conversion element toward described semiconductor layer extends；
Semiconductor regions is formed between the plurality of groove；And
In described groove, imbed electroconductive component and form grid.
The manufacture method of 14. device for solid photography according to claim 13, it is characterised in that
Form described semiconductor regions to include:
Form the described semiconductor regions that conductivity type is contrary with described floating diffusion region.
The manufacture method of 15. device for solid photography according to claim 13, it is characterised in that
Form described groove to include:
Form columnar described groove.
The manufacture method of 16. device for solid photography according to claim 13, it is characterised in that
Form described semiconductor regions to include:
Towards the region clipped by the plurality of groove, from incline direction, change the direction of illumination of impurity, while carrying out the injection of impurity.
The manufacture method of 17. device for solid photography according to claim 16, it is characterised in that
Form described semiconductor regions to include:
Described impurity is injected to the two sides of described groove.
The manufacture method of 18. device for solid photography according to claim 13, it is characterised in that
Form described photo-electric conversion element to include:
The region that the conductivity type being internally formed quadrangular shape is p-type at described semiconductor layer；And
Along adjacent two sides in the region that described conductivity type is p-type, formed and be L-shaped when overlooking and conductivity type is the region of N-type.
The manufacture method of 19. device for solid photography according to claim 18, it is characterised in that
Form described floating diffusion region to include:
The region that described conductivity type is N-type forms described floating diffusion region.
The manufacture method of 20. device for solid photography according to claim 18, it is characterised in that
Form described groove to include:
Form the described groove of the upper surface reaching up to the region that described conductivity type is N-type from the surface of described semiconductor layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015011336A JP2016136584A (en) | 2015-01-23 | 2015-01-23 | Solid-state imaging device, and method of manufacturing the same |
| JP2015-011336 | 2015-01-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105826336A true CN105826336A (en) | 2016-08-03 |
Family
ID=56434211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610028492.4A Pending CN105826336A (en) | 2015-01-23 | 2016-01-15 | Solid-state image pickup device and method for manufacturing a solid-state image pickup device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20160218138A1 (en) |
| JP (1) | JP2016136584A (en) |
| KR (1) | KR20160091244A (en) |
| CN (1) | CN105826336A (en) |
| TW (1) | TW201630173A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110476252A (en) * | 2017-03-28 | 2019-11-19 | 株式会社尼康 | Photographing element and photographic device |
| CN112534579A (en) * | 2018-07-31 | 2021-03-19 | 索尼半导体解决方案公司 | Imaging device and electronic apparatus |
| US11552119B2 (en) | 2017-11-09 | 2023-01-10 | Sony Semiconductor Solutions Corporation | Solid-state imaging device and electronic equipment |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015053411A (en) * | 2013-09-09 | 2015-03-19 | ソニー株式会社 | Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic equipment |
| KR102546550B1 (en) * | 2016-06-24 | 2023-06-23 | 에스케이하이닉스 주식회사 | Image Sensor Having Transfer Gates in Deep Trenches |
| JP2018026444A (en) * | 2016-08-10 | 2018-02-15 | ソニー株式会社 | Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method |
| KR20180080931A (en) | 2017-01-05 | 2018-07-13 | 삼성전자주식회사 | Image sensor |
| JP2018190797A (en) | 2017-04-28 | 2018-11-29 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging element and electronic apparatus |
| JP6650909B2 (en) * | 2017-06-20 | 2020-02-19 | キヤノン株式会社 | Imaging device, imaging system, moving object, and method of manufacturing imaging device |
| DE102018122628B4 (en) | 2017-09-29 | 2023-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS image sensor with jagged photodiode structure |
| US10790321B2 (en) * | 2017-09-29 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS image sensor having indented photodiode structure |
| CN111279482A (en) | 2017-11-09 | 2020-06-12 | 索尼半导体解决方案公司 | Solid-state image pickup device and electronic apparatus |
| EP3709358B1 (en) | 2017-11-09 | 2024-02-21 | Sony Semiconductor Solutions Corporation | Solid-state image pickup device and electronic apparatus |
| KR102549400B1 (en) * | 2018-03-21 | 2023-06-30 | 에스케이하이닉스 주식회사 | Image Sensor Having PD Bias Patterns |
| JP2020035916A (en) * | 2018-08-30 | 2020-03-05 | ソニーセミコンダクタソリューションズ株式会社 | Imaging apparatus and electronic equipment |
| US10861892B2 (en) * | 2018-11-21 | 2020-12-08 | Bae Systems Information And Electronic Systems Integration Inc. | Low-light-level CMOS image sensor pixel |
| JP7403993B2 (en) * | 2019-08-20 | 2023-12-25 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging device and its manufacturing method, and electronic equipment |
| WO2021131844A1 (en) * | 2019-12-25 | 2021-07-01 | ソニーセミコンダクタソリューションズ株式会社 | Light-receiving element and light-receiving device |
| JP2021141262A (en) * | 2020-03-06 | 2021-09-16 | Ｇｐｉｘｅｌ Ｊａｐａｎ株式会社 | Pixel for solid-state imaging device |
| US11616088B2 (en) * | 2020-03-25 | 2023-03-28 | Omnivision Technologies, Inc. | Transistors having increased effective channel width |
| US11521997B2 (en) * | 2020-04-16 | 2022-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-protrusion transfer gate structure |
| WO2021241243A1 (en) * | 2020-05-29 | 2021-12-02 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging device and photodetection method |
| JP2021193696A (en) | 2020-06-07 | 2021-12-23 | ソニーセミコンダクタソリューションズ株式会社 | Sensor device |
| US11574947B2 (en) * | 2020-08-18 | 2023-02-07 | Omnivision Technologies, Inc. | Method and image sensor with vertical transfer gate and buried backside-illuminated photodiodes |
| CN117203769A (en) * | 2021-06-11 | 2023-12-08 | 索尼半导体解决方案公司 | Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus |
| KR20240038972A (en) * | 2021-08-13 | 2024-03-26 | 소니 세미컨덕터 솔루션즈 가부시키가이샤 | Imaging devices and electronic devices |
| JP2023157511A (en) * | 2022-04-15 | 2023-10-26 | ソニーセミコンダクタソリューションズ株式会社 | Optical detector and electronic apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221966A (en) * | 2006-12-29 | 2008-07-16 | 东部高科股份有限公司 | CMOS image sensor and method for manufacturing the same |
| CN101826536A (en) * | 2009-03-04 | 2010-09-08 | 索尼公司 | Solid state image pickup device and manufacture method thereof and camera head |
| US20100308385A1 (en) * | 2009-06-03 | 2010-12-09 | Sony Corporation | Semiconductor device and a method of manufacturing the same, and solid-state image pickup element |
| CN102693989A (en) * | 2011-03-23 | 2012-09-26 | 索尼公司 | Solid state imaging device, method of producing solid state imaging device, and electronic apparatus |
-
2015
- 2015-01-23 JP JP2015011336A patent/JP2016136584A/en active Pending
- 2015-12-29 TW TW104144307A patent/TW201630173A/en unknown
- 2015-12-29 US US14/982,553 patent/US20160218138A1/en not_active Abandoned
- 2015-12-30 KR KR1020150189327A patent/KR20160091244A/en not_active Application Discontinuation
-
2016
- 2016-01-15 CN CN201610028492.4A patent/CN105826336A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221966A (en) * | 2006-12-29 | 2008-07-16 | 东部高科股份有限公司 | CMOS image sensor and method for manufacturing the same |
| CN101826536A (en) * | 2009-03-04 | 2010-09-08 | 索尼公司 | Solid state image pickup device and manufacture method thereof and camera head |
| US20100308385A1 (en) * | 2009-06-03 | 2010-12-09 | Sony Corporation | Semiconductor device and a method of manufacturing the same, and solid-state image pickup element |
| CN102693989A (en) * | 2011-03-23 | 2012-09-26 | 索尼公司 | Solid state imaging device, method of producing solid state imaging device, and electronic apparatus |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110476252A (en) * | 2017-03-28 | 2019-11-19 | 株式会社尼康 | Photographing element and photographic device |
| US11552119B2 (en) | 2017-11-09 | 2023-01-10 | Sony Semiconductor Solutions Corporation | Solid-state imaging device and electronic equipment |
| CN112534579A (en) * | 2018-07-31 | 2021-03-19 | 索尼半导体解决方案公司 | Imaging device and electronic apparatus |
| US11923387B2 (en) | 2018-07-31 | 2024-03-05 | Sony Semiconductor Solutions Corporation | Imaging device and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201630173A (en) | 2016-08-16 |
| JP2016136584A (en) | 2016-07-28 |
| US20160218138A1 (en) | 2016-07-28 |
| KR20160091244A (en) | 2016-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105826336A (en) | Solid-state image pickup device and method for manufacturing a solid-state image pickup device | |
| US11729530B2 (en) | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus | |
| US9659987B2 (en) | Approach for reducing pixel pitch using vertical transfer gates and implant isolation regions | |
| US8053272B2 (en) | Semiconductor device fabrication method | |
| CN103117289A (en) | Solid-state imaging element, manufacturing method, and electronic device | |
| TWI536553B (en) | Solid-state imaging device and method for manufacturing solid-state imaging device | |
| JP2016139660A (en) | Solid-state image pickup device | |
| US7776638B2 (en) | Two epitaxial layers to reduce crosstalk in an image sensor | |
| JP2015220255A (en) | Backside irradiation type cmos imaging device, and method for manufacturing thereof | |
| KR100741877B1 (en) | CMOS Image Sensor and Method for Manufacturing the Same | |
| KR101543098B1 (en) | Solid-state image pickup device and method of fabricating the same | |
| KR101583904B1 (en) | Solid-state imaging device, method for manufacturing solid-state imaging device, and camera module | |
| JP2017054932A (en) | Solid state imaging apparatus and method of manufacturing image state imaging apparatus | |
| JP4779781B2 (en) | Solid-state imaging device and manufacturing method thereof | |
| JP6682674B2 (en) | Solid-state imaging device and method of manufacturing solid-state imaging device | |
| JP2019114797A (en) | Solid state image sensor and manufacturing method of the same | |
| JP2017045879A (en) | Solid state image sensor and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160803 |
|
| WD01 | Invention patent application deemed withdrawn after publication |