CN105811887A

CN105811887A - Linearization mixer

Info

Publication number: CN105811887A
Application number: CN201610247220.3A
Authority: CN
Inventors: 蔡秋富; 章国豪; 李嘉进; 陈锦涛; 林俊明
Original assignee: Foshan Zhenzhiweixin Technology Co Ltd
Current assignee: Foshan Zhenzhiweixin Technology Co Ltd
Priority date: 2016-04-20
Filing date: 2016-04-20
Publication date: 2016-07-27
Anticipated expiration: 2036-04-20
Also published as: CN105811887B

Abstract

The invention belongs to the technical field of mixers, and particularly relates to a linearization mixer. The linearization mixer comprises a field-effect transistor mixer; and is characterized in that a local oscillation signal of the field-effect transistor mixer is generated by a driving stage, the driving stage comprises a local oscillation signal output end, and the local oscillation signal output end is in a high impedance state. The linearization mixer has the beneficial effect that stability of Vgs level is controlled well by means of existence of a grid-source parasitic capacitor (Cgs), thus, Ron is constant, the degree of linearity of the mixer is improved effectively, and signals subjected to mixing become more accurate.

Description

Linearisation frequency mixer

Technical field

The invention belongs to frequency mixer technical field, particularly relate to a kind of linearisation frequency mixer.

Background technology

In a wireless communication system, frequency mixer is requisite equipment.In radio-frequency receiving-transmitting chain, relate to frequency to be transferred to high band by low-frequency range, and frequency is transferred to low-frequency range by high band.And the intermediate-freuqncy signal that obtains is undistorted after requiring conversion, this just harsh requirement to the linearity proposition of frequency mixer.In traditional receivers, transducer is generally made up of the frequency mixer with Metal-Oxide Semiconductor field-effect transistor (MOSFET), the rf signal drain-source end by MOSFET, and the grid of MOSFET is driven by local oscillator signals.During local oscillation signal makes MOSFET open, rf signal is passed through, and the grid voltage of MOSFET is typically remained stable by local oscillation signal, voltage radio frequency (RF) signal intensity of the Lead-through terminal of MOSFET and change.Therefore, during transistor is opened, its gate source voltage V_gsThe change of radio frequency (RF) signal and change.And then, transistor conduct resistance R during this period_onAlso change with the change of RF signal.Therefore, when carrying out down coversion, the R of change_onThe non-linear of signal by this MOSFET can be increased.Therefore, the linearity of the frequency mixer improving frequency mixer becomes extremely necessary.

Summary of the invention

The present invention solves the problems referred to above, it is provided that a kind of linearisation frequency mixer.

Technical scheme is as follows: linearisation frequency mixer, and including field effect transistor frequency mixer, the local oscillation signal of described field effect transistor frequency mixer is produced by driving stage, and described driving stage includes that local oscillation signal outfan, local oscillation signal outfan are high-impedance state.

High impedance status input can improve the linearity of field effect transistor frequency mixer.Owing to field effect transistor frequency mixer has a parasitic gate-source capacitance (C_gs), cause the grid of field effect transistor frequency mixer and source class to be mutually coupled.Electric capacity is equivalent to open circuit under direct current signal, and is equivalent to short circuit under AC signal.When the grid of field effect transistor frequency mixer is driven to high-impedance state, due to gate-source parasitic capacitance (C_gs ₎Existence, be input to the change of AC signal that the local oscillation signal on field effect transistor frequency mixer can follow the trail of the source class input of field effect transistor frequency mixer.Therefore, during high-impedance state, the gate source voltage (V of field effect transistor frequency mixer_gs) will keep being approximately equal to set V_gsLevel is changed into high impedance status as LO_OUT_C from high level state.Due to high impedance status period V_gsGenerally remain constant, when input signal is by field effect transistor frequency mixer, the R of field effect transistor frequency mixer_onAlso generally remain constant.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of specific embodiment.

Fig. 2 is the circuit theory diagrams of specific embodiment.

Fig. 3 is the sequential chart of each end points and node.

Detailed description of the invention

Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is further described.

The 100(of linearisation frequency mixer shown in Fig. 1 is such as: upconverter or low-converter) structured flowchart.This linearisation frequency mixer 100 comprises driving stage 110 and field effect transistor frequency mixer 120.Field effect transistor frequency mixer 120 can be that bilateral device can realize up-conversion and down coversion, the schematic diagram of instance transfer device shown in Fig. 2 200.Frequency mixer 220 is made up of the 4th NMOS tube 250 and a PMOS350.4th NMOS tube 250 and PMOS350 is parallel to each other and the source class of each of which and drain are connected together.Both source class are coupled to the input IN of frequency mixer 220, and both drain are coupled to the output OUT of frequency mixer 220.

Driving stage includes local oscillation signal input LO, local oscillation signal outfan LO_OUT, the first phase inverter the 230, first PMOS the 231, second PMOS 232 and the first NMOS tube 233, the input of the first phase inverter 230 and the grid of the second PMOS 232 and the first NMOS tube 233 grid be coupled to local oscillation signal input LO, the grid of the first PMOS 231 is coupled in the output of the first phase inverter 230.The source class of the first PMOS 231 is coupled to power vd D, and the drain of the first PMOS 231 is coupled to the source of the second PMOS 232.The source ground connection of the first NMOS tube 233, the drain of the first NMOS tube 233 is coupled to the drain terminal of the second PMOS 232.The drain terminal that second PMOS 232 and the first NMOS tube 233 connect altogether is connected to local oscillation signal outfan LO_OUT.

The complementary end of driving stage includes complementary local oscillation signal outfan LO_OUT_C, second phase inverter the 205, the 3rd phase inverter the 330, the 3rd PMOS the 333, second NMOS tube the 332, the 3rd NMOS tube 331, the input of the second phase inverter 205 connects local oscillation signal input LO, the grid of outfan connection the 3rd PMOS 333 of the second phase inverter 205 and the grid of the second NMOS tube 332 and the input of the 3rd phase inverter 330.The source ground connection of grid the 3rd NMOS tube 331 of output termination the 3rd NMOS tube 331 of the 3rd phase inverter 330, the drain of the 3rd NMOS tube 331 is coupled to the source class of the second NMOS tube 332, the source of the 3rd PMOS 333 meets power vd D, the drain of the 3rd PMOS 333 couples the drain of the second NMOS tube 332, and the drain that the 3rd PMOS 333 and the second NMOS tube 332 connect altogether connects complementary local oscillation signal outfan LO_OUT_C.

Described frequency mixer includes the 4th PMOS 350 and the 4th NMOS tube 250, and the grid of the 4th NMOS tube 250 connects local oscillation signal outfan LO_OUT, and the grid of the 4th NMOS tube 250 connects complementary local oscillation signal outfan LO_OUT_C.

In the present embodiment, phase inverter can include any circuit, system, equipment or device, can be a digital signal inversion of input and in outfan output.Phase inverter receives a low-voltage (such as: logical zero) from input, and it obtains a high voltage (such as: logic 1) at outfan.On the contrary, if phase inverter obtains a high voltage at input, it can obtain a low-voltage at outfan.Phase inverter can be PMOS phase inverter, NMOS phase inverter, static CMOS inverter, saturated carry digital phase inverter or other suitable implementation.Phase inverter 230 is internal comprises one or more gates, such as non-conjunction or " nor gate " or other the gate being suitable for or combinational logic gate.Therefore, phase inverter 230 has propagation delay, i.e. the output of phase inverter to spend a bit of time to respond the change of input.

During the work of linearisation frequency mixer: LO signal is high level (such as: logic 1) when first phase, and the first NMOS tube 233 turns on, and the second PMOS 232 turns off, therefore drive LO_OUT to be low level and the 4th NMOS tube 250 turns off in first phase.Now, node 211(NODE211) due to the first phase inverter 230 it is low level (logical zero) and the first PMOS 231 turns on.When LO signal from first phase to second phase saltus step from high to low, the first NMOS tube 233 is from ON transitions for turning off, and the second PMOS 232 transfers conducting to from shutoff.As Fig. 3 shows, node 211 continues to keep the low level of a bit of time t1 to t2 due to the propagation delay of phase inverter 230, and the first PMOS 231 is held on.Therefore, LO_OUT is driven into high level and the 4th NMOS tube 250 is driven to conducting in the first paragraph time due to the propagation delay of phase inverter 230.After the propagation delay of phase inverter 230, node 211 is changed into high level in the t2 moment from low level, and the first PMOS 231 is transferred to shutoff by from conducting.At this moment, the first PMOS 231 and the first NMOS tube 233 simultaneously turn off.Owing to being not turned on path between power vd D and LO_OUT, also being not turned on path between LO_OUT and ground GND, LO_OUT is forced into high impedance status, thus within t1 to t2 time second segment time, i.e. in second phase remaining time, the grid of the 4th NMOS tube 250 suspends.Fig. 3 is only not used in accurately measurement with explaining.It practice, first paragraph time t1 to t2 may account for a minimum part of total time t1 to t3, and second segment time t2 to t3 accounts for the overwhelming majority of total time t1 to t3.In the time is in t2 to the t3 time period, the grid of the 4th NMOS tube 250 enters high impedance status after conducting state and can improve the linearity of frequency mixer 220.Owing to the 4th NMOS tube 250 has a parasitic gate-source capacitance (C_gs), cause the grid of the 4th NMOS tube 250 to be alternatively coupled to source class.Electric capacity is equivalent to open circuit under direct current signal, and is equivalent to short circuit under AC signal.When the grid of the 4th NMOS tube 250 is driven to high-impedance state, due to gate-source parasitic capacitance (C_gs ₎Existence, LO_OUT can follow the trail of the change of AC signal of the source class input of the 4th NMOS tube 250, so during high-impedance state, the 4th NMOS tube 250 gate source voltage (V_gs) will keep being approximately equal to set V_gsLevel.Due to high impedance status period V_gsGenerally remain constant, when input signal is by four NMOS tube 250, the R of the 4th NMOS tube 250_onAlso generally remain constant.R compared to other frequency mixers MOSFET_onDepend on the signal passed through,

The same working condition for complementary local oscillation signal outfan LO_OUT_C is similar with the working condition of local oscillation signal outfan LO_OUT, simply the 4th PMOS 350 in field effect transistor frequency mixer 120 allows the transmission signal that IN end and OUT terminal can be two-way, makes mixing effect more preferable.

The present invention has the beneficial effects that: make use of gate-source parasitic capacitance (C_gs ₎Existence well control V_gsStabilization of level, makes R_onConstant, it is effectively improved the linearity of frequency mixer, make that the signal after mixing becomes is more accurate.

Claims

1. linearisation frequency mixer, including field effect transistor frequency mixer, it is characterised in that: the local oscillation signal of described field effect transistor frequency mixer is produced by driving stage, and described driving stage includes that local oscillation signal outfan, local oscillation signal outfan are high-impedance state.

Linearisation frequency mixer the most according to claim 1, it is characterized in that: described driving stage includes local oscillation signal input, local oscillation signal outfan, first phase inverter, first PMOS, second PMOS and the first NMOS tube, the input of the first phase inverter and the grid of the second PMOS and the first NMOS tube grid be coupled to the input of local oscillation signal, the grid of the first PMOS is coupled in the output of the first phase inverter, the source class of the first PMOS is coupled to power vd D, the drain of the first PMOS is coupled to the source of the second PMOS, the source ground connection of the first NMOS tube, the drain of the first NMOS tube is coupled to the drain terminal of the second PMOS, the drain terminal that second PMOS and the first NMOS tube connect altogether is connected to local oscillation signal outfan.

nullLinearisation frequency mixer the most according to claim 2，It is characterized in that: described driving stage includes complementary local oscillation signal outfan、Second phase inverter、3rd phase inverter、3rd PMOS、Second NMOS tube、3rd NMOS tube，The input of the second phase inverter connects local oscillation signal input，The outfan of the second phase inverter connects the grid of the 3rd PMOS and the grid of the second NMOS tube and the input of the 3rd phase inverter，The source ground connection of grid the 3rd NMOS tube of output termination the 3rd NMOS tube of the 3rd phase inverter，The drain of the 3rd NMOS tube is coupled to the source class of the second NMOS tube,The source of the 3rd PMOS meets power vd D，The drain of the 3rd PMOS couples the drain of the second NMOS tube，The drain that 3rd PMOS and the second NMOS tube connect altogether connects complementary local oscillation signal outfan.

Linearisation frequency mixer the most according to claim 3, it is characterised in that: described frequency mixer includes the 4th PMOS and the 4th NMOS tube, and the grid of the 4th NMOS tube connects local oscillation signal outfan, and the grid of the 4th NMOS tube connects complementary local oscillation signal outfan.