CN105810252B - A kind of storage unit, storage unit defect detection circuit and memory - Google Patents
A kind of storage unit, storage unit defect detection circuit and memory Download PDFInfo
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Abstract
This application discloses a kind of storage unit, two MOS transmission gates in the storage unit are bigrid MOS transmission gates, therefore when carrying out static noise margin test to said memory cells, are bilateral disturbance, therefore test intensity higher.
Description
Technical field
This application involves computer chip technology fields, more specifically to a kind of storage unit, storage unit defect
Detection circuit and memory.
Background technology
Memory (Memory) is the memory device in computer system, is used to store program and data, by multiple use
In the storage unit composition of storage binary code, as shown in Figure 1, storage unit is equivalent to two end to end phase inverter institutes
The latch of construction, each storage unit have its static noise margin.
Such as the schematic diagram that Fig. 2 is the storage unit static noise margin (Static Noise Margin, SNM), it is assumed that
Storage unit in Fig. 1 deposits ' 1 ' when Q points deposit ' 1 ', QB points and deposit ' 0 ', in Q when two opposite polarity noises are added in QB points
Point disturbs downwards Vn, deposits ' 0 ' point disturbance Vn upwards.Fig. 3 is the VTC curve graphs of SNM, shown in Fig. 3, according to the volt-ampere of storage unit
Characteristic curve, when Vn gradually increases, storage unit can be overturn.Vn just makes the value that storage unit is overturn, and it is single to characterize storage
Member deposits ' 1 ' noise resisting ability.Similarly, when Q points deposit ' 0 ', QB points and deposit ' 1 ', opposite polarity noise is added, Vn just makes storage
The value of unit overturning, then characterize the noise resisting ability that storage unit deposits ' 0 '.' 1 ' is deposited, the minimum of ' 0 ' noise resisting ability is deposited
Value, then referred to as static noise margin.
The storage unit static noise margin of existing defects is lower than the static noise margin of healthy and strong storage unit, deposits
The stability of value wants poor.Since 1. defected memory cell stability is poor, the value deposited be easy is interfered by noise, to system can
It is impacted by property.2. defect storage element reflects technological fluctuation and manufacturing defect in manufacturing process, technique is reflected
Yield situation.Therefore, it is necessary to the static noise margins of detecting defects storage unit.
In the prior art when being tested into line storage unit static noise margin, due to the MOS transmission gates in storage unit
Only there are one Gate, therefore there was only unilateral disturbance in test, thus causes to test in static noise margin test process
The low problem of intensity, therefore how to improve in static noise margin test process test intensity and become those skilled in the art urgently
Technical problem to be solved.
Invention content
In view of this, the application provides a kind of storage unit, static noise margin survey is carried out in the prior art for solving
When examination, the low problem of test intensity.
To achieve the goals above, it is proposed that scheme it is as follows：
A kind of storage unit, including：
Two MOS transmission gates in the storage unit are bigrid MOS transmission gates.
Preferably, in said memory cells, the bigrid MOS transmission gates are using fin field-effect transistor FinFET works
MOS transmission gates made of skill.
A kind of storage unit defect detection circuit, for testing said memory cells, including：
Bit line decoder and identical first bias generator of structure and the second bias generator；Wherein：
For obtaining the 3rd MOS transmission gates of WBL signals and for obtaining WBLB signals in the bit line decoder
4th MOS transmission gates are double-grid structure；
The first input end of first bias generator is used for obtaining mode selection signal, and the second input terminal is for obtaining
First clock signal；First output end is connected with the first grid of the first MOS transmission gates of the storage unit, exports for controlling
Make the control signal of the first MOS transmission gate opening degrees；2nd MOS transmission gates of second output terminal and the storage unit
First grid be connected, output is for controlling the control signals of the 2nd MOS transmission gate opening degrees；Third output end and described the
The second grid of one MOS transmission gates and the second grid of the 2nd MOS transmission gates are connected, for exporting first clock signal；
For obtaining the mode select signal, the second input terminal is used for the first input end of second bias generator
Obtain the second clock signal；First output end is connected with the first grid of the 3rd MOS transmission gates, and output is described for controlling
The control signal of 3rd MOS transmission gate opening degrees；Second output terminal is connected with the first grid of the 4th MOS transmission gates,
Export the control signal for controlling the 4th MOS transmission gate opening degrees；Third output end and the bit line decoder
Clock signal input terminal is connected.
Preferably, in said memory cells defect detection circuit, first bias generator includes：
Identical first and second voltage branch circuit of structure；
The voltage branch circuit includes：
The the first, second bigrid PMOS and the first, second bigrid NMOS that second end is connected with common node；
The first end of the first bigrid PMOS and the first bigrid NMOS are connected with first voltage source, for obtaining the
One input voltage；
The first end of the second bigrid PMOS and the second bigrid NMOS are connected with the second voltage source, for obtaining the
Two input voltages；
First input end is connected with the common node, second end is inputted as the second of first bias generator
End, control terminal are used to obtain the selector of the mode select signal.
Preferably, in said memory cells defect detection circuit, further include：
Output end respectively in first bias generator the first, second bigrid PMOS and first, second pair
The first and second grids of grid NMOS, which correspond, to be connected, for the first, second bigrid PMOS and first, the
The mode decoder of two bigrid NMOS output control signals.
Preferably, in said memory cells defect detection circuit, including：
The first voltage source and the second voltage source are all higher than the free voltage source of the storage unit.
A kind of memory, including：It is multiple such as above-mentioned storage units and it is multiple it is corresponding with the multiple storage unit such as
Above-mentioned storage unit defect detection circuit.
Preferably, in above-mentioned memory, including：
The bit line decoder of the multiple storage unit defect detection circuit is a common bit line decoder.
Preferably, in above-mentioned memory, including：
The first bias generator in the memory per line storage unit is a first shared bias generator.
Preferably, in above-mentioned memory, including：
Mode decoder in the multiple storage unit defect detection circuit is a common mode decoder.
It can be seen from the above technical scheme that the storage list disclosed in the present application for carrying out static noise margin test
In member, two MOS transmission gates are bigrid MOS transmission gates, therefore when static noise margin is tested, and are bilateral disturbance, therefore
Intensity higher is tested, the definition of noise margin is more in line with.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural domain of storage unit in the prior art；
Fig. 2 is the schematic diagram of storage unit static noise margin；
Fig. 3 is the VTC curve graphs of SNM；
Fig. 4 is a kind of structure chart of storage unit disclosed in the embodiment of the present application；
Fig. 5 is the structure chart of storage unit defect detection circuit disclosed in the embodiment of the present application；
Fig. 6 is the VTC curve graphs of the SNM of memory in test process；
Fig. 7 is a kind of structure chart of memory disclosed in the embodiment of the present application；
Fig. 8 is the test flow chart of the memory.
Specific implementation mode
Being directed to the MOS transmission gates of storage unit in the prior art, only there are one Gate so as to the storage list
Member carries out the problem there was only unilateral disturbance when static noise margin test, and cause test intensity low, and this application discloses one
Kind storage unit, storage unit defect detection circuit and memory.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 4 is a kind of structure chart of storage unit disclosed in the embodiment of the present application.
Referring to Fig. 4, the mechanism base of memory cell structure disclosed in the embodiment of the present application and storage unit in the prior art
This is identical, and difference lies in two MOS transmission gates (01 and 02) in storage unit disclosed in the present application are that bigrid MOS is passed
Defeated door.
Referring in storage unit disclosed in the present application, two MOS transmission gates (01 and 02) are bigrid MOS transmission gates, because
This is bilateral disturbance, therefore test intensity higher, is more in line with when carrying out static noise margin test to said memory cells
The definition of noise margin.
It is understood that fin field-effect transistor (FinFET) technique and planographic technique in the prior art are not
Together, the MOS device of FinFET is three-dimensional structure, by process, can cover the Gate layers of the tops Fin so that MOS devices
The raceway groove of part is controlled (double gate) by 2 ends Gate, the storage in technical solution disclosed in the above embodiments of the present application
Unit applies this characteristic of FinFET techniques.Bigrid MOS transmission gates in the i.e. described said memory cells are using fin
MOS transmission gates made of formula field-effect transistor FinFET techniques.
It is understood that corresponding with said memory cells, disclosed herein as well is one kind for above-mentioned storage list
Member carries out the storage unit defect detection circuit of static noise margin test, including：
Referring to Fig. 5, storage unit defect detection circuit disclosed in the above embodiments of the present application includes：
Identical first bias generator 1 (Bias generator1) of structure and 2 (Bias of the second bias generator
generator2)；
The bit line decoder 3 (YMUX) being connected with second bias generator；
Its specific connection relation is：
The first grid of first output end of first bias generator 1 and the first MOS transmission gates 01 of storage unit 4
It is connected, exports the control signal for controlling MOS transmission gate opening degrees；
The second output terminal of first bias generator 1 and the first of the 2nd MOS transmission gates 02 of the storage unit 4
Grid is connected, and exports the control signal for controlling MOS transmission gate opening degrees；
The first input end of first bias generator 1 is obtained for control model selection signal MS, the second input terminal
Input the clock signal for controlling the opening and closing of MOS transmission gates；
The third output end of first bias generator 1 and the first and second MOS transmission gates of the storage unit 4
Second grid is connected, and is used for output timing signal；
When the mode select signal MS that first bias generator 1 is got is 0, test pattern is not turned at this time,
First and second output end no signals of the first bigoted signal generator 1 export, the third output end output timing letter
Number, at this point, the state of the first and second MOS transmission gates is controlled by clock signal, the first bigoted signal generator 1 is right
The signal GPG_I and the first grid of the 2nd MOS transmission gates is carried out that the first grid of the first MOS transmission gates is controlled
The signal GPG_II of control follows clock signal variation, and when the mode select signal is 1, test pattern is opened at this time, institute
The output of third output end no signal is stated, first and second output end has signal output；
For obtaining the 3rd MOS transmission gates TN_BLB of WBL signals and for obtaining WBLB in the bit line decoder 3
4th MOS transmission gates TN_BL of signal is double-grid structure；
As shown in figure 5, the BLB signal output ends of the bit line decoder 3 and the BLB signals of the storage unit 4 are defeated
Enter end to be connected；
The BL signal output ends of the bit line decoder 3 are connected with the BL signal input parts of the storage unit 4；
The first grid phase of first output end of second bias generator 2 and the 3rd MOS transmission gates TN_BLB
Even；
The first grid phase of the second output terminal of second bias generator 2 and the 4th MOS transmission gates TN_BL
Even；
Third output end is connected with the clock signal input terminal of the bit line decoder 3；
Wherein, the first bias generator 1 described above obtains and the clock signal of output can be the first clock signal WL,
Second bias generator 2 obtains and the clock signal of output is the second clock signal YM.
As it can be seen that technical solution carries out static noise margin survey to storage unit disclosed in using the above embodiments of the present application
When examination, as the mode select signal MS=0, GPG_I, GPG_II follow the signal of the first clock signal WL, and described second
The signal GTN_BL and the 4th MOS is passed that bigoted signal generator 2 controls the first grid of the 3rd MOS transmission gates
The signal GTN_BLB that the first grid of defeated door is controlled follows the second clock signal YM variations, when the mode select signal
When MS=1, by first bias generator, 1 and second bias generator first end and second end export signal GPG_I,
GPG_II, GTN_BL, GTN_BLB are biased processor, since the first end and second end of the bias generator exports
Signal therefore to be signal for controlling MOS transmission gate opening degrees can adjust the MOS by the adjusting to the signal
The opening degree (such as full open or semi-open) of transmission gate, therefore the modulated property of bias voltage is more preferable.
It is understood that first bias generator and the second bias generator in the above embodiments of the present application can
For that can realize any one bias generator of above-mentioned function, for example, its concrete structure can bury shown in 5, including：
Identical first and second voltage branch circuit of structure；
The voltage branch circuit includes：
The first bigrid PMOS101, the second bigrid PMOS102 and the first double grid that second end is connected with common node
Pole NMOS103 and the second bigrid NMOS104；
The first end of the first bigrid PMOS101 and the first bigrid NMOS103 are connected with first voltage source, are used for
Obtain the first input voltage VDD2；
The first end of the second bigrid PMOS102 and the second bigrid NMOS103 are connected with the second voltage source, are used for
Obtain the second input voltage VSS2；
Further include：First input end is connected with the common node, second end as first bias generator
Two input terminals obtain clock signal, control terminal is used to obtain the selector 105 of the mode select signal MS.
Referring to Fig. 5, in technical solution disclosed in the above embodiments of the present application, each bigrid MOS all has two grid
Pole includes 16 grids altogether in first and second bias generator, and each grid corresponds to a control signal, such as is schemed
In S0~S7 and S0 '~S7 ', the control signal S0~S3 (S0 '~S3 ') is for selecting different partial-pressure structures, then
It selects to open intensity (opening or semi-open) by S4~S7 (S4`~S7`) again, therefore, using first and second bias
The modulated property of bias voltage that generator generates is more preferable.
It is understood that a in first and second bias generator for controlling in the above embodiments of the present application
The control signal of a grid same can be sent out by a controller, for example, said memory cells defect detection circuit, can also wrap
Include a mode decoder, multiple output ends of the mode decoder respectively in first and second bias generator
One, the first and second grids of the second bigrid PMOS and the first, second bigrid NMOS, which correspond, is connected, and is used for institute
The first, second bigrid PMOS and the first, second bigrid NMOS output control signals (S0~S7 and S0 '~S7 ') are stated,
In, the bias voltage of the GPG_I and GTN_BL signals is carried out by { S0, S1, S2, S3, S4, S5, S6, S7 } this group of decoded signal
Modulation；The bias voltage of GPG_II and GTN_BLB is by { S0 ', S1 ', S2 ', S3 ', S4 ', S5 ', S6 ', S7 ' } this group of decoded signal
It is modulated.As mode select signal MS=1, which enters test pattern.Assuming that Q points are deposited in said memory cells
' 1 ', by modulation so that the voltage value of GPG_I, GTN_BL are less than VDD, modulation is so that GPG_II, the voltage of GTN_BLB are higher than
VDD.Read operation is carried out to storage unit, at this point, third bigrid MOS and the 4th bigrid described in control bit line decoder
The WBL signals and WBLB signals of MOS and input are VDD high level, and the ports RBL and RBLB of the bit line decoder connect sensitive
Amplifier, the second clock signal of control YM=1, the first clock signal WL=1 open transmission gate progress read operation.Since processing is single
The opening degree of the metal-oxide-semiconductor TN_BL of metal-oxide-semiconductor PG_I and bit line decoder kind in member are weak, therefore cannot conduct well
The vdd voltage in processing unit is stated, on the other hand, the metal-oxide-semiconductor of metal-oxide-semiconductor PG_II and bit line decoder kind in processing unit
TN_BLB opening degrees are strong, can preferably conduct the vdd voltage in above-mentioned processing unit, are equivalent at this time in read operation,
Opposite polarity disturbance is carried out to storage unit both sides, disturbance read operation exactly is being carried out to storage unit.
Fig. 6 is the VTC curve graphs of the SNM of memory in test process.
Referring to Fig. 6, the application technical solution disclosed above is understood for convenience, and existing, applicant is bent with the VTC in Fig. 7
Line carries out the program more careful analysis, and metal-oxide-semiconductor PU_I and metal-oxide-semiconductor PD_I constitutes I phase inverters, VTC in storage unit 4
Curve is that curve A in Fig. 6, metal-oxide-semiconductor PU_II and metal-oxide-semiconductor PD_II constitute II phase inverters, is curve B in Fig. 6, when Q points deposit 1, Q
=' 1 ', QB point deposit 0, QB=' 0 '.Due to the analysis by front it is found that this circuit of Q-BL-WBL cannot conduct well
Vdd voltage, so the VTC curves of I phase inverters are moved to the left and (become dotted line from solid line in figure), this line of QB-BLB-WBLB
Road can preferably conduct vdd voltage, so the VTC curves of II phase inverters move up and (become dotted line from solid line in figure).
Therefore, the SNM (rectangular area in Fig. 6) for depositing ' 1 ' quadrant is tight by the two sides VTC of the VTC and II phase inverters of I phase inverters
It forces so that the quadrant becomes smaller, and increases the potential energy to ' 0 ' overturning.At this point, healthy and strong storage unit can also maintain ' 1 '
Value, and the storage unit of defect is then directly turned to ' 0 ' that quadrant.Similarly, storage unit can be detected with map function direction
Deposit ' 0 ' stability.Defected memory cell is just filtered out as a result,.At the end of read operation, using sense amplifier by RBL and
RBLB terminals read the value of storage unit, you can directly judge whether storage unit overturns in test.When model selection is believed
Then it is general mode when number MS=0.At this point, GPG_I, GPG_II follow the signal of WL, GTN_BL, GTN_BLB to follow the letter of YM
Number, storage unit carries out normal read-write operation.
It is understood that the first voltage source VDD2 in the above-mentioned bias circuit of the application and the second voltage source VSS2
It is all higher than the free voltage source of the storage unit, the voltage range to may make bias voltage that can reach big.
Be appreciated that on the basis of said memory cells defect detection circuit, disclosed herein as well is a kind of storages
Device, the memory may include：
Storage unit defect detection circuit described in multiple above-mentioned any one.
Fig. 7 is a kind of structure chart of memory disclosed in the embodiment of the present application.
Referring to Fig. 7, memory disclosed in the above embodiments of the present application may include multiple storage units, as every in Fig. 7
One Cell is a storage unit.
Referring to Fig. 7, in order to reduce cost, facilitate wiring, it is described in the memory in the above embodiments of the present application
The bit line decoder of multiple storage unit defect detection circuits is a common bit line decoder 701 (YMUX).It is described to deposit
Reservoir can arrange by ranks, and have a first shared bias generator 702 per line storage unit.And every one first bias
Corresponding one second bias generator 703 of generator, above-mentioned multiple second bias generators 703 are decoded by bus and bit line
Device 701 is connected.Mode decoder in the multiple storage unit defect detection circuit is a common mode decoder 704,
And the mode decoder 704 can be additionally used in bias generator sending mode selection signal MS.
It is understood that in the processor, it can also be including one for being sent to first bias generator 702
Corresponding one first bias of each output end of first driver 705 of the first clock signal, first driver 705 occurs
Device 702, for exporting matched first clock signal to first bias generator 702.
It is understood that in the processor, it can also be including one for being sent to second bias generator 703
The timing module 706 (Timing block) of second clock signal, the timing module 706 are additionally operable to the mode decoder
704 send RD and WD signals, it is, of course, also possible to include a switching value conversion module 707, are used for the bit line decoder
701 provide RBLB signals, RBL signals, WBLB signals and WBL signals.
Referring to Fig. 7, GPG_I, GPG_II signal lateral connection per line storage unit, finally with the first bias generator
702 are connected, and often the first clock signal WL of row accesses the first corresponding bias generator 702, are used in the normal mode,
Control GPG_I and GPG_II signals.GTN_BL the and GTN_BLB signals of YMUX are also coupled laterally to the second bias generator 703,
This 4 signals of second clock signal YM0~YM3 access corresponding second bias generator 703, are used in the normal mode,
Control corresponding GTN_BL and GTN_BLB signals.Mode decoder 704 is used for the mode selection command (Mode to getting
Option it) is decoded, generates matched S0~S7 and S0 '~S7 ' signals, to control the first and second bias generators
In voltage branch circuit.Mode select signal MS controls the first and second all bias generators and and the pattern solution
Code device 704, as mode select signal MS=1, into test pattern, to GPG_I, GPG_II, GTN_BL and GTN_BLB signal
It is biased；As MS=0, into general mode, pressure makes voltage branch circuit floating so that the often GPG_ of row processing unit
I, GPG_II signal follow the first clock signal WL signal intensities of every row, GTN_BL, GTN_BLB signal to follow corresponding second
Clock signal YM signal intensities.The sequential control circuit in memory in the prior art can be continued to use in this memory, by when
The CK triggerings of clock signal generate the first clock signal WL, the second clock signal YM, read signal RD and write signal WR and are written and read operation
Sequential generate.
Above-mentioned memory is biased whole storage arrays and YMUX when entering test pattern so that read operation has
There is tendentiousness.It is exactly read operation (the Disturb for having disturbance on progress both sides in fact at this point, carrying out read operation to storage unit
read).Since the storage unit of the storage unit place a line in read operation, chosen all is opened, all read at the same time
Value Operations, but the value of only selected storage unit can just be read out by YMUX and switching value conversion module.For example,
Read operation is carried out to Cell22 in Fig. 7 (storage unit 22), then Cell02, Cell12 and Cell32 are partly chosen, while
Read operation is carried out, but the value that only Cell22 is read can be exported by BL2, BLB2.So being disturbed to a storage unit
When dynamic reading, entire a line is all equally carrying out disturbance reading, and the forcing frequency for allowing for test in this way is very high, can more make defective
Storage unit overturning.In general mode, often capable GPG_I and GPG_II signals follow the first clock signal WL of every row,
When WL is opened, the transfer tube of storage unit fully opens, and when WL is closed, the transfer tube of storage unit completely closes.GTN_
BL and GTN_BLB signals follow corresponding second clock signal YM, and when YM is opened, the NMOS transfer tubes of YM controls are opened completely
It opens, when YM is closed, the NMOS transfer tubes of control completely close.As it can be seen that above-mentioned test circuit does not influence the normal of memory
Function.
It is understood that corresponding to memory disclosed in above-described embodiment, disclosed herein as well is one kind to deposit to above-mentioned
Testing process when reservoir is tested.
Referring to Fig. 8, which includes：
Step S101：Background data ' 1 ' is write to whole storage units；
Step S102：Disturbance reading ' 1 ' is carried out to a line storage unit to operate；
Step S103：Judge whether the often row of storage array has all detected, if so, executing step S104, otherwise executes
Step S102；
Step S104：Background data ' 0 ' is write to whole storage units；
Step S105：Disturbance reading ' 0 ' is carried out to a line storage unit to operate；
Step S106：Judge that the often row of storage array has all detected, if so, terminating, otherwise continues to execute step S105.
The above method passes through：Background data ' 1 ' is write to full array first, then array and YMUX are biased, to every
The storage unit of a line carries out the read operation of bilateral disturbance, and a line storage unit is tested, and next line is turned again to, until whole surveys
Complete, this just all detects the stability that the array that is over deposits ' 1 '.Background data ' 0 ' is write to full array again, array and YMUX are carried out
Another polar biasing carries out disturbance reading to each row, thus has detected the stability that array deposits ' 0 '.In disturbance read operation
In, the storage unit for reading Data flipping is exactly then defective storage unit.
Pass through above-mentioned analysis, it is seen that storage unit defect detection circuit and memory disclosed in the present application are compared to existing skill
Art：
1) this programme is bilateral disturbance, tests intensity higher, more meets the definition of static noise margin.
2) original measuring technology needs additional step to determine whether storage unit overturns, and this programme is in test, just
It is known that whether storage unit overturns, testing procedure is saved.
3) original measuring technology can only simultaneously apply a storage unit and disturb, where the unit that this programme is chosen
A line all carries out disturbance test at the same time, and test frequency higher improves testing efficiency.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (10)
1. a kind of storage unit defect detection circuit, which is characterized in that for testing storage unit, including：
Bit line decoder and identical first bias generator of structure and the second bias generator；Wherein, the bit line
The BLB signal output ends of decoder are connected with the BLB signal input parts of the storage unit, the BL letters of the bit line decoder
Number output end is connected with the BL signal input parts of the storage unit：
The 3rd MOS transmission gates in the bit line decoder for obtaining WBL signals and for obtaining WBLB signals the 4th
MOS transmission gates are double-grid structure；
The first input end of first bias generator is used for obtaining mode selection signal, and the second input terminal is for obtaining first
Clock signal；First output end is connected with the first grid of the first MOS transmission gates of the storage unit, exports for controlling
State the control signal of the first MOS transmission gate opening degrees；The of 2nd MOS transmission gates of second output terminal and the storage unit
One grid is connected, control signal of the output for controlling the 2nd MOS transmission gate opening degrees；Third output end and described first
The second grid of the second grid of MOS transmission gates and the 2nd MOS transmission gates is connected, for exporting first clock signal；
The first input end of second bias generator is for obtaining the mode select signal, and the second input terminal is for obtaining
Second clock signal；First output end is connected with the first grid of the 3rd MOS transmission gates, exports for controlling the third
The control signal of MOS transmission gate opening degrees；Second output terminal is connected with the first grid of the 4th MOS transmission gates, output
Control signal for controlling the 4th MOS transmission gate opening degrees；Third output end and the bit line decoder sequential
Signal input part is connected.
2. storage unit defect detection circuit according to claim 1, which is characterized in that the first bias generator packet
It includes：
Identical first and second voltage branch circuit of structure；
The voltage branch circuit includes：
The the first, second bigrid PMOS and the first, second bigrid NMOS that second end is connected with common node；
The first end of the first bigrid PMOS and the first bigrid NMOS are connected with first voltage source, defeated for obtaining first
Enter voltage；
The first end of the second bigrid PMOS and the second bigrid NMOS are connected with the second voltage source, defeated for obtaining second
Enter voltage；
First input end is connected with the common node, second input terminal of the second end as first bias generator, control
End processed is used to obtain the selector of the mode select signal.
3. storage unit defect detection circuit according to claim 2, which is characterized in that further include：
Output end respectively with the first, second bigrid PMOS and the first, second bigrid in first bias generator
The first and second grids of NMOS, which correspond, to be connected, for the first, second bigrid PMOS and first, second pair
The mode decoder of grid NMOS output control signals.
4. storage unit defect detection circuit according to claim 2, which is characterized in that including：
The first voltage source and the second voltage source are all higher than the free voltage source of the storage unit.
5. a kind of memory, which is characterized in that including：Multiple storage units and multiple such as any one of claim 1-4 institutes
The storage unit defect detection circuit stated.
6. memory according to claim 5, which is characterized in that two MOS transmission gates in the storage unit are double
Gate MOS transmission gate.
7. memory according to claim 5, which is characterized in that the bigrid MOS transmission gates are to be imitated using fin field
MOS transmission gates made of transistor FinFET techniques.
8. memory according to claim 7, which is characterized in that including：
The bit line decoder of the multiple storage unit defect detection circuit is a common bit line decoder.
9. memory according to claim 7, which is characterized in that including：
The first bias generator in the memory per line storage unit is a first shared bias generator.
10. memory according to claim 7, which is characterized in that including：
It is described when the storage unit defect detection circuit is the storage unit defect detection circuit described in claim 3
Mode decoder in multiple storage unit defect detection circuits is a common mode decoder.
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| CN104183269A (en) * | 2014-08-29 | 2014-12-03 | 东南大学 | Low-voltage single-end read-write SRAM (Static Random Access Memory) storage unit and control method |
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| CN101427321A (en) * | 2006-04-24 | 2009-05-06 | Nxp股份有限公司 | SRAM cell |
| CN102027588A (en) * | 2008-05-13 | 2011-04-20 | 意法半导体(鲁塞)公司 | Read-only memory with EEPROM structure |
| CN101727971A (en) * | 2008-10-22 | 2010-06-09 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
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