CN105808803B - A kind of integrated circuit diagram automatic testing method - Google Patents
A kind of integrated circuit diagram automatic testing method Download PDFInfo
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- CN105808803B CN105808803B CN201410844687.7A CN201410844687A CN105808803B CN 105808803 B CN105808803 B CN 105808803B CN 201410844687 A CN201410844687 A CN 201410844687A CN 105808803 B CN105808803 B CN 105808803B
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Abstract
The invention discloses a kind of integrated circuit diagram automatic testing methods, belong to Semiconductors data detection technique field；Method include: by domain be converted into include path type and polygon-type GDS file；The data of path type are converted to the data of polygon-type, and are gathered according to the largest connected domain that every layer of metal layer is calculated in the data of polygon-type；Find the default associated all metal layers of pin；The largest connected domain for covering default pin is found in the metal layer for being associated with default pin；Judge to be associated in all metal layers between the largest connected domain of default pin and whether there is through-hole connection: if having between largest connected domain, there is no through-holes to connect, and exporting integrated circuit diagram, there are the judging results of hanging pin.The beneficial effect of above-mentioned technical proposal is: solving the problems, such as not detecting the hanging pin that may include in layout design in time by existing detection means, shortens the design cycle, promotes design efficiency.
Description
Technical field
The present invention relates to Semiconductors data detection technique field more particularly to a kind of integrated circuit diagram sides of detection automatically
Method.
Background technique
In the prior art, it will usually a degree of automatic detection be carried out to integrated circuit diagram, to detect integrated circuit
Whether whether layout design is consistent with basic circuit diagram, and be consistent with IC design rule.
In the prior art, the automatic testing method being applied to when usually detecting to integrated circuit diagram can not detect
Out the problem of " hanging " pin that may be present in integrated circuit diagram.Therefore it will lead to the entire design cycle seriously to be elongated,
It causes to seriously affect to the manufacture to integrated circuit and into market.
Summary of the invention
According to defect existing in the prior art, a kind of technical side of integrated circuit diagram automatic testing method is now provided
Case, it is intended to achieve the purpose that carry out integrated circuit diagram automatic detection to detect corresponding hanging pin problem；
Above-mentioned technical proposal specifically includes:
A kind of integrated circuit diagram automatic testing method, wherein step includes:
The integrated circuit diagram that design is completed is converted into including two kinds of data of path type and polygon-type by step S1
The GDS file of type；
The data of the path type are converted to the data of the polygon-type by step S2, and according to described polygon
The set in the largest connected domain for including is calculated in every layer of metal layer in the data of shape type；
Step S3 finds the associated all metals of the default pin being not yet judged including one in the GDS file
Layer；
Step S4 finds the institute for covering the default pin respectively in every layer of metal layer for being associated with the default pin
State largest connected domain；
Whether step S5 judges to be associated in all metal layers between the largest connected domain of the default pin and deposit
It is connected in through-hole:
If having between largest connected domain, there is no through-holes to connect, and exporting integrated circuit diagram, there are the judgements of hanging pin
As a result.
Preferably, integrated circuit diagram automatic testing method, wherein in the step S5, if being associated with described default
There is through-hole connection between the largest connected domain of pin, then exports the default pin and pass through the judgement knot detected automatically
Fruit.
Preferably, integrated circuit diagram automatic testing method, wherein in the step S5, if the judging result table
Show that the default pin passes through to detect automatically, then execute following step:
Step S6 judges whether to judge to finish to all pins in the GDS file:
If judging to finish to all pins, exports integrated circuit diagram and pass through the testing result detected automatically, then
It exits；
The pin being not yet judged if it exists then returns to the step S3.
Preferably, the integrated circuit diagram automatic testing method, wherein before executing the step S2, be first carried out with
Lower step:
It obtains the GDS file and is parsed, to establish the data store organisation of the corresponding GDS file；
The data store organisation of the corresponding GDS file is a Storage Structure of Tree:
The host node of the Storage Structure of Tree preserves the related data of top layer unit in the integrated circuit diagram, institute
Top layer unit is stated for indicating the metal layer of top in the integrated circuit diagram；
Associated each child node preserves each non-top layer unit in the integrated circuit diagram under the host node
Related data, the non-top layer unit are used to indicate to remove in the integrated circuit diagram except the metal layer of top
The metal layer.
Preferably, integrated circuit diagram automatic testing method, wherein in the step S2, obtain described largest connected
The method of the set in domain specifically includes:
Step S21, according to the data of the corresponding polygon-type, for one layer of metal layer meter not yet by calculating
Calculation obtains corresponding multiple largest connected domains；
All largest connected domains in the correspondence metal layer are merged operation, to be corresponded to by step S22
The set in the largest connected domain of the metal layer；
Step S23 judges whether there is the metal layer not yet by calculating；
The step S21 is then not yet returned by the metal layer calculated if it exists；
The step S3 is then not yet gone to by the metal layer calculated if it does not exist.
Preferably, integrated circuit diagram automatic testing method, wherein the step S3 is specifically included:
Step S31, according to the top layer unit, lookup obtains all metals for including in the Storage Structure of Tree
All pins in layer；
Step S32, search obtain include all metal layers of the same default pin set, then switch into
The step S4.
Preferably, integrated circuit diagram automatic testing method, wherein in the step S5, judgement is per adjacent two
It is associated between the largest connected domain of the pin and whether there is through-hole connection:
If having between adjacent largest connected domain, there is no through-holes to connect, and exporting integrated circuit diagram, there are hanging pins
Judging result, with backed off after random.
Preferably, integrated circuit diagram automatic testing method, wherein in the step S5, judgement is per adjacent two
It is associated between the largest connected domain of the pin and whether there is through-hole connection:
If existing, the step S6 is gone to.
The beneficial effect of above-mentioned technical proposal is: by finding the most Dalian in each layer metal layer including the same pin
Logical domain, and judge that the mode that whether there is through-hole connection between largest connected domain detects layout design with the presence or absence of hanging pin
The problem of, it can make up for it the prior art and can not using such as design rule detection method or schematic diagram consistency detecting method
Detect that the defect that whether there is hanging pin in layout design promotes design and system so as to shorten the entire design cycle in time
The efficiency made.
Detailed description of the invention
Fig. 1 is in preferred embodiment of the invention, and there are the schematic diagrames of hanging pin in integrated circuit diagram；
Fig. 2 is in preferred embodiment of the invention, and in integrated circuit diagram, there is no hanging for single pin
The schematic diagram of pin；
Fig. 3-6 is a kind of process signal of integrated circuit diagram automatic testing method in preferred embodiment of the invention
Figure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
In the prior art, integrated circuit diagram is usually referred to as graph data stream file (Graphic Data with one kind
Stream file format) is exported and saves.GDS file is a kind of data streaming file stored in binary form, is one
The generally acknowledged Semiconductor Physics domain storage file format of kind industry.
In the prior art, as the size of semiconductor chip is smaller and smaller, the integrated level of one single chip is also gradually increased, version
The scale of chart database is increasing, this makes the automatic detection-phase in IC Layout, needs to detect and verify
Project it is also more and more, wherein just include verifying " hanging " pin the problem of.
So-called hanging pin, if referring on different metal layers includes the same pin, then each covering pin
Metal layer in largest connected domain between must have through-hole as connection, otherwise will form hanging pin phenomenon.
For example, as shown in Figure 1, there is pin pin_A in metal layer { M1, M2, M3, M4 }, and in metal layer M1 and M2
Between there is no any through-hole connection (in Fig. 1 and Fig. 2, through-hole is indicated with A), it can be considered that pin_A is hanging pin.
Correspondingly, as shown in Fig. 2, similarly there are pin pin_A, and any two in metal layer { M1, M2, M3, M4 }
There are through-hole connections between the largest connected domain of a metal layer, so that pin pin_A is not hanging pin.
In the prior art, to the IP module (Intellectual of integrated circuit diagram, especially integrated circuit
Property core, the standard module with relatively independent interface verified by being pre-designed, in advance) it is detected automatically
Several detection methods would generally be used, including domain is designed rule detection (Design Rule Check, DRC), and/
Or the detection (Layout Versus Schematic, LVS) etc. with schematic diagram consistency is carried out to domain.But either DRC
Detection or LVS detection, the problem of can not all detecting in IP module with the presence or absence of hanging pin.Therefore, similar problems have very much
It may can be just found in the second half section of entire chip design cycle, such as placement-and-routing's stage, so that entire design can be elongated
Period causes to seriously affect to the design process of chip.
In preferred embodiment of the invention, it is based on the above-mentioned problems in the prior art, a kind of integrated electricity is now provided
Road domain automatic testing method.
Said integrated circuit domain automatic testing method is as shown in figure 3, specifically include:
The integrated circuit diagram that design is completed is converted into including two kinds of data of path type and polygon-type by step S1
The GDS file of type；
In preferred embodiment of the invention, in above-mentioned steps S1, the integrated circuit diagram that design is completed is obtained first, and
Integrated circuit diagram is converted to form corresponding graph data stream file (hereinafter referred to as GDS file).Preferable reality of the invention
It applies in example, includes two kinds of data types of path type and polygon-type inside GDS file.The data of so-called path type, can
With for marking wider path-line in integrated circuit diagram, the data of so-called polygon-type can be used for marking integrated electricity
The polygonal region surrounded in the domain of road by path-line.Therefore, using the data of above two type, it can completely indicate whole
A IC Layout.
The data of path type are converted to the data of polygon-type by step S2, and according to the data of polygon-type
The set in the largest connected domain for including is calculated in every layer of metal layer；
In preferred embodiment of the invention, due to include in GDS file data type can there are two types of: path type
(Path) and polygon-type (Boundary), and before the calculating for carrying out largest connected domain, it is necessary first to will be in GDS file
Path type data conversion at corresponding polygon-type data.
In preferred embodiment of the invention, by the data conversion of the path type in GDS file at corresponding polygon
The operation of the data of type can be carried out by special software tool, such as in Cadence software tool, provide use
The data by the data conversion of the path type in GDS file at corresponding polygon-type may be implemented in person's corresponding operation.
In preferred embodiment of the invention, as shown in figure 5, obtaining the set in largest connected domain in above-mentioned steps S2
Method specifically includes:
Step S21 is not yet calculated by the metal layer calculated according to the data of corresponding polygon-type for one layer
To corresponding multiple largest connected domains；
In preferred embodiment of the invention, for one layer of metal layer without calculating, include according in GDS file
The data of polygon-type calculate the largest connected domain for including in one layer of metal layer using polygon algorithm.
The largest connected domain for including in preferred embodiment of the invention, in same layer metal layer usually not only one,
Therefore in above-mentioned steps S21, by multiple largest connected domains that corresponding same layer metal layer is calculated.
All largest connected domains in corresponding metal layer are merged operation by step S22, to obtain corresponding metal layer
The set in largest connected domain；
In preferred embodiment of the invention, operation is merged on the basis of above-mentioned steps S21, one layer will be corresponded to
Multiple largest connected domains of metal layer merge the set to form corresponding largest connected domain.
Step S23 judges whether there is the metal layer not yet by calculating；
Not yet through metal layer calculating if it exists, then return step S21；
Step S is then not yet gone to by the metal layer calculated if it does not exist.
In preferred embodiment of the invention, the above calculating is carried out to every layer of metal layer, and is finally obtained every layer corresponding
The set in the largest connected domain of metal layer.
For example, as shown in Figs. 1-2, including four layers of metal layer { M1, M2, M3, M4 } in IC Layout, then corresponding to
Every layer of metal layer carries out the calculating in largest connected domain, and merges the set to form the largest connected domain of corresponding every layer of metal layer.
Step S3 finds the associated all metal layers of the default pin being not yet judged including one in GDS file；
In preferred embodiment of the invention, before handling GDS file, GDS file is parsed first,
And corresponding data store organisation is established according to parsing result.
In preferred embodiment of the invention, above-mentioned data store organisation can be a kind of Storage Structure of Tree.
It specifically, include under host node and the node in Storage Structure of Tree in preferred embodiment of the invention
Multiple child nodes.In preferred embodiment of the invention, top layer unit is preserved in the host node of Storage Structure of Tree
Related data, and the related data of each non-top layer unit is preserved in each child node under the host node.
It therefore, include relevant data of top layer unit and non-in above-mentioned GDS file in preferred embodiment of the invention
The relevant data of top layer unit.Further, in preferred embodiment of the invention, so-called top layer unit refers to integrated circuit
The metal layer of top is in layout design；So-called non-top layer unit refers in IC Layout and removes in most
Other metal layers outside the metal layer of top layer.In preferred embodiment of the invention, by being stored in the top layer unit of host node,
Other non-top layer units being stored under corresponding child node can be found.
In preferred embodiment of the invention, the top layer being stored under host node can be found by the title of top layer unit
The related data of unit.
Then in preferred embodiment of the invention, as shown in fig. 6, above-mentioned steps S3 is specifically included:
Step S31 searches obtain in all metal layers for including in Storage Structure of Tree all and draws according to top layer unit
Foot；
In preferred embodiment of the invention, the top layer unit, subsequent basis are found according to the title of top layer unit first
The top layer unit finds all non-top layer units under it, finally according to the relevant data of all units (i.e. all metal layer phases
The data of pass) find all pins for including in every layer of metal layer.
Step S32, search obtain include all metal layers of the same default pin set, then switch into step S4.
Such as shown in Fig. 1-2, the metal layer including the same pin pin_A includes { M1, M2, M3, M4 }, therefore is searched
To above-mentioned four layers of metal layer, and export the set of corresponding metal layer.
Step S4 finds respectively in every layer of metal layer for being associated with default pin and covers the largest connected of default pin
Domain；
In preferred embodiment of the invention, the same default pin is corresponded to according to obtained in above-mentioned steps S32 first
Metal layer set, find out the largest connected domain that default pin is associated in the set in the largest connected domain of every layer of metal layer.
Further, in preferred embodiment of the invention, a covering is found in the set in the largest connected domain of every layer of metal layer
The largest connected domain of above-mentioned default pin thus defines in above-mentioned steps S3 for every layer of metal layer, only can find one most
Big connected domain.
In preferred embodiment of the invention, every layer of metal that obtained correspondence includes the same default pin is searched in output
The largest connected domain of layer.
Step S5 judges to be associated between the largest connected domain of default pin whether there is through-hole company in all metal layers
It connects:
If having between largest connected domain, there is no through-holes to connect, and exporting integrated circuit diagram, there are the judgements of hanging pin
As a result.
In preferred embodiment of the invention, a corresponding default pin is wrapped by that can search in above-mentioned steps
Include the largest connected domain that the default pin is covered in every layer of metal layer of the default pin.Then in above-mentioned steps S4, these are judged
Whether there is through-hole connection between largest connected domain.Further, in preferred embodiment of the invention, judge adjacent two
Whether there is through-hole connection between largest connected domain in layer metal layer.
In preferred embodiment of the invention, have in adjacent two metal layers (including same default pin) if it exists
Largest connected domain (cover this default pin) between there is no through-hole to connect, such as shown in Fig. 1, then judge the integrated circuit version
There is the hanging pin of pin pin_A shown in similar Fig. 1 in G- Design.
In preferred embodiment of the invention, in above-mentioned steps S5, if the most Dalian in any two layers adjacent metal layer
There are through-hole connections between logical domain, then it represents that and default pin is not hanging pin (pin pin_A as shown in Figure 2), because
This output indicates that default pin passes through the judging result detected automatically.
In preferred embodiment of the invention, in above-mentioned steps S5, if the judging result of output indicates that default pin passes through
Pair that is, there is through-hole connection between largest connected domain, then continue to execute following step S6 (as shown in Figure 4) in automatic detection, i.e.,
Next pin not yet by judgement is judged accordingly.
Correspondingly, in preferred embodiment of the invention, in above-mentioned steps S4, draw if the judging result of output indicates default
Foot does not pass through to be detected automatically, i.e., when default pin is hanging pin, then exits entire testing process.
Step S6 judges whether to judge to finish to all pins in GDS file:
If judging to finish to all pins, exports layout design and pass through the testing result detected automatically, with backed off after random；
The pin being not yet judged if it exists, then return step S3.
In preferred embodiment of the invention, when judging to finish to all pins, and all pins are not to draw vacantly
When foot, then it is assumed that the IC Layout can be by detecting automatically.Conversely, have if it exists pin be hanging pin when,
Indicating layout design in output, there are exit testing process while the judging result of hanging pin.
In conclusion technical solution of the present invention is, layout design is converted into corresponding GDS file and is exported, parsed
The GDS file simultaneously establishes corresponding Storage Structure of Tree, and by the data conversion of the path type in GDS file at polygon
The data of type.
Then, it according to GDS file, is obtained in every layer of metal layer most using polygon algorithm and corresponding union operation
The set of big connected domain, and using the top layer unit related data in Storage Structure of Tree, lookup obtain include in GDS file
All pins, search to obtain all metal layers including the pin for each pin；
Finally, finding the largest connected domain for covering the pin in every layer of metal layer for including the same pin, and judge
Whether there are the connections of corresponding through-hole between the largest connected domain of adjacent two metal layers, i.e., including the same pin
Whether linked together between largest connected domain with through-hole.
In the present invention, having between the largest connected domain in adjacent two metal layers if it exists does not have through-hole connection, such as
Situation shown in Fig. 1, then it represents that the pin is hanging pin；If include in any two layers adjacent metal layer is largest connected
There are through-hole connections between domain, then it represents that the pin passes through detection.
In the present invention, the above process is recycled, to make corresponding judgement to all pins for including in GDS file, thus
Complete the automatic detection to entire layout design.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (8)
1. a kind of integrated circuit diagram automatic testing method, which is characterized in that step includes:
The integrated circuit diagram that design is completed is converted into including two kinds of data types of path type and polygon-type by step S1
GDS file；
The data of the path type, are converted to the data of the polygon-type by step S2, and according to the step S1 and
The largest connected domain for including is calculated in every layer of metal layer in the data of all polygon-types in the step S2
Set；
Step S3 finds the associated all metal layers of the default pin being not yet judged including one in the GDS file；
Step S4 is found described in the covering default pin most respectively in every layer of metal layer for being associated with the default pin
Big connected domain；
Whether step S5 judges to be associated in all metal layers to exist between the largest connected domain of the default pin and lead to
Hole connection:
If having between largest connected domain, there is no through-holes to connect, and exports judgement knot of the integrated circuit diagram there are hanging pin
Fruit.
2. integrated circuit diagram automatic testing method as described in claim 1, which is characterized in that in the step S5, if closing
It is coupled between the largest connected domain of the default pin and there is through-hole connection, then export the default pin and pass through automatically
The judging result of detection.
3. integrated circuit diagram automatic testing method as claimed in claim 2, which is characterized in that in the step S5, if institute
Stating judging result indicates that the default pin by detecting automatically, then executes following step:
Step S6 judges whether to judge to finish to all pins in the GDS file:
If judging to finish to all pins, exports integrated circuit diagram and pass through the testing result detected automatically, with backed off after random；
The pin being not yet judged if it exists then returns to the step S3.
4. integrated circuit diagram automatic testing method as described in claim 1, which is characterized in that execute the step S2 it
Before, following steps are first carried out:
It obtains the GDS file and is parsed, to establish the data store organisation of the corresponding GDS file；
The data store organisation of the corresponding GDS file is a Storage Structure of Tree:
The host node of the Storage Structure of Tree preserves the related data of top layer unit in the integrated circuit diagram, the top
Layer unit is used to indicate the metal layer of top in the integrated circuit diagram；
Associated each child node preserves the correlation of each non-top layer unit in the integrated circuit diagram under the host node
Data, the non-top layer unit are used to indicate to remove in the integrated circuit diagram described except the metal layer of top
Metal layer.
5. integrated circuit diagram automatic testing method as described in claim 1, which is characterized in that in the step S2, obtain
The method of the set in the largest connected domain specifically includes:
Step S21 is not yet calculated by the metal layer calculated according to the data of the corresponding polygon-type for one layer
To corresponding multiple largest connected domains；
All largest connected domains in the correspondence metal layer are merged operation, described in being corresponded to by step S22
The set in the largest connected domain of metal layer；
Step S23 judges whether there is the metal layer not yet by calculating；
The step S21 is then not yet returned by the metal layer calculated if it exists；
The step S3 is then not yet gone to by the metal layer calculated if it does not exist.
6. integrated circuit diagram automatic testing method as claimed in claim 4, which is characterized in that the step S3 is specifically wrapped
It includes:
Step S31, according to the top layer unit, lookup is obtained in all metal layers for including in the Storage Structure of Tree
All pins；
Step S32, search obtain include all metal layers of the same default pin set, then switch into described in
Step S4.
7. integrated circuit diagram automatic testing method as described in claim 1, which is characterized in that in the step S5, judgement
It is associated between the largest connected domain of the pin whether there is through-hole connection per adjacent two:
If having between adjacent largest connected domain, there is no through-holes to connect, and exports integrated circuit diagram sentencing there are hanging pin
Break as a result, with backed off after random.
8. integrated circuit diagram automatic testing method as claimed in claim 3, which is characterized in that in the step S5, judgement
It is associated between the largest connected domain of the pin whether there is through-hole connection per adjacent two:
If existing, the step S6 is gone to.
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| CN107967371B (en) * | 2016-10-18 | 2021-02-23 | 展讯通信（上海）有限公司 | Method and device for deleting redundant metal wires on Net |
| CN108228917B (en) * | 2016-12-09 | 2021-08-03 | 展讯通信（上海）有限公司 | Circuit schematic diagram inspection device and method |
| CN107239619B (en) * | 2017-06-06 | 2020-06-16 | 北京华大九天软件有限公司 | Method for quickly cutting off acute angle in integrated circuit layout |
| CN110888087B (en) * | 2018-08-20 | 2021-12-03 | 珠海零边界集成电路有限公司 | Layout interconnection line defect inspection system and inspection method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7464350B1 (en) * | 2006-08-11 | 2008-12-09 | Xilinx, Inc. | Method of and circuit for verifying a layout of an integrated circuit device |
| CN101866371A (en) * | 2009-04-16 | 2010-10-20 | 奇景光电股份有限公司 | Verification method of stereoscopic integrated circuit |
| CN102663169A (en) * | 2012-03-21 | 2012-09-12 | 领佰思自动化科技(上海)有限公司 | Method and system for design rule checking of integrated circuit layout |
| CN102663170A (en) * | 2012-03-21 | 2012-09-12 | 领佰思自动化科技(上海)有限公司 | Inspection method for minimumcut rule in integrated circuit layout design |
-
2014
- 2014-12-30 CN CN201410844687.7A patent/CN105808803B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7464350B1 (en) * | 2006-08-11 | 2008-12-09 | Xilinx, Inc. | Method of and circuit for verifying a layout of an integrated circuit device |
| CN101866371A (en) * | 2009-04-16 | 2010-10-20 | 奇景光电股份有限公司 | Verification method of stereoscopic integrated circuit |
| CN102663169A (en) * | 2012-03-21 | 2012-09-12 | 领佰思自动化科技(上海)有限公司 | Method and system for design rule checking of integrated circuit layout |
| CN102663170A (en) * | 2012-03-21 | 2012-09-12 | 领佰思自动化科技(上海)有限公司 | Inspection method for minimumcut rule in integrated circuit layout design |
Non-Patent Citations (1)
| Title |
|---|
| New algorithms for increased efficiency in hierarchical design rule checking;Nils Hedenstierna 等;《Integration,the VLSI Journal》;19871231;第5卷(第3-4期);319-336 |
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