CN105808497A - Data processing method - Google Patents

Abstract

The present invention provides a data processing method, which is applied to a CC-NUMA system. The CC-NUMA includes a first processor and a second processor, the first processor and the second processor are connected through a bus, and the first processor is connected to the second processor. A processor includes a first core, a first cache, and a first decoder; the second processor includes a second home agent, a second cache, and the second home agent is connected to a second memory, including: a first The kernel sends a first request, and the first request carries the address of the data to be read; the first cache receives the first request, and finds out from the first decoder that the address points to the second memory , sending a second request to the second home agent, the data requested by the second request includes at least two parts of data, the first part includes the data to be read, and the second home agent preferentially provides the latest first part to the data Describe the first kernel, and then provide the rest. Applying the invention can reduce the waiting time of the first kernel.

Description

A data processing method

technical field

The invention relates to the field of processors, in particular to cache coherent non-uniform memory access.

Background technique

The multi-processor system is connected through the system bus to form a Cache Coherency-Non Uniform Memory Access (CC-NUMA) system. The CC-NUMA system is essentially a distributed shared memory multi-processor system. Each processor has its own private cache (Cache) and is mounted with memory. Due to the tight coupling relationship between the existing processor and the memory controller, when the processor accesses memory in different address spaces, the access speed and bandwidth are inconsistent. That is to say, if you access your own memory, the access speed is relatively fast, and if you access the memory mounted on other processors, the speed is relatively slow.

In the existing CC-NUMA system, a unified data granularity is used to solve the data consistency problem. For example, the granularity of a common cache line is 64 bytes (byte). In most cases, the data that the program actually needs to use is far less than 64 bytes. Taking 8 bytes as an example, the 8 bytes of data are stored in the memory. Then, according to the value of the granularity, the data read from the memory It is 64 bytes of data, and then after a series of cache consistency processing, the CPU (cache and core) finally receives the 64 bytes of data. These 64 bytes of data contain the 8 bytes of data that the program needs to use. However, the time required to solve the cache coherence problem of 64 bytes of data and return it to a specific CPU (the person who requested the data) is much longer than 8 bytes. The corresponding time of the data.

In the prior art, when the processor core is running a program, the waiting time for data is relatively long.

Contents of the invention

The invention provides a data processing method, which can reduce the waiting time of the processor core for data.

In a first aspect, the present invention provides a data processing method, which is applied to a cache-coherent non-uniform memory access CC-NUMA system, and CC-NUMA includes a first processor and a second processor, and the first processor and the The second processor is connected by a bus, the first processor includes a first core, a first cache, and a first decoder; the second processor includes a second home agent, a second cache, and the second home Proxy and second memory connections, including:

The first core sends a first request, and the first request carries the address of the data to be read; the first cache receives the first request, and finds out from the first decoder that the address points to the first Two memory, send a second request to the second home agent, the data requested by the second request includes at least two parts of data, the first part includes the data to be read, and the total size of the at least two parts of data is equal to the cache The size of the line; after the second home agent receives the second request, it provides the latest first part of data to the first cache; and then provides the latest rest of the data to the first cache, which includes At least two parts of data have adjacent addresses in the second memory; the first cache acquires the data to be read from the first part of data and sends it to the first core, and caches the latest At least two parts of data.

In the first possible implementation solution of the first aspect, providing the latest first part of data to the first cache; and then respectively providing the latest rest of the data to the first cache, specifically includes: from the second memory read out the directory information of the first part of data, according to the data status recorded in the directory information, if the first part of data stored in the second memory is the latest first part of data, then the second home agent sends the latest first part of data to the The first cache, otherwise, find the cache with the latest first part of data, and send the first part of data in the cache with the latest first part of data to the first cache; then for the rest of the data: from the second Reading out the directory information in the memory, according to the data state recorded in the directory information, if the part of the data stored in the second memory is the latest data, the second home agent sends the latest part of the data to the first cache, Otherwise, search for the cache with the latest part of the data, and send the part of the data in the cache with the latest part of the data to the first cache.

In the second possible implementation solution of the first aspect, the latest first part of data is provided to the first cache; and then the latest rest of the data are respectively provided to the first cache, specifically including:

Send a query request for the first part of data to all caches except the first cache, and send the first part of data in the cache with the latest first part of data to the first cache;

Then for the remaining parts of data: send the query request of this part of data to all caches except the first cache, and send the data in the cache with the latest part of the data to the first cache.

In a third possible implementation solution of the first aspect, the first part of data is the data to be read.

In a fourth possible implementation solution of the first aspect, the first part of data is greater than or equal to the data to be read and is a minimum integer multiple of 8 bytes; the size of the cache line is 64 bytes.

In a second aspect, the present invention provides a data processing method, which is applied to a cache-coherent non-uniform memory access CC-NUMA system. CC-NUMA includes a first processor and a second processor, and the first processor and the The second processor is connected by a bus, the first processor includes a first core, a first cache, and a first decoder; the second processor includes a second home agent, a second cache, and the second home The agent is connected to the second memory, including: the first core sends a first request, and the first request carries the address of the data to be read; the first cache receives the first request, and the first request is received from the first decoder Querying that the address points to the second memory, sending a second request to the second home agent, the data requested by the second request includes at least two parts of data, the first part includes the data to be read, and the The total size of at least two parts of data is equal to the size of the cache line; after receiving the second request, the second home agent provides the latest first part of data to the first cache; and then provides the latest rest of the data to In the first cache, at least two parts of data are adjacent to each other in the second memory; the first cache sends the latest first part of data to the first core, and caches the latest The at least two parts of data.

In the first possible implementation solution of the second aspect, providing the latest first part of data to the first cache; and then respectively providing the latest rest of the data to the first cache, specifically includes: from the second memory read out the directory information of the first part of data, according to the data status recorded in the directory information, if the first part of data stored in the second memory is the latest first part of data, then the second home agent sends the latest first part of data to the The first cache, otherwise, find the cache with the latest first part of data, and send the first part of data in the cache with the latest first part of data to the first cache; then for the rest of the data: from the second Reading out the directory information in the memory, according to the data state recorded in the directory information, if the part of the data stored in the second memory is the latest data, the second home agent sends the latest part of the data to the first cache, Otherwise, search for the cache with the latest part of the data, and send the part of the data in the cache with the latest part of the data to the first cache.

In a second possible implementation solution of the second aspect, providing the latest first part of data to the first cache; and then respectively providing the latest rest of the data to the first cache, specifically includes: Send query requests for the first part of data to all the caches of , and send the first part of data in the cache with the latest first part of data to the first cache; then for the rest of the data: to all caches except the first cache Sending the query request of this part of data sends the data in the cache with the latest part of the data to the first cache.

In a third possible implementation solution of the second aspect, the first part of data is the data to be read.

In a fourth possible implementation solution of the second aspect, the first part of data is greater than or equal to the data to be read and is a minimum integer multiple of 8 bytes; the size of the cache line is 64 bytes.

In the embodiment of the present invention, the data requested by the second request includes at least two parts of data, and the latest first part of data is preferentially returned to the first cache, wherein the first part requests data required by the first core for operation. Therefore, the waiting time of the first core can be reduced.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the embodiments or the description of the prior art. The accompanying drawings in the following description are only some embodiments of the present invention. Additional drawings can also be derived from these drawings.

Fig. 1 is a schematic structural diagram of a CC-NUMA embodiment of the present invention;

Fig. 2 is a flowchart of an embodiment of the data processing method of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in FIG. 1 , the CC-NUMA system involved in this embodiment is composed of multiple processors and memory. The processor is, for example, a CPU. The interior of the processor includes a core, a cache, a home agent, and a decoder. The cache is connected to the kernel, home agent, and address decoder respectively. The home agent can also be called a memory home agent, which is used to manage the memory directly connected to the CPU. If other CPUs want to access the memory of this CPU, it needs to be relayed by the memory of this CPU.

Each processor is mounted with memory, the home agent is connected to the mounted memory, and the memory is used to store data. The core is the core component of the processor, has computing power, can run programs, and is the demand side of data. The cache holds temporary data for use by the kernel. The kernel accesses cache faster than it can access memory. The home agent can read and write the mounted memory data. The address decoder records the corresponding relationship between the address and the home agent. When the address of a piece of data is known, the address decoder can be used to query the corresponding home agent, and the memory stored in the home agent has this The data represented by the address. The memory mounted by the processor means that it is directly connected and can read data from it. Optionally, the mounted memory can also be managed. The memory is, for example, random-access memory (RAM).

Multiple processors can be connected using a bus, such as the QuickPath Interconnect (QPI) bus used by Intel Corporation's X86 processors. Through the bus, a processor can indirectly access the memory mounted by other processors. Processors access directly mounted memory faster, while accessing memory mounted by other processors is slower.

In the architecture of FIG. 1 , the first processor includes a first core, a first cache, a first address decoder, and a first home agent, and the first home agent is connected to a first memory. The second processor includes a second core, a second cache, a second address decoder, and a second home agent, and the second home agent is connected to a second memory. The cache can access the home agents of other processors through the QPI bus. The third processor includes a third processor core, a third processor cache, a third processor address decoder, and a third processor home agent, and the third processor home agent is connected to the third processor memory.

FIG. 1 is just an example, and in other embodiments, there may be more processors, such as 4 or 8 or even more. When the number of processors is large, a relay can be set between the processors.

A data processing method according to an embodiment of the present invention will be described in detail below.

In step 21, the first core sends a data read request to the first cache. In this embodiment, the data required by the first core is referred to as data to be read. The data requirements of the first core come from the programs it runs. The read request carries the address of the data to be read. The requested data is smaller than the cacheline size. In this embodiment, this request is referred to as the first request.

Usually, the first kernel is for the purpose of running the program and needs to use the data to be read. In this embodiment, the data to be read is smaller than the cache line data. For example, the data to be read is 8 bytes (Byte), and the size of a cache line (cacheline) is 64 bytes. The amount of data requested by the first request is 8 bytes.

Step 22, the first cache uses the address of the data to be read to query whether the first cache stores the data to be read. If there is, the data to be read is directly returned to the first kernel, and the method ends. If not, an inquiry request is sent to the first address decoder, and step 23 is entered.

In step 23, the first cache queries the home agent corresponding to the address by using the first address decoder. And send the second read request to the queried home agent through the QPI bus. In this embodiment, it is assumed that the home agent corresponding to the address is the second home agent in FIG. 1 . The second home agent manages memory directly connected to the second CPU.

The data requested by the second request includes several parts, and the sum of the sizes of these parts of data is equal to the size of the cache line. Wherein, the first part includes the data to be read. Since the sum of the sizes of these parts of data is equal to the size of the cache line, it is compatible with existing designs.

In this embodiment, the first part of data includes the data requested by the first request, and is a multiple of 8 bytes, such as the smallest multiple. If the data requested by the first request does not exceed 8 bytes, the first part of the data is 8 bytes; if the first part of the data is greater than 8 bytes but not more than 16 bytes, the data of the first part of the data is 16 bytes; And so on.

Subtract the length of the first part of data from the size of the cache line to get the length of the rest of the data. Example 1: It is divided into two parts. The first part of data is 8 bytes, and the length of the cache line is 64 bytes. Then the length of the second part of data is 56 bytes. Example 2: Each part is 8 bytes, and the cache line length is 64 bytes, then there are 8 parts in total including the first part.

In other embodiments, the length of the first part of data may also be kept the same as that of the data to be read.

However, in the prior art, in the request sent by the first cache to the second home agent, the requested data volume is a whole, not divided into two parts, and its size is the same as the cache line, which is also 64 bytes.

The first address decoder is stored with an address mapping table, and the address mapping table records the mapping relationship between the address of the data and the storage location of the data. Specifically, what is stored is the mapping relationship between the address and the home agent, and the memory directly mounted by the home agent stores data corresponding to the address.

Step 24, after receiving the second request, the second home agent reads the directory information of the first part of data from the memory 2 mounted on it. According to the data status recorded in the directory information, the latest first part of data is provided to the first cache. Then, the home agent 2 provides the latest rest data to the first cache according to the directory information of each rest data.

The addresses of these partial data in the second memory are adjacent. The second home agent gives priority to providing the latest data of the first part, and then provides the latest data of the remaining parts.

Each part of data corresponds to an address segment in the memory, and these address segments can be spliced into a continuous address segment.

The first part of the data is stored in the second memory, but may be an earlier version of the data rather than the latest first part of the data. For example, if the first part of data in the second memory is read and modified by other processors, then the latest first part of data will exist in the cache memory of other processors. The second home agent provides the latest first part of the data to the cache in the following two ways.

(1) If the latest first part of data is stored in the second memory, the second home agent directly reads the latest first part of data from the second memory, and then the second home agent sends the data to the first through the QPI bus cache.

(2) If the latest first part of data is not stored in the second memory, it means that the latest first part of data is stored in the cache of other processors. Then the second home agent queries the ID of the cache that has the latest first part of the data, and sends an instruction to this cache. There are three optional instructions, which are described below. In this embodiment, assuming that the cache with the latest first part of data is the third cache of the third processor, the scheme of sending the first part of data in the third cache to the first cache is as follows:

(2.1) Instruct the third cache to send the latest first part of data to the first cache.

(2.2) Instruct the third cache to send the latest first part of data to the second home agent, and the second home agent caches the latest pending data in the second memory, and sends the latest first part of data to the first cache.

(2.3) It is equivalent to the combination of the first two instructions, which not only instructs the third cache to send the latest first part of data to the first cache, but also instructs the third cache to send the latest first part of data to the second home agent, and the second home agent The agent caches the latest pending data in the second memory.

In general, there are directories recorded in the home agent. The second home agent uses the partial address of the first part of the data as a label, and queries the status bit and the storage location of the first part of the data in the directory. Therefore, it can be confirmed whether the latest first part of data is stored in the second memory; and it can be confirmed that if the latest first part of data is not stored in the second memory, there is a cache of the latest first part of data stored.

For example, whether the data recorded in the directory is in M (modified, modified state), E (Exclusive, exclusive state), S (Share, shared state), I (Invalid, invalid state) or A (Any/Unknown, arbitrary state/unknown state) and other states.

For example: the data in the M state is dirty (dirty), indicating that the data to be read has been modified and has not been written back to the memory, so it is inconsistent with the memory. Therefore, what is stored in the second memory is not the latest data to be read. The data in the E state is clean, and other caches are not aligned and modified, so they are consistent with the memory. The latest data to be read is stored in the memory. Other states will not be described in detail.

Also, in some cases, the state of the directory record in the home agent may be inaccurate. For example, it is recorded that a certain piece of data in the cache of a certain processor is in the E state, but it has actually been downgraded to the S state but its home agent has not been notified in the future. Therefore, sending a message to the home agent of each processor to query the actual state according to the directory is a common action in maintaining cache consistency. Because of this, an optional solution is: even if the directory confirms that the latest data to be read is stored in the memory, the method (2) can also be used to provide a local solution to query the caches of other processors for the latest data to be read data.

Also, it is possible that there is no directory in the home agent, in which case all other caches can be queried. That is to say, when there is a directory, each other cache recorded in the directory is unknown. Other caches refer to caches other than the originator, and the originator is the first cache in this embodiment.

The above describes how to obtain the latest first part data. For the rest of the parts, the scheme of obtaining the latest data is similar, so it will not be described in detail here.

The first part of the latest data is given priority here. It does not mean that the latest data of the first step must be queried and sent to the first core before starting to search for the latest data of the remaining parts. This means that in each period, when there is a conflict between providing the latest first part of data and providing the latest other part of data, the first part of data will be processed first. In other words, if the efficiency of providing the latest first part of data is affected during the process of providing any of the latest other parts of data, the latest first part of data is given priority.

It can be seen from this step that in this embodiment, the second home agent will give priority to the first part of the data to the first cache; and then provide the rest of the data. Therefore, the first part of data can reach the first cache faster. The rest of the data does not have a high timeliness requirement, so it can be delayed to arrive at the first cache and temporarily stored in the first cache for future use. The sum of these parts of data is the same as the data finally obtained by the first cache in the prior art. However, in the prior art, the speed of data to be read to the first cache is too slow. However, after the present invention is divided into several parts, the first part of data where the data to be read is located arrives at the first cache first, reducing the waiting time of the first cache, thereby reducing the waiting time of the first core.

Step 25, the first cache receives the latest first part of data, extracts the latest data to be read from it and sends it to the first core, and temporarily stores the latest first part of data. The first cache receives the latest rest of the data, and temporarily stores the latest rest of the data.

After the first core receives the latest data to be read, it can use this part of the data to continue running the program.

Applying the embodiment of the present invention, first check the first part of data (for example, 8 bits), and then check the state of the rest of the byte data, which has certain benefits for avoiding complex conflict scenarios. For example, if the first part of data is shared state, and some of the remaining bytes are modified state, then the entire 64byte is modified state. Then the first part of data can be directly returned from the second processor to the requester (the first cache), without sending any data to other processors. On the other hand, when the home agents of multiple processors request data at the same address at the same time, conflicts are likely to occur. The resolution of conflict scenarios is the most complex and time-consuming scenario in cache coherence protocol design. The granularity of data is reduced from 64 bytes to 8 bytes, which can reduce the probability of conflict; in order to ensure the cache hit rate, the present invention is compatible with the design of 64 bytes, and finally the data cached in the first cache is still Same as the prior art, it is 64 bytes, that is to say, consistent access to 64-byte data is finally completed.

In step 25, the data sent from the first cache to the first core in the embodiment of the present invention is the data actually needed by the first core. However, in the prior art, even if the data required by the first core is less than 64 bytes, what the first cache sends to the first core is always 64 bytes of data. Therefore, in the prior art, the first cache sends more data to the first cache, and the first core needs to select actually required data from it, which increases the complexity of the system.

In step 25, "the first cache receives the latest first part of data, extracts the latest data to be read from it and sends it to the first core" can also have an alternative method, that is, the first cache does not extract the latest data to be read, and directly transfers the first part of the data to the first core. Part of the data is sent to the first core. After the first core receives it, it extracts the latest data to be read from it.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. a data processing method, it is applied to buffer consistency nonuniform memory access CC-NUMA system, CC-NUMA includes first processor and the second processor, described first processor and described second processor are connected by bus, and described first processor includes the first kernel, the first buffer memory and the first decoder；Described second processor includes the second home agent, the second buffer memory, described second home agent and the second Memory linkage, it is characterised in that including:

First kernel sends the first request, and the address of the data that continue is carried in described first request；

Described first buffer memory receives described first request, from described first decoder, inquire described address point to described second internal memory, second request that sends is to described second home agent, described second asks requested data to include at least two parts data, Part I continues data described in including, and the total size of described at least two parts data is equal to the size of cache lines；

After described second home agent receives described second request, it is provided that up-to-date Part I data give described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, described in include at least that two parts data address in described second internal memory is adjacent；

Described first buffer memory obtain from described Part I data described in the Data Concurrent that continues give described first core and described at least two parts data up-to-date described in buffer memory.

2. method according to claim 1, it is characterised in that provide up-to-date Part I data to described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, specifically include:

The directory information of Part I data is read from described second internal memory, data mode according to directory information record, if the second internal memory stored Part I data are up-to-date Part I data, then described second home agent sends up-to-date Part I data to described first buffer memory, otherwise, search the buffer memory having up-to-date Part I data, the Part I data in the buffer memory having up-to-date Part I data are sent to described first buffer memory；

Then for all the other each several part data: read directory information from described second internal memory, data mode according to directory information record, if the second internal memory these part data stored are up-to-date data, then described second home agent sends these up-to-date part data to described first buffer memory, otherwise, search the buffer memory having these up-to-date part data, these part data in the buffer memory having these up-to-date part data are sent to described first buffer memory.

3. method according to claim 1, it is characterised in that provide up-to-date Part I data to described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, specifically include:

Send the inquiry request of Part I data to all buffer memorys except the first buffer memory, the Part I data in the buffer memory having up-to-date Part I data are sent to described first buffer memory；

Then for all the other each several part data: send the inquiry request of these part data to all buffer memorys except the first buffer memory, these data in the buffer memory having these up-to-date part data are sent to described first buffer memory.

4. the method according to claim 1,2 or 3, it is characterised in that:

Described Part I data continue data described in being.

5. the method according to claim 1,2 or 3, it is characterised in that:

Described Part I data are be more than or equal to the described data that continue, and are the smallest positive integrals times of 8 bytes；The size of described cache lines is 64 bytes.

6. a data processing method, it is applied to buffer consistency nonuniform memory access CC-NUMA system, CC-NUMA includes first processor and the second processor, described first processor and described second processor are connected by bus, and described first processor includes the first kernel, the first buffer memory and the first decoder；Described second processor includes the second home agent, the second buffer memory, described second home agent and the second Memory linkage, it is characterised in that including:

First kernel sends the first request, and the address of the data that continue is carried in described first request；

Described first buffer memory receives described first request, from described first decoder, inquire described address point to described second internal memory, second request that sends is to described second home agent, described second asks requested data to include at least two parts data, Part I continues data described in including, and the total size of described at least two parts data is equal to the size of cache lines；

After described second home agent receives described second request, it is provided that up-to-date Part I data give described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, described in include at least that two parts data address in described second internal memory is adjacent；

Described up-to-date Part I data are sent to described first core and described at least two parts data up-to-date described in buffer memory by described first buffer memory.

7. method according to claim 6, it is characterised in that provide up-to-date Part I data to described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, specifically include:

The directory information of Part I data is read from described second internal memory, data mode according to directory information record, if the second internal memory stored Part I data are up-to-date Part I data, then described second home agent sends up-to-date Part I data to described first buffer memory, otherwise, search the buffer memory having up-to-date Part I data, the Part I data in the buffer memory having up-to-date Part I data are sent to described first buffer memory；

Then for all the other each several part data: read directory information from described second internal memory, data mode according to directory information record, if the second internal memory these part data stored are up-to-date data, then described second home agent sends these up-to-date part data to described first buffer memory, otherwise, search the buffer memory having these up-to-date part data, these part data in the buffer memory having these up-to-date part data are sent to described first buffer memory.

8. method according to claim 6, it is characterised in that provide up-to-date Part I data to described first buffer memory；Then provide up-to-date remainder data to described first buffer memory respectively, specifically include:

Send the inquiry request of Part I data to all buffer memorys except the first buffer memory, the Part I data in the buffer memory having up-to-date Part I data are sent to described first buffer memory；

Then for all the other each several part data: send the inquiry request of these part data to all buffer memorys except the first buffer memory, these data in the buffer memory having these up-to-date part data are sent to described first buffer memory.

9. the method according to claim 6,7 or 8, it is characterised in that:

Described Part I data continue data described in being.

10. the method according to claim 6,7 or 8, it is characterised in that:

Described Part I data are be more than or equal to the described data that continue, and are the smallest positive integrals times of 8 bytes；The size of described cache lines is 64 bytes.