CN105793927A - Management of data storage in analog memory cells using a non-integer number of bits per cell - Google Patents

Management of data storage in analog memory cells using a non-integer number of bits per cell Download PDF

Info

Publication number
CN105793927A
CN105793927A CN201480065225.3A CN201480065225A CN105793927A CN 105793927 A CN105793927 A CN 105793927A CN 201480065225 A CN201480065225 A CN 201480065225A CN 105793927 A CN105793927 A CN 105793927A
Authority
CN
China
Prior art keywords
data
read
reversion
unit
coded data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480065225.3A
Other languages
Chinese (zh)
Other versions
CN105793927B (en
Inventor
M·安霍尔特
N·萨莫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of CN105793927A publication Critical patent/CN105793927A/en
Application granted granted Critical
Publication of CN105793927B publication Critical patent/CN105793927B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Description

Data storage in the analog memory unit of every unit use non-integer number position Management
Technical field
Present invention relates generally to data storage, and in particular relate to for storing data in analog memory unit Method and system.
Background technology
Polytype memory devices such as flash memories uses analog memory cellular array to store data. The quantity of each analog memory unit storage analogue value, this analogue value is also called storage value, such as electric charge or voltage.This simulation Value expression is stored in the information in this unit.Such as, in flash memories, each analog memory unit keeps a certain amount of Electric charge.The scope of the possible analogue value is typically divided into some intervals, and each interval corresponds to one or more data bit value.Pass through Write writes data into analog memory unit with desired one or more corresponding nominal analog values.
Commonly referred to some memory devices of single stage unit (SLC) equipment store single letter in each memory cell Breath position, i.e. can be programmed each memory cell using two possible programming levels.Commonly referred to multi-level unit (MLC) higher density equipment every memory cell storage two or the more multidigit of equipment, i.e. it can be programmed to employing many In two possible programming levels.Such as, three grades of unit (TLC) equipment use eight programming levels to make every unit store three.
Such as, in IEEE collection of thesis volume 91 the 4th phase the 489-502 page in April, 2003, deliver Bez et al. Describing flash memory device in " Introduction to Flash Memory ", the document is incorporated by reference this Literary composition.Such as, the New York city in New York state hold 1996 IEEE International Electro equipment meeting (IEDM) paper Concentrate the 169-172 page, Eitan et al. " the Multilevel Flash Cells and their Trade-delivered Offs " in describe multi-level flash cell and equipment, the document is incorporated by reference herein.This paper compares several multistage Flash cell, the most altogether ground connection, DINOR, AND, NOR and NAND cell.
The solid condition apparatus in 1999 that in JIUYUE, 1999 21-24 day holds at the Tokyo of Japan grind with material (SSDM) world Beg for can collection of thesis in the 522-524 page, by Eitan et al. at " Can NROM, a 2-bit, Trapping Storage NVM Cell,Give a Real Challenge to Floating Gate Cells？The referred to as read-only storage of nitride is described in " The another type of analog memory unit of device (NROM), this paper is incorporated by reference herein.3-7 day in February, 2002 Paper at the IEEE ISSCCs in 2002 (ISSCC 2002) that the San Francisco of California holds Concentrate the 100-101 page, by Maayan et al. at " A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Rate " in also illustrate NROM-cell, this paper is incorporated by reference herein.Analog memory unit Other exemplary types are floating boom (FG) unit, ferroelectric RAM (FRAM) unit, magnetic ram (MRAM) unit, charge-trapping flash memory And phase transformation RAM (PRAM, also referred to as phase transition storage-PCM) unit (CTF).Such as, 16-19 day in May, 2004 is Serbia's In the collection of thesis of the 24th microelectronics (MIEL) international conference that Nis and Montenegro holds volume 1 the 377-384 page, By Kim and Koh described in " Future Memory Technology including Emerging New Memories " FRAM, MRAM and PRAM cell, this paper is incorporated by reference herein.
Some storage schemes have the density of the position of non-integer number to store data with each memory cell.Such as, United States Patent (USP) 7,071,849 describe allow the increment of product instead of chien shih every location mode number little to 1 fractional bits system, By quoting, the disclosure of which is expressly incorporated herein.Owing to the status number of every unit is not the integral number power of 2, thus often single The figure place of unit takes fractional value.Generally in units of word, unit is decoded, and can optimize by adjusting word width System effectiveness.
And for example, United States Patent (USP) 6,646,913 describe a kind of for having the storage formed by multiple memory cells The method stored in the multi-stage non-volatile memory of device array and read data, by quoting by the disclosure of which also Enter herein.Each in this memory cell stores a number of position, and this quantity is the integral number power of non-2.By this Mode, can store a data byte in the memory cell of non-integer number.This management method includes by advance If the neighbor memory cell of quantity is programmed and stores the data word that formed by multiple bytes within the same clock cycle.Logical Cross the data word that reading is stored within the same clock cycle and perform reading.
Method described in United States Patent (USP) 7,167,109 allows little at the increment of product instead of chien shih every location mode number N To 1, by quoting, the disclosure of which is expressly incorporated herein.It is no longer the integral number power of 2 due to N, thus b takes fractional value, Thus obtained fractional bits system.In fractional bits system, in units of word, unit is decoded.Can be by adjusting word width Degree optimizes system effectiveness.Mixing N metasystem can be used to improve fabrication yield and Durability.
United States Patent (USP) 7,742,335 describes for operating the method for multi-stage non-volatile memory unit, equipment, module And system, by quoting, the disclosure of which is expressly incorporated herein.One method embodiment includes to coupleding to row selection The programming state of the first quantity that first module can be programmed for by the first module distribution of line.The method also includes to coupleding to The programming state of the second quantity that second unit can be programmed for by the second unit distribution of row select line, wherein the second quantity Programming state is more than the programming state of the first quantity.The method is included in the programming state that second unit is programmed for the second quantity In one before first module is programmed in the programming state of the first quantity one.
United States Patent (USP) 7,848,142 describes the method for being programmed memory cell, equipment, module and is System, is programmed the data mode that can include storage with integer the position in expression storage stack unit to memory cell Corresponding electric charge.Memory cell is programmed being included in the element memory storage electric charge of this group, and wherein electric charge corresponds to Programming state, wherein programming state represents the position of mark quantity, and wherein programming state represents the numeral of data mode, this number Word is represented by the counting as integer of the round-up with N as radix, and wherein N is equal to 2B, and wherein B is equal to what programming state represented The mark quantity of position.
United States Patent (USP) 7,420,841 describe a kind of memory devices and a kind of method operating memory devices, pass through Quote and the disclosure of which is expressly incorporated herein.In an embodiment of this invention, memory devices includes multiple many Level memory cell, each in multiple multilevel memory cells has quantity m level, and this quantity m is not with 2nCoupling, wherein N is nonzero integer, and this memory devices also include for by least two in memory cell be used for write and read The level of extract operation is merged into one group of merging phase and for 2 to this group merging phase of major generalnThe subset of individual combination is converted into n The circuit of individual two-stage data bit or equipment.
Summary of the invention
One embodiment of invention described herein provides a kind of method for data storage, including by profit With at least outer code and ISN data encoded and optionally made before the data of coding are stored in memory cell Coding data reversal and store data in storage stack unit.The data of coding are read from memory cell.To institute The coded data application inner decoding read, to produce decoded result.According to the decoded result of ISN, make conditionally to be read At least part of reversion of data.
In some embodiments, ISN includes that the reversion of valid code word produces the generation of another valid code word the most all the time Code, and apply inner decoding include in the coded data read and the inverted version of coded data read at least One is decoded.In other embodiments, application inner decoding includes the coded data read and the volume read Code data both inverted version be decoded, and conditionally reversion read data at least partly include only exist The decoded result of the coded data that the decoded result of inverted version is error-free and is read non-error-free time make read data At least partly reversion.
In other embodiments, storage data include storing whether the data that represent storage relevant with data receive The reversion instruction of reversion, reads coded data and includes reversion instruction is read out and is decoded, and apply inner decoding to include Only to the coded data decoding read or only the inverted version of the coded data read is decoded according to reversion instruction.
In one embodiment, conditionally reversion read data be at least partially included in read coding When the decoded result of data and reversion instruction contradiction, the instruction data that can not decide whether to being read invert.Separately In one embodiment, ISN includes error detection code, and at least part of bag of the data that reversion is read conditionally Include at decoded result equal to making at least part of of read data invert during to the result of complete 1 word application inner decoding, and At least part of reversion of read data is not made when decoded result is error-free.
In another embodiment, conditionally reversion read data be at least partially included in read volume When the decoded result of code data and the decoded result contradiction of the inverted version of coded data read, instruction can not decide whether The data read are inverted.
According to one embodiment of the invention, additionally provide and include that (this memorizer includes memory cell battle array to memorizer Row) and the device of storage circuit.Storage circuit is configured to utilize at least that outer code and ISN be to data encoding and optionally The data reversal of coding was made to store data into storage stack before the data of coding being stored in memory cell In unit, read the data of coding from memory cell, to the coded data application inner decoding read to produce decoding knot Really, and according to the decoded result of ISN at least part of of read data is inverted conditionally.
According to one embodiment of the invention, additionally provide a kind of method for data storage, be included in the first volume First data are stored one group deposit by the memory cell in this group is programmed to one group of initial programming level by the journey stage In storage unit.In following the second programming phases after the first programming phases closely, program rank by identifying in this group first It is programmed to the memory cell of the corresponding stage of the predefined parton concentration of initial programming level in Duan and the second data are stored In this group.Only the memory cell identified is used the second data programming, thus in the memory cell that will be identified At least some is set to be different from the one or more additional programming level of initial programming level.By only reading the part of the first data Subset and identify the memory cell that the second data are programmed into.The second data are read from the memory cell identified.
In some embodiments, store the first data and include storing multiple data page, and recognition memory unit bag Include the part subset only reading multiple pages.In other embodiments, store the first data to include storing least significant bit (LSB) Page and central authorities' significance bit (CSB) page, and store the second data and include storing highest significant position (MSB) page, and identify storage Device unit includes only reading LSB page or CSB page.In other embodiments, read LSB page or CSB page to include using single reading Take order and read LSB page or CSB page.In other embodiments, read the second data include using two read thresholds come from The memory cell identified reads MSB page.
According to one embodiment of the invention, additionally provide and include that (this memorizer includes memory cell battle array to memorizer Row) and the device for data storage of storage circuit.Storage circuit is configured to program the memory cell in group First data are stored in this group memory cell in the first programming phases to one group of initial programming level, and following closely In second programming phases of the first programming phases, it is programmed to initial programming level by identifying in this group in the first programming phases The memory cell of the corresponding stage that predefined parton is concentrated, and only use the second data to enter the memory cell identified Row programming, thus at least some in the memory cell that will be identified sets to the most different from initial programming level one or more Second data are thus stored in this group by additional programming level, identify second by only reading the part subset of the first data The memory cell that data are programmed into, and read the second data from the memory cell identified.
According to one embodiment of the invention, additionally provide a kind of method for data storage, be included in one group and deposit Storage unit identifies in this group and will be programmed to the memory cell of the anticipated number of given programming state.According to being programmed The memory cell of anticipated number to given programming state set between given programming state and adjacent program state every From degree.Use the isolation set that the memory cell in this group is programmed.
In some embodiments, by forming adjacent programmed shape according to predefined division than being allocated to delimit the organizational structure journey state State, and identify that the memory cell of anticipated number includes using division than estimating the memorizer being programmed to given programming level The quantity of unit.In other embodiments, it is programmed memory cell including being set to memory cell multiple depositing Reservoir state so that the corresponding isolation between adjacent memory state is heterogeneous.
According to one embodiment of the invention, additionally provide and include that (this memorizer includes memory cell battle array to memorizer Row) and the device for data storage of storage circuit.Storage circuit is configured to identify this group in storage stack unit The memory cell of the middle anticipated number that will be programmed to given programming state, foundation will be programmed to the pre-of given programming state The memory cell of issue amount sets the isolation between given programming state and adjacent program state, and uses setting Memory cell in this group is programmed by isolation.
Additionally provide a kind of method for data storage according to one embodiment of the invention, be included in the first programming First data are stored many by the memory cell in each group is programmed to corresponding set of initial programming level by the stage In group memory cell.In following the second programming phases after the first programming phases closely, by identify in each group the One programming phases is programmed to initial programming level predefined parton concentrate corresponding stage available memory cells and incite somebody to action Second data store in multiple groups.Only the second data are used to be programmed the available memory cells identified so that from Fixed position in groups of memory cells starts to be programmed, second data of given group regardless of available memory cells The change of actual quantity how, is thus set at least some memory cell in available memory cells be different from initially The one or more additional programming level of programming level.
In some embodiments, the method includes that the memory cell at by access fixed position reads given group The second data.In other embodiments, the second data include multiple data word, and the size of each data word is more than many The actual quantity of the available cell in often group memory cell in group memory element.In other embodiments, second is read Data include by only reading the first number from one or more groups memory cell within it programmed data-oriented word According to and read the data-oriented word in multiple data word.
In one embodiment, the method is included in the programming using the second data to be done the available cell identified One or more leaving in identified available cell when not being programmed, uses the 3rd data to unprogrammed memorizer list Unit is programmed.In another embodiment, the second data include multiple data word, and the data word size of this data word does not surpasses The too much quantity of the available memory cells in the often group memory cell in group memory cell.
According to one embodiment of the invention, additionally provide and include that (this memorizer includes memory cell battle array to memorizer Row) and the device for data storage of storage circuit.Storage circuit is configured to compile the memory cell in often group First data are stored in multi-bank memory unit to corresponding one group of initial programming level in the first programming phases by journey, and And in the second programming phases following the first programming phases closely, at the beginning of identifying and often group being programmed in the first programming phases The available memory cells of the corresponding stage that the predefined parton of the programming level that begins is concentrated, and only to the available memory identified Unit uses the second data programming so that the fixed position from groups of memory cells starts to compile second data of given group Journey, regardless of available memory cells actual quantity change how, in order to by least some in available memory cells Available memory cells is set to be different from the one or more additional programming level of initial programming level, thus by the second data storage In the plurality of group.
From below the detailed description of embodiment of the present invention be will be more fully understood the present invention in conjunction with accompanying drawing, attached In figure:
Accompanying drawing explanation
Fig. 1 is the block diagram schematically showing the accumulator system according to one embodiment of the invention；
Fig. 2 is the diagram schematically showing the data code word according to one embodiment of the invention；
Fig. 3 A and Fig. 3 B shows according to embodiment of the present invention for using non-integer number position at every unit The diagram of the programming level distribution of storage data；
Fig. 4 A and Fig. 4 B is to schematically show according to embodiment of the present invention in available memory cells Diagram according to two kinds of technology of known side-play amount storage data；
Fig. 5 be schematically show according to one embodiment of the invention in available memory cells according to The flow chart of the method for known side-play amount write data；
Fig. 6 is to schematically show according to one embodiment of the invention for reading in available memory cells The flow chart of the method for the data write according to known side-play amount.
Detailed description of the invention
General introduction
Relative to the situation of employing integer amount, the position of every unit employing non-integer number carries out data storage and can have excellent Gesture, because the programming of the quantity improved or reduce can be respectively adopted in the case of total progression is not limited to the integral number power of 2 Level, it is thus possible to realize the raising of memory density or reliability.
Embodiment of the present invention provide for using non-integer number position to manage data each memory cell The improved method of storage and system.Disclosed embodiment uses several modification of two benches programming scheme.Such as, 2011 The U.S. Patent application 13/192,501 of the assignee being assigned to present patent application that on July 28, in submits to describes this type of The various examples of two benches programming scheme, are expressly incorporated herein the disclosure of which by quoting.In this type of scheme, In one programming phases, memory cell is programmed by the programming level of the integral number power using quantity to be 2.In the second programming phases, The only element memory storage of certain one-level in each one is programmed to the group of one or more selected level in the first phase is additional Position.These unit are suitable to the programming in second stage, and the most also these unit are referred to as " available cell ".
The exact amount of available cell has data dependence, thus is change.Therefore, in some embodiments, Optionally make the data page generation bit flipping (that is, the polarity making position inverts) write in the first phase, to guarantee to have foot The available cell storage second stage data of enough amounts.But, when data stand error correction and/or error detection code, Bit flipping there may be problem because the valid code word now inverted may not or valid code word.Do not ensure the generation of each reversion The example of the code that code word all maps to another valid code word includes cyclic redundancy code (CRC) and Bose-Chaudhuri- Hocquenghem(BCH).In one embodiment, encoding scheme uses ISN and outer code.For example, it is possible to by ISN (example As, CRC or BCH) it is used together with outer code (such as, low-density checksum-LDPC), in order to identify and iteration LDPC is decoded Device terminates in advance or to solve the condition of capture collection circumstances.In some embodiments, by corresponding reversion position instruction institute The polarity of code word of storage, this reversion position generally (but not necessarily) is embedded in code word.
In one embodiment, ISN includes error detection code, and such as CRC code is (or in fault detection mode BCH code).Data are read, to outer-decoder, and to the data read and the identical data through inverting from memory cell CRC is all applied to decode (likely parallel with outer decoder).Based on whether have arbitrary CRC decoding instruction do not find mistake (and It is possibly based on reversion position) determine polarity.In another embodiment, according to the pole of the reversion position in the data read Property only apply CRC decoding.In another embodiment, by the result of CRC decoder and zero word (instruction is without reversion) and Word equal to the CRC being applied to complete 1 word (instruction once applied reversion) all compares.In another embodiment, ISN Including error correcting code, such as BCH code (being configured to error correction operations pattern), and to the data read with through reversion Identical data both of which application decoder.Whether the result according to any decoder in two BCH decoders is decodable, I.e., if the error-free polarity determining code word.
In some embodiments, in (the above-mentioned two benches encoding scheme) first stage, each memory cell is entered Row programming, to use an initial level in four initial level, two initial level in four initial level are selected for second Stage.In second stage, the only unit to the selected level being programmed in two selected levels writes additional Position.Thus, the unit occupation rate of the level selected in second stage is about double division, thus has obtained total of six Level, wherein has four levels to be about being occupied by half.Due to according to this scheme, unit has half store 3/mono- Unit, and second half 2/unit of storage, thus the storage average of this equipment is 2.5/unit.
In the disclosed embodiment using above-mentioned six grades of programming schemes, for three bit combinations are mapped to each programming The dedicated alternative of level designed to be able to without identifying in the case of reading the total data that programs in the first phase the The unit of programming in two-stage.In one embodiment, by utilizing two read thresholds only to read central authorities' significance bit (CSB) Page and the identification of performance element.In another embodiment, the identification of unit relates to the use of single read threshold and only reads Low order (LSB) page.Thus disclosed technology avoids and reads and the unnecessary operation of decoding.
In some embodiments, uniform level will not be taked to be spaced, but unit occupation rate based on each grade will determine Threshold voltage interval between programming level.In this type of embodiment, by the interval between adjacent level low for occupation rate or isolation The interval that is set as between the adjacent level higher than occupation rate of degree closer to.It is for instance possible to use this type of non-uniform spacing realizes Cross over the uniform read error probability of all levels.
In some embodiments, the word (such as, the N position code word of the data of coding) with the size of N position is write In the group of N unit, this group is also called unit group.In this type of embodiment, before storage, application is optional in the first phase Bit reversal, to guarantee to have enough level occupation rate (that is, sufficient amount of available cell) in second stage, such as institute above State.If additionally three levels (coming from four levels of first stage employing) are divided in second stage, then each In unit group, the unit of only about 3/4 can be used for storing extra order.In some embodiments, can use four unit groups Unit stores three N position code words.Each code word is divided into two sections, fixing inclined according to some in available cell Two sections are written in two independent unit groups by shifting amount.
In an exemplary embodiment, use up all of available cell and sequentially write the section of code word.Real at this Executing in scheme, the side-play amount write between the available cell of each section has data dependence.In order to read code word, pass through At least unit group from any section not writing respective section reads data to estimate the side-play amount of respective section.
In other embodiments, the available cell in each unit group writes generation according to known constant offset amount The section of code word.By utilizing constant offset amount, the section of given code word read only need to be from writing this code word The unit group of section reads data.Afterwards, the section read is merged, to recover original code word.Thus employing known offset Amount is it can be avoided that read and the unnecessary operation of decoding.
In other embodiments, the size of data in second stage is selected, in order to minimum available in engagement unit group Element number, and thus simplify digital independent and write operation.But, in this type of embodiment, the first programming phases and Two programming phases may need single different encoding schemes, so that whole encoding scheme is more complicated.
System description
Fig. 1 is the block diagram schematically showing the accumulator system 20 according to one embodiment of the invention.System 20 can be used in various host computer system and equipment, are such as used for the equipment that calculates, cell phone or other communication terminals, may move and deposit Memory modules (such as " portable disk " or " flash drive " equipment), solid state hard disc (SSD), digital camera, music and other matchmakers Body player and/or store and retrieve any other system or equipments of data wherein.
System 20 is included in the memory devices 24 storing data in memory cell array 28.Memory array includes many Individual analog memory unit 32.At the linguistic context and in detail in the claims of present patent application, term " analog memory unit " For describing any memory cell of the progressive die analog values keeping physical parameter such as voltage or electric charge.Array 32 can include appointing The solid state analogue memory cell of which kind of class, such as NAND, NOR and charge-trapping flash memory (CTF) flash cell, phase transformation RAM (PRAM, also referred to as phase transition storage (PCM)), nitride ROM (NROM), ferroelectric RAM (FRAM), magnetic ram And/or dynamic ram (DRAM) unit (MRAM).Although embodiment described herein is primarily referred to as analog memory, but Disclosed technology can also be used in combination with other type of memory various.
Store levels of charge in the cells and/or be written to analog voltage or the electric current that unit neutralization reads from unit In the collectively referred to herein as analogue value, storage value or analog storage value.Although embodiment described herein mainly processes threshold value electricity Pressure, but method and system described herein can also be used in combination with the storage value of any other suitable kind.
System 20 is by coming at analog memory with the corresponding programming state of employing (also referred to as programming level) unit programming Unit stores data.Programming level is from selecting the finite aggregate of energy level, and each level is corresponding to a certain nominal storage value. For instance, it is possible to be written in unit come 2 by the nominal storage value that in the nominal storage value possible by four is possible Position/unit MLC is programmed using a kind of possible programming level in four kinds of possible programming levels.Technology described herein The memory density of the main non-integer number position processing each memory cell, i.e. the quantity of programming level not 2 integer Power.
Memory devices 24 includes read/write (R/W) unit 36, and the data stored in memory devices are turned by this read-write cell Change analog storage value into and by they write memory cells 32.In the embodiment of alternative, R/W unit does not perform this Conversion, but it is provided with voltage sample, i.e. the storage value of storage in unit.When reading data from array 28, R/W unit 36 The storage value of memory cell 32 is converted to the numeral sample with one or more integer resolution.Data commonly write In memory cell (this is referred to as the page) in group and read from which.In some embodiments, R/W unit can be by inciting somebody to action One or more negative erasing pulses are applied to unit and wipe one group of unit 32.
Performed to retrieve data in memory devices 24 store data inside with from it by Memory Controller 40.Memorizer controls Device 40 includes the interface 44 for communicating with memory devices 24, processor 48 and error correcting code (ECC) unit 50.Disclosed skill Art can by Memory Controller 40, by R/W unit 36 or both perform.Therefore, under current context, memorizer controls Device 40 and R/W unit 36 is collectively referred to as performing the storage circuit of disclosed technology.
Memory Controller 40 communicate with main frame 52 for receive the data that are stored in memory devices and for Export the data from memory devices retrieval.ECC cell 50 use suitable ECC to data encoding to be stored, and to from depositing The ECC decoding of the data of reservoir retrieval.Can use the ECC of any suitable type, such as, low-density checksum (LDPC), Reed-Solomon (RS) or Bose-Chaudhuri-Hocquenghem (BCH).In some embodiments, entangle except comprising Outside error code, ECC cell 50 also includes another kind (the least) error correcting code or error detection code.May be used for this type of attached The exemplary codes adding code includes the BCH for error correction and the cyclic redundancy code (CRC) for error detection.Coding The output of the ECC cell 50 in direction is also called " code word ".
Hardware can be passed through, such as, use one or more special IC (ASIC) or field programmable gate array (FPGA) Memory Controller 40 is implemented.Alternatively, Memory Controller can include the microprocessor running appropriate software, or firmly Part element and the combination of software element.
The configuration of Fig. 1 is the example system configuration purely illustrated for the reason of clear concept.Can also use any Other suitable memory system configuration.Such as, although the example of Fig. 1 shows single memory equipment, but in alternative In embodiment, Memory Controller 40 can control multiple memory devices 24.For the sake of clarity, omit from accompanying drawing For understanding the nonessential element of the principle of the present invention, the most various interfaces, addressing circuit, timing and ranking circuit and debugging Circuit.
In the example system configuration shown in Fig. 1, memory devices 24 and Memory Controller 40 are as two individually Integrated circuit (IC) realizes.But, in the embodiment of alternative, memory devices and Memory Controller can be integrated into On separate semiconductor module in single multi-chip package (MCP) or SOC(system on a chip) (SoC), and can be mutual by internal bus Even.The most alternatively, partly or entirely may reside in of memory controller circuit is being arranged above with memory array On same module.The most alternatively, some or all functions of Memory Controller 40 can implement and pass through place in software Other elements of reason device or host computer system perform.In some embodiments, main frame 44 and Memory Controller 40 can be same Manufacture on module, or manufacture on the independent module in same equipment packages.
In some embodiments, Memory Controller 40 includes general processor, and it is programmed to carry out this in software Function described in literary composition.Alternatively or in addition software such as can Electronically download to processor by network, or, It can be provided and/or store in non-transient state tangible medium such as magnetic, optics or electronic memory.
In the example arrangement of array 28, memory cell 32 is arranged with the form of multiple row and columns, and each storage Device unit includes floating transistor.The grid of the transistor in every a line is connected by wordline, and the transistor in every string Source electrode is connected by bit line.Under current context, " OK " word is to use according to conventional implication, it is intended that represent by common word line The storage stack unit of feeding, and " arranging " word then represents the storage stack unit fed by common bit lines.Term " OK " and " arranging " does not implies that memory cell has a certain physical orientation relative to memory devices.Memory array is generally drawn It is divided into multiple locked memory pages, i.e. the groups of memory cells being programmed and reading simultaneously.
In some embodiments, storage page is separated into sector.In various manners page can be mapped to wordline. Each wordline can store one or more page.In the given page can be stored all memory cells of wordline or Storage is interior (such as, odd order or the memory cell of even order) to the subset of memory cell.
The generally erasing of implementation unit in the block comprising multiple page.Typical memory devices can include on thousands of The erasing block of ten thousand.In the MLC device of typical every unit two, each erasing block is about 32 wordline, every wordline bag Include several ten thousand unit.Often every wordline of such equipment is divided into page four (odd order/even order unit, unit minimum/the highest Significance bit).In each erasing block has three equipment of every unit of 32 wordline, often erasing block will have page 192, and In every four equipment of unit, every piece will have page 256.Or, it is also possible to use other block size and configurations.Some memorizeies set For including two or more single memory cell arrays, this array is usually referred to as plane.Owing to each plane is in succession There is between write operation a certain " busy " cycle, thus alternately can write data to Different Plane, to improve programming speed Degree.
Data are stored in the case of every unit uses non-integer number position
In the case of every unit uses non-integer number position, store data be equivalent to memory cell is programmed, from And use programming level or the programming state of the integral number power of quantity non-2.In some embodiments, system 20 uses two benches to compile Journey scheme, thus in the case of every unit uses non-integer number position, store data.
In the first phase, memory cell is programmed by the programming level using the quantity of the integral number power of 2.Such as, In TLC equipment, first only with four levels (from eight possible levels), unit is programmed.In second stage, can Only the unit employing extra order of some grade being programmed in the first phase in each grade of first stage is programmed. In eight grades of TLC examples, the first stage level of the programming being selected for use in second stage include one of one group, two or Three levels, thus respectively obtaining sum is five, six or the level of seven.
In second stage, the value (" 0 " or " 1 ") of extra order determines that corresponding unit is to maintain unit in the first phase The programming level being programmed to, is still programmed to the programming level of another the most higher all levels being different from the first stage.Cause And, to carrying out division about half-and-half with the programming level filled to the unit of determined number in the first phase in second stage, It uses similar " 0 " and " 1 " position universality.Such as, at U.S. Patent application 13/192 cited hereinabove, describe in 501 The various examples of such two benches programming scheme.
In some embodiments, data to be programmed include single data page, such as, have orderly position effective The page of property.Storage circuit stores the effectiveness page less than highest significant position (or Must Significant Bit) in the first phase, and And in second stage, only store most effective data page.Such as, in TLC equipment, storage circuit stores the most in the first phase Low order (LSB) and central authorities' significance bit (CSB) page.Afterwards, storage circuit based on the data stored in the first phase the Must Significant Bit (MSB) page is stored during two-stage.Hereafter contact Fig. 3 A and Fig. 3 B is described first stage programming level and second-order Section programming level, level divide and the scheme of bit combination is mapped to the example programming level.
Method for the code word decoding to reversion
When data (such as, MSB data) being programmed in second stage, fill the unit of the programming level that will divide Sum has data dependence, and it may be found that this quantity is inadequate.In some embodiments, optionally it is reversed in The position polarity of the data page of write in one stage, to guarantee that the level divided in second stage is had enough unit fills. Additionally, when data are also encoded by error correction, the conventional decoding of reversal data may be infeasible, because the data after Fan Zhuan Valid code word may not be included.
In order to improve memory reliability, in some embodiments, storage circuit uses suitable encoding scheme to protect institute Data to be programmed, generally implement this encoding scheme by ECC cell 50.
Fig. 2 is the diagram schematically showing the code word 70 according to one embodiment of the invention.Showing at Fig. 2 In example, code word 70 includes data bit 74 (such as, LSB or the CSB data in the first stage), reversion position 78, inner code parity school Test position 82 and Outer code parity checks position 86.In current example, parity check bit 86 includes being applied in the lump by ECC cell 50 Data bit 74, reversion position 78 and the LDPC code of inner code parity checks position 82.Thus, data bit 74, reversion position 78, inner code parity school The set testing position 82 and Outer code parity checks position 86 comprises LDPC code word.Additionally, in the figure 2 example, parity check bit 82 It is applied to data bit 74 and the CRC of reversion position 78 or BCH code including by ECC cell 50.In the configuration described, LDPC outer code Mistake in ISN parity check bit 82 can be corrected, its realization is used ISN terminate ahead of time LDPC decoding iteration or Person uses ISN to eliminate the residual error occurred after following outer decoding closely, as mentioned below.
The configuration of Fig. 2 is the exemplary configuration purely illustrated for the reason of clear concept, and can also use it The configuration that he is suitable.For example, it is also possible to use other suitable codes, encoding scheme and size and the Bu Tong unit of code word 70 Sequence.
In some embodiments, such as can be by ISN 82 (such as, including CRC or BCH code) and LDPC code 86 It is used together, thus identifies the condition terminated ahead of time when to LDPC code word iterative decoding, or detect and alleviate LDPC solution Capture collection circumstances in code device.And for example, when ISN includes error correcting code (such as, BCH), can be used for code 82 alleviating The mistake (" error floor ") of residual at the output of LDPC decoder.The U.S. Patent application 12/ that on October 28th, 2010 submits to 913,815 describe several method terminated ahead of time during performing iterative decoding, and this application is transferred to this patent Shen Assignee and the disclosure of which please are incorporated herein by.
In some embodiments, reversion position 78 is initially set as " 0 " by storage circuit, and optionally makes whole code There is reversion or bit flipping in word 70, to guarantee that having enough levels done by unit in the level of to be marked point fills, as above Literary composition is described.When reading data, storage circuit is from array 28 retrieval coding word, and uses ECC cell 50 application decoder.If solved Bit reversal 78 after Ma is equal to " 1 ", then the data bit of code word is overturn before being delivered on main frame by storage circuit in place 74 Return.But, in order to make decoding properly functioning, the code word after each reversion all should also include valid code word.In other words, Each valid code word of encoding scheme all should map to another valid code word by reversion.By comprising the even-odd check of code Every a line of matrix has the requirement of even number weighting (that is, this row includes even number non-zero entry), it is possible to by LDPC Code Design be Support such characteristic, i.e. for each valid code word, bit flipping will produce another valid code word.But, this characteristic exists CRC code and BCH code are difficult to or can not realize.In following description, it is assumed that outer code is (such as, LDPC) characteristic of the effectiveness of above-mentioned reversion valid code word is supported.
We will describe several for decoding code word 70 and determining that this code word is subject to the most before storing now Reversion the method therefore should being inverted back.In disclosed embodiment, ISN 82 includes not guaranteeing accordingly The code of the effectiveness of bit flipping code word.In following description, X represents CRC or BCH code word.Such as, X can wrap Include data bit 74, reversion position 78 and parity check bit 82.Additionally, make～X represents the bit flipping version of X, and CRC (X) or BCH (X) decoding operation is represented.And, ZEROS and ONES represents " 0 " and complete " 1 " bit sequence entirely respectively.Linguistic context in present patent application Descend and in detail in the claims, inner decoding had both referred to error detection code, referred to again error correcting code.
First description ISN 82 is included the several embodiments of error detection code by us.Although described description mainly relates to And the embodiment of employing CRC coding, but any other suitable error detection code can also be used, such as, it is configured For the BCH code of operation under fault detection mode.According to the characteristic of error detection code, if X does not has mistake, then CRC (X)=ZEROS, and on the other hand, it is low-down for obtaining the probability of ZEROS to the code word applies CRC decoding of mistake.
In one embodiment, ECC cell 50 applies two kinds of CRC decoding operations, i.e. (having can for CRC (X) and CRC (～X) Can be parallel).If CRC (X)=ZEORS, then code word 70 is considered as when not inverting depositing by storage circuit Storage.If on the other hand, CRC (～X)=ZEROS, then think that code word 70 receives reversion.Otherwise (that is, at two When CRC decoder not having any one produce ZEROS result), still it is unsatisfactory for the mark that LDPC iterative decoder terminates ahead of time Accurate.
In another embodiment, ECC cell 50 is based only upon value execution a kind of CRC decoding of reversion position 78.If it is anti- Indexing instruction is without reversion (" 0 "), then CRC (X) is decoded by ECC cell 50.Otherwise, this position will indicate code word by the most anti- Turn, and CRC (～X) will be decoded by ECC cell 50.If corresponding CRC decoded result is equal to ZEORS, then ECC cell 50 Terminating ahead of time of LDPC decoding iteration can be performed.
In another embodiment, decoding scheme depends on ISN is linear code.According to linear characteristic, CRC (～X+ ONES)=CRC (～X)+CRC (ONES), wherein, "+" represent XOR by turn.But, due to X=～X+ONES, thus we push away Break and ZEROS=CRC (X)=CRC (～X)+CRC (ONES).In an exemplary embodiment, ECC cell 50 performs CRC solution Code, and check that result is equal to CRC (ONES) and is also equal to ZEORS, thus identify code word respectively and still do not had by crossing reversion Cross and inverted.It may be noted that for each different ISN, need precalculate value CRC (ONES) and only it deposited Storage is once.
In embodiment described above, ECC cell 50 (on rare occasion) may run into the knot that CRC () decodes Fruit and the conflict solved between code value of bit flipping 78.Additionally, the result of application CRC (X) and CRC (～X) may be not always able to Obtain the final the decision whether data read inverted.In such cases, suitable finger is provided for ECC cell Show.When there is such conflict or without final conclusion situation, ECC cell 50 can use any suitable coding/decoding method.Such as, ECC cell 50 may decide that and do not terminates LDPC iterative decoder.
Some in the embodiment described under the linguistic context of error detection code above are also applied for error correcting code.
Now, we describe ISN 82 and include one of error correcting code such as BCH (being configured to error correction operations pattern) Embodiment.ECC cell 50 applies two kinds of decoding operations, i.e. BCH (～X) and BCH (X).If only～one of X or X is can Decoding, i.e. error-free result is decoded, then code word 70 is considered as bit flipping or non-bit flipping by storage circuit respectively 's.If～X and X is the most decodable, or both fail to generate error-free result, then can use a certain other Standard determines inverted status, such as, and standard based on the mistake with (after following decoding closely) minimum quantity.Other standards bag With concordance or the weighting of error pattern inverting position after including such as decoding.In the embodiment of alternative, ECC cell 50 Indicate indecisive result or multiple decoded result.In the embodiment that interior error correcting code is used for " error floor " circumstances In, seldom it is necessary to apply inner decoding device, and therefore BCH decoding will only be caused a small amount of calculating to increase twice by (every code word) Add.
In above-described embodiment, we commonly assume that, in outer code, the valid code word of reversion are mapped to other Valid code word.In other do not guarantee the embodiment of this characteristic, it is also possible to describe with above with respect to ISN to outer code application Similar decoding scheme.
Read the data of storage in the second programming phases
Fig. 3 A and Fig. 3 B shows according to embodiment of the present invention for using non-integer number position at every unit The diagram of the programming level distribution of storage data.Each one of Fig. 3 A and Fig. 3 B is divided into upper and lower, first volume is shown respectively Programming level after journey stage and the second programming phases and corresponding unit occupation rate.
In disclosed embodiment, according to Fig. 3 A and Fig. 3 B, we use lower floor's TLC equipment, will be in the first stage The memory cell 32 of this equipment is programmed by four levels of middle employing, will do two levels in four levels in second stage Further Division.Owing to each unit stores two information after stage, and the half in unit is programmed for Second stage stores extra order, thus equipment the most averagely stores 2.5/unit (using six in eight TLC levels).
In figure 3 a, L0, L1, L3 and L5 represent four can be programmed into by memory cell 32 in the first phase Level.Each one in level L0, L1, L3 and L5 is respectively mapped to the even combination in corresponding position, i.e. " 11 ", " 10 ", " 00 " and " 01 ". In the even combination in each such position, each corresponds to independent data stream or page.In following description, left lateral position pair Should be in LSB page position, and right lateral position is corresponding to CSB page of position (that is, " 10 " represent LSB=" 1 " and CSB=" 0 ").
In the second programming phases, only with the extra order (MSB) list to being programmed to grade L1 or L3 in the first phase Unit programs further.It may be noted that owing to mapping according to selected position to level, CSB position is equal to " 1 " in level L0 and L5, And equal to " 0 " in level L1 and L3, it is thus possible to by only examining the unit that CSB position and identifying is on grade L1 and L3. This characteristic also simplify MSB data and reads, as mentioned below.
As shown in Figure 3A, the programming of extra order makes division, so that there are about in each unit by filling the unit on L1 Half is retained on L1, and remaining second half unit is then programmed to L2.Similarly, about half quilt in the unit on L3 Being programmed to L4, second half unit then keeps constant on L3.Thus, be programmed in second stage a grade L1, L2, L3, The unit of the one in L4 distributes " 100 ", " 101 ", " 001 " or " 000 " storage three information according to corresponding position.Each this In the position tlv triple of sample, the position on left side, centre and right side corresponds to corresponding separate data stream, such as, LSB, CSB or MSB number According to page.Owing to not programming level L0 and L5 in second stage, thus the corresponding positions tlv triple distributing to these grades is represented as " 11x " or " 01x ", wherein " 11 " and " 01 " are the even combinations (from the first stage) in previous position, and " x " of the rightmost side represents Unprogrammed extra order.
Now, description is used for using the programming level configuration described in Fig. 3 A and Fig. 3 B to read in TLC equipment storing by we The several method of data.As described below, both should read with LSB and CSB data to identify the list using extra order programming The conventional method of unit is different, and some in disclosed method can identify adopt by the most only reading CSB or LSB data Unit with MSB data programming.
In one embodiment, with reference to Fig. 3 A, in order to read MSB page, first storage circuit identifies in second stage Use extra order to be programmed, be i.e. programmed to a grade L1 ... the memory element of L4.First this storage circuit reads LSB and CSB In Ye each one and to its application ECC decoding, and identify that the position, the leftmost side of tlv triple in place stores place value " 10 " or " 00 " in even Memory cell.In another embodiment, storage circuit uses the read threshold TH_CSB_LO in single reading order Only read CSB data with TH_CSB_HI (in Fig. 3 A) and it is carried out ECC decoding.Programming level shown in Fig. 3 A and position are to level The configuration mapped makes to store circuit it can be avoided that the unnecessary reading and the decoding that cause because reading LSB and CSB data are grasped Make.
Afterwards, storage circuit identification CSB position is equal to the unit of " 0 ".In order to read the number of write in the unit identified According to (such as, MSB data), storage circuit for example with two read threshold (not shown), thus a threshold value is placed in L1 and Between L2, and another threshold value is placed between L3 and L4.
In figure 3b, in the first phase level L0, L1, L2 and L4 are mapped to corresponding position even " 11 ", " 10 ", " 00 " and “01”.In second stage, extra order is only programmed to be programmed in the first phase the memorizer of L2 or L4 by storage circuit Unit.Thus, in the unit on L2, approximately half of level is moved to the level of half in the unit on L3, and L4 and is moved to L5. L2, L3, L4 and L5 level is mapped to corresponding position tlv triple " 001 ", " 000 ", " 010 " and " 011 ".L0 and L1 is at second-order for level In Duan unprogrammed, and be mapped to corresponding position tlv triple " 11x " and " 10x ".
In some embodiments, similar with the description in fig. 3 above A, the position on left side, centre and right side corresponds to phase LSB, CSB of answering and MSB data page.In one embodiment, in order to read MSB data, storage circuit is initially with at figure The single read threshold represented with TH_LSB in 3B only reads LSB page decoding it (to be carried out with to LSB and CSB page of both of which Read and decoding define comparison), thus identify the unit using extra order to be programmed.This embodiment is relative to above The embodiment (wherein read and need two read thresholds) of Fig. 3 A has advantage, because greater amount of read threshold generally will Increase the page and read the time.Additionally, similar with the method for Fig. 3 A, it is only necessary to two read thresholds read MSB data.Afterwards, deposit Storage circuit uses two read thresholds to read MSB data from the unit identified, in two read thresholds, one is placed in L2 and L3 Between, and another is placed between L4 and L5.By the configuration using the programming level shown in Fig. 3 B and position to map to level, deposit Storage circuit can effectively read MSB page and avoid the unnecessary reading caused because reading LSB and CSB data to conciliate Code operation.
From the description above with accompanying drawing it can be seen that the programming carrying out extra order in second stage would generally be different Uneven unit occupation rate is formed between Ji.Such as, Fig. 3 B is programmed to a grade L2 ... the quantity of the unit of each one of L5 About it is programmed to the half of the quantity of the unit of L0 or L1.As shown in Figure 3 B, the threshold voltage (V between levelTH) interval or every Unit occupation rate (together with other factors) from degree and every one-level affects the lap between adjacent level distribution.Owing to this is overlapping Closely related with read error probability, thus unit occupies the uniform intervals between the level that there are differences and may cause crossing over each There is uneven (and non-optimal) read error probability in level.
In some embodiments, the threshold voltage distributing to different programming level is entered by unit occupation rate based on each grade Row sets, thus realizes crossing over the uniform read error probability of all levels.In order to compensate for different unit occupation rates, Distance (that is, threshold voltage difference) between adjacent highly-filled level should be set greater than the relatively low adjacent level of compactedness it Between distance.
In the exemplary configuration of Fig. 3 B, Δ L01 represents the voltage difference between L0 and L1, and Δ L23, Δ L34 and Δ L45 represents the voltage difference between L2-L3, L3-L4 and L4-L5 respectively.In one embodiment, by based on level occupation rate Adjust interval so that Δ L01 is more than voltage difference delta L23, Δ L34 and Δ L45 (supposing that in present exemplary they are similar) In each one, storage circuit will cross over each program level realize uniform read error probability.Additionally, should be by between L1 and L2 Interval be configured to more than Δ L23, Δ L34 and Δ L45, but be less than Δ L01.
In some embodiments, storage circuit can additionally based on the factor beyond level occupation rate determine programming level it Between voltage spaces.Such as, the United States Patent (USP) 7,925,936 that on July 11st, 2008 submits to describes for by adjusting inter-stage Interval and compensate for having the read operation of varying number performed in the reading of the not page of coordination effectiveness, thus across More each programming level realizes the several method of uniform read error probability, by quoting, the disclosure of which is incorporated to this Literary composition.
The configuration of Fig. 3 A and Fig. 3 B is the exemplary configuration purely illustrated for the reason of clear concept, and can also Use the configuration that other are suitable.Such as, in the embodiment of alternative, it would however also be possible to employ other program level, progression, level division side Case, the mapping of position to level, read threshold and/or inter-stage interval.
Data are stored according to known offset in second stage
For example, it is contemplated that use seven programming levels to store data in TLC equipment.In some embodiments, storage circuit Use the appropriate variations storage data of above-described two benches programmed method.In an exemplary embodiment, storage electricity Road uses such as four levels as shown in the top of Fig. 3 A to store LSB and CSB data in the first phase.Therefore, currently Example in, will be to three levels in second stage, such as, L0, L1 and the L3 on Fig. 3 A top divide.
In some embodiments, the data stream that LSB, CSB and MSB data are represented by storage circuit is separately encoded to code In word such as code word 70.In one embodiment, the memory cell 32 in N unit group is programmed by storage circuit, And also will have data encoding to be stored in the code word of N position, as described herein.In following description, term is " single Tuple " or only group refer to the one group of N unit being simultaneously programmed.Although it may be noted that it is assumed that the data stored are in phase The code word answered is encoded by ECC, but disclosed method applies also for storing original noncoding data.
Storage circuit uses four programming level write (in the first phase) N position LSB code words and CSB code word.As follows Literary composition is it is further described that in each unit group, the quantity of available cell is less than N, but storage circuit will really in the first phase Protect this numeral more than 0.75 N (the most a small amount of exceeding).Therefore, although can not be by complete MSB code word storage In individual unit group, but three N position code words can be stored in four unit groups.
In following table 1, we demonstrate for dividing three N position code words between four unit groups Technology.In Table 1, MSB0 ... MSB2 represents MSB code word, and CW0 ... CW3 represents unit group.Entry in table 1 depicts The quantity of the position taken out from each code word and be written in the available cell corresponding units group.Such as, by from MSB0's 0.25 N position and the 0.5 N position from MSB1 are programmed in CW1.And for example, between CW1 and CW2, MSB1 position is carried out half-and-half Divide.
MSB0 MSB1 MSB2
CW0 0.75·N 0 0
CW1 0.25·N 0.5·N 0
CW2 0 0.5·N 0.25·N
CW3 0 0 0.75·N
Table 1: divide code word bit in unit group
In some embodiments, if it is necessary, storage circuit in the first phase by reversion LSB, CSB or this two Plant code word and data are carried out pretreatment, so that it is guaranteed that at least 0.75 N number of unit can be used for storing accordingly MSB data Unit group in.The group of available cell can be divided into two complementary subgroups so that a subgroup comprises 0.75 N number of list Unit, and another subgroup comprises the remaining element being referred to as " extra cell ".Due to each one in four levels in the first stage Unit occupation rate depend on stored real data, thus the quantity of extra cell also has data dependence.
The various position being arranged between four unit groups and dividing three MSB code words can be used.Table 1 above describes A kind of such example, and additional example is described below.In one embodiment, each code word is divided into two Section, according to some side-play amount by unit groups different for two storage of sectors to two in available cell.Storage circuit is used All available cell in each unit group are by code word MSB0 to the greatest extent ... each section of MSB2 is continuously stored in CW0 ... in CW3. Make Ni represent the quantity of the available cell in unit group CWi, and Ei represents the quantity of corresponding extra cell.
In this embodiment, according to the section of the side-play amount storage code word changed in available cell.It may be noted that Under current context, only weigh the side-play amount between the available cell in each unit group.Thus, such as offset of zero relates to unit The first available cell in group.Reading given MSB code word, storage circuit needs by from the section storing other code words Unit group read low efficacy data estimate each section storage according to respective offsets amount.
Such as, in current embodiments, the N0=0.75 N+E0 of MSB0 position is deposited by storage circuit with offset of zero Storage is to (that is, the first section) in CW0, and with offset of zero, the remainder (that is, the second section) of MSB0 position is stored CW1 In.Afterwards, storage circuit is after following MSB0 the second section closely, i.e. from the beginning of side-play amount N-N0=0.25 N-E0, immediately will Oneth MSB1 storage of sectors is in CW1.
Therefore, when reading MSB1 the first section, first storage circuit should read LSB and the CSB number being stored in CW0 According to and decode it, identify and measure the quantity of available cell N0, calculate E0=N0-0.75 N and also use E0 estimation first The real offset (or equivalently calculating N-N0) of MSB1 section.Reading about the section of MSB2 code word has similar begging for Opinion is set up.Therefore, in this example, the MSB1 section that reading is stored in CW1 and CW2 further relates to reading and is stored in another unit Data in group (i.e. CW0).
In the alternative embodiment being described below, storage circuit stores MSB according to known offset in available cell Section.So it is capable of the effective reading to MSB data, because reading given MSB code in the case of known to side-play amount Word only need to read the data stored in the unit group of the section storing this code word.
Fig. 4 A and Fig. 4 B is to schematically show for storing number according to known offset in available memory cells According to the diagram of two kinds of technology.Consider passing through CW0 ... four unit groups that CW3 represents write by MSB0, MSB1 and Three N position MSB code words that MSB2 represents.As it has been described above, each unit group in seven grades of TLC examples, in four unit groups Including N+Ei available cell of Ni=0.75 of respective numbers, wherein Ei includes extra cell.
In Figure 4 A, each code word MSBi (i=0 ... 3) is divided into two districts represented with MSBi_A and MSBi_B Section, each section has known predefined size.MSB0_A section includes 0.75 N number of position, and stores with offset of zero In CW0.The MSB0_B section comprising 0.25 N number of is also stored in CW1 with offset of zero.MSB1 section partition is become MSB1_A and MSB1_B section, they each one there is 0.5 N number of position.After following MSB0_B position closely, i.e. according to 0.25 N number of list The known offset of unit is by MSB1_A storage of sectors to CW1.MSB1_B section is stored in CW2 according to offset of zero, from And forming the known offset of 0.5 N number of unit for storing MSB2_A the first section, MSB2_A the first section comprises 0.25 N number of position.MSB2_B the second section includes 0.75 N number of position, and stores in CW3 with offset of zero.Table 2 summarizes MSB section as shown in Figure 4 A is in unit group CW0 ... the distribution in CW3.
Table 2: distribute code word according to known offset according to Fig. 4 A
In figure 4b, use up all available cell and write the first section of each MSB code word according to known offset.? According to remaining position (the i.e. second section) of offset of zero write code word in another unit group.Although by each MSBi code stroke It is divided into section MASBi_A and MSBi_B that size depends on Ei, but section remains and carries out according to known constant offset amount Location.Table 3 summarizes the distribution in corresponding unit group of the MSB code field according to Fig. 4 B.
Table 3: distribute code word in unit group according to Fig. 4 B
In the above-described embodiment, all code words comprising MSB code word share common N position size.One side Face, this simplify coding/decoding and write/read operation and interlock circuit.But, on the other hand, need each N position MSB code word stores in more than one unit group, as described above.In the embodiment of alternative, MSB code word only includes 0.75 N number of position (is referred to as short MSB code word).Owing to each N unit group includes the N number of available cell in Ni >=0.75, thus Short MSB code word can be fitted in unit group all the time.But, the encoding scheme of short MSB code word is different from N position code word Encoding scheme, it should use the segmentation of other data and parity check bit.Therefore, ECC cell 50 can include for short MSB generation Independent encoder special/the decoder of code word.
Fig. 5 be schematically show according to one embodiment of the invention in available memory cells according to The flow chart of the method for known side-play amount write MSB data.The method of Fig. 5 and the MSB data shown in Fig. 4 B are in unit group In distribution consistent.When the method starts, it is assumed that storage circuit has been carried out LSB and CSB data are write CW0 ... CW3 The first programming phases, and three code words MB0 ... MB2 prepares to be programmed.The method starts from storing circuit and knows at unit Other step 200 identifies the unit that can be used for being programmed MSB data in each unit group CWi.In making Ni represent CWi The quantity of available cell, and Ei=N-Ni represents the quantity of corresponding extra cell.Method advances to MSB0 programming step subsequently Rapid 204.In step 204, storage circuit uses up all available CW0 unit with offset of zero by 0.75 N+E0 position before MSB0 It is programmed in CW0.Remaining 0.25 N-E0 position of MB0 is programmed in CW1 by storage circuit with offset of zero afterwards.Connect down Coming, MSB1 and MSB2 code word is programmed in corresponding step 208 and 212 by storage circuit.Storage circuit is according to skew Measure in MSB1 is write CW1 by 0.25 N and continue in CW2.Similarly, MSB2 is write by storage circuit according to side-play amount 0.5 N Enter in CW2, and according to offset of zero by remaining MSB2 position write CW3.
Fig. 6 is to schematically show according to one embodiment of the invention for reading in available memory cells The flow chart of the method for the MSB data write according to known side-play amount.The method starts from storing circuit and programs in identification Unit step 250 identifies the unit using MSB data to be programmed.Such as, it will be clear that want independent from table 3 Ground only reads the one in MSB0, MSB1 or MSB2 code word, identify the most respectively CW0 and CW1}, CW1 and CW2} or CW2 and The unit of the employing extra order programming in CW3} is sufficient to.MSB0, MSB1 or MSB2 to be read, storage circuit is carried out to accordingly Read step 254,258 or 262.In step 254, storage circuit is by all available cell (the i.e. N0=0.75 in CW0 N+E0 position) read into the interim section represented with MSB0_A.The quantity of the position N0 that the circuit First Astronautic Research Institute for Measurement and Test of storage afterwards reads, calculates E0=N0-0.75 N, and 0.25 N-E0 position before the available cell of CW1 was read into facing that MSB0_B represents Time section.Two interim sections are coupled together, to generate complete MSB0 code word by storage circuit afterwards.In read step In 258 and 262, storage circuit reads MSB1 or MSB2 according to Fig. 4 B and table 3 similarly with suitable section sizes and side-play amount Code word.
Fig. 4 A, Fig. 4 B, Fig. 5 and Fig. 6 are the exemplary configuration purely illustrated for the reason of clear concept, and also may be used To use other suitable configurations.For example, it is also possible to use other an appropriate number of code words and unit group.And for example, Ke Yixuan Select code word section other sequencing schemes in unit group, such as, hand between MSB2_A and MBS0_B or MSB1_B Change.
In embodiment described in Fig. 4 A, Fig. 4 B, Fig. 5 and Fig. 6, during second stage, generally skip additional list Unit.But, in the embodiment of alternative, storage circuit can use extra cell storage user, storage to manage and/or any Other kinds of data.
Should be appreciated that embodiment as described above is quoted by way of example, and the invention is not restricted to above Content that is the most specifically shown or that describe.On the contrary, the scope of the present invention includes combination and the son of various feature as described above Combination both, and those skilled in the art when reading described above it is appreciated that and the most undocumented institute State the variants and modifications of various feature.The document being incorporated by reference in the present patent application is considered as that the application is inseparable The part cut, if but any term be defined as in these documents being incorporated to this specification in explicitly or implicitly The definition made conflicts mutually, should only consider the definition in this specification.

Claims (14)

1. for a method for data storage, including:
By utilizing at least outer code and ISN data are encoded and optionally coded data is being stored in memorizer Coded data reversal was made to store the data in memory cell described in a group before in unit；And
From the data coded by the reading of described memory cell；
To the coded data application inner decoding read, to produce decoded result；And
According to the described decoded result of described ISN, make at least some of reversion of read data conditionally.
Method the most according to claim 1, wherein said ISN includes that the reversion of valid code word produces another the most all the time The code of valid code word, and wherein apply described inner decoding to include the coded data read and the coded number read According to inverted version at least one be decoded.
Method the most according to claim 2, wherein applies described inner decoding to include the coded data read and institute Described both inverted version of the coded data read are decoded, and invert the institute of the data read the most conditionally State the decoding knot including coded data that is only error-free at the decoded result of described inverted version and that read at least partially The most non-error-free time make described at least some of reversion of read data.
Method the most according to claim 2, wherein stores described data and includes being stored in relation to represent institute with described data The reversion the instruction whether data of storage are inverted, wherein reads coded data and includes being read out described reversion instruction And decoding, and described inner decoding is wherein applied to include, according to described reversion instruction, only the coded data read being carried out Decode or only the described inverted version of the coded data read be decoded.
Method the most according to claim 4, the most described at least some of bag of the data that reversion is read Including when the described decoded result of the coded data read is with described reversion instruction contradiction, instruction can not decide whether to institute The data read invert.
Method the most according to claim 2, wherein said ISN includes error detection code, and the most anti- Turn the described of data read and be included in described decoded result at least partially equal to the complete 1 word described inner decoding of application Described at least some of reversion of read data is made during result, and do not make when described decoded result is error-free to be read Described at least some of reversion of data.
Method the most according to claim 2, the most described at least some of bag of the data that reversion is read Include the decoded result contradiction of the decoded result in the coded data read and the described inverted version of the coded data read Time, the instruction data that can not decide whether to being read invert.
8. for a device for data storage, including:
Memorizer, described memorizer includes the array of memory cell；With
Storage circuit, described storage circuit be configured to utilize at least outer code and ISN data are carried out coding and optionally Coded data reversal was made to store the data in one before by coded data storage in a memory cell Organize in described memory cell, from the data coded by the reading of described memory cell, in the coded data application read Code decoding is to produce decoded result, and makes read data conditionally extremely according to the described decoded result of described ISN Few part reversion.
Device the most according to claim 8, wherein said ISN includes that the reversion of valid code word produces another the most all the time The code of valid code word, and wherein said storage circuit is configured to the coded data read and the coded number that read According to inverted version at least one be decoded.
Device the most according to claim 9, wherein said storage circuit is configured to the coded data read and institute Described both inverted version of the coded data read are decoded, and only error-free at the decoded result of described inverted version And the decoded result of the coded data read non-error-free time make described at least some of reversion of read data.
11. devices according to claim 9, wherein said storage circuit is configured to be stored in relation to table with described data Show the reversion instruction whether stored data are inverted, described reversion instruction is read out and decodes, and according to described The coded data read only is decoded or only enters the described inverted version of the coded data read by reversion instruction Row decoding.
12. devices according to claim 11, wherein said storage circuit is configured in the coded data read When described decoded result and described reversion instruction contradiction, the instruction data that can not decide whether to being read invert.
13. devices according to claim 9, wherein said ISN includes error detection code, and wherein said storage Circuit is configured to make read data at described decoded result equal to during to the result of complete 1 word application described inner decoding Described at least some of reversion, and the described at least some of anti-of read data is not made when described decoded result is error-free Turn.
14. devices according to claim 9, wherein said storage circuit is configured to the solution in the coded data read When code result and the decoded result contradiction of the described inverted version of coded data read, instruction can not decide whether to institute The data read invert.
CN201480065225.3A 2013-12-20 2014-09-30 For the method and apparatus for being encoded and being stored to data Active CN105793927B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US14/135,881 US9230655B2 (en) 2013-12-20 2013-12-20 Data storage management in analog memory cells using a non-integer number of bits per cell
US14/135,881 2013-12-20
US14/135,823 US9171624B2 (en) 2013-12-20 2013-12-20 Management of data storage in analog memory cells using a non-integer number of bits per cell
US14/135,823 2013-12-20
PCT/US2014/058162 WO2015094452A1 (en) 2013-12-20 2014-09-30 Management of data storage in analog memory cells using a non-integer number of bits per cell

Publications (2)

Publication Number Publication Date
CN105793927A true CN105793927A (en) 2016-07-20
CN105793927B CN105793927B (en) 2018-06-08

Family

ID=53400746

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480065225.3A Active CN105793927B (en) 2013-12-20 2014-09-30 For the method and apparatus for being encoded and being stored to data

Country Status (7)

Country Link
US (4) US9230655B2 (en)
JP (1) JP6145220B2 (en)
KR (1) KR101885976B1 (en)
CN (1) CN105793927B (en)
DE (1) DE112014005810B8 (en)
TW (1) TWI516035B (en)
WO (1) WO2015094452A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111240584A (en) * 2018-11-28 2020-06-05 华邦电子股份有限公司 Control method of memory and non-transient computer readable medium

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015167509A1 (en) * 2014-04-30 2015-11-05 Empire Technology Development Llc Differential writing for life extension of portions of a memory device
US9979416B2 (en) * 2014-12-10 2018-05-22 Rambus Inc. Memory controller and method of data bus inversion using an error detection correction code
US9965356B2 (en) * 2016-09-02 2018-05-08 Alibaba Group Holding Limited Method and system of high-availability PCIE SSD with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset
US10484008B2 (en) * 2017-09-28 2019-11-19 SK Hynix Inc. Memory system with on-the-fly error detection and termination and operating method thereof
JP6910739B2 (en) * 2018-03-05 2021-07-28 東芝情報システム株式会社 Evaluation analysis target memory device and memory evaluation analysis system
US11811424B2 (en) * 2021-04-05 2023-11-07 Micron Technology, Inc. Fixed weight codewords for ternary memory cells

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030076718A1 (en) * 2001-09-28 2003-04-24 Stmicroelectronics S.R.I Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor
US20040135709A1 (en) * 2000-12-27 2004-07-15 Cornelius William P. Methods and apparatus for constant-weight encoding and decoding
CN1601654A (en) * 2003-09-25 2005-03-30 松下电器产业株式会社 Semiconductor nonvolatile memory device
US20070047042A1 (en) * 2005-08-30 2007-03-01 Sony Corporation Hologram recording apparatus and hologram recording method
WO2008069385A1 (en) * 2006-12-06 2008-06-12 Samsung Electronics Co., Ltd. A multi-level cell memory device and method thereof
CN101405810A (en) * 2006-01-20 2009-04-08 马维尔国际贸易有限公司 Method and system for error correction in flash memory
US20100125701A1 (en) * 2008-11-18 2010-05-20 Ki Tae Park Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same
CN102024501A (en) * 2009-09-18 2011-04-20 株式会社东芝 Memory system and control method for the same
CN102099864A (en) * 2008-07-02 2011-06-15 莫塞德技术公司 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1199725B1 (en) 2000-10-13 2010-10-06 STMicroelectronics Srl Method for storing and reading data in a multibit nonvolatile memory with a non-binary number of bits per cell
US6834017B2 (en) 2002-10-03 2004-12-21 Hewlett-Packard Development Company, L.P. Error detection system for an information storage device
US7069494B2 (en) 2003-04-17 2006-06-27 International Business Machines Corporation Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
US7071849B2 (en) 2004-04-04 2006-07-04 Guobiao Zhang Fractional-Bit Systems
US7167109B2 (en) 2005-03-31 2007-01-23 Chenming Hu Hybrid fractional-bit systems
US7844879B2 (en) 2006-01-20 2010-11-30 Marvell World Trade Ltd. Method and system for error correction in flash memory
US8055979B2 (en) * 2006-01-20 2011-11-08 Marvell World Trade Ltd. Flash memory with coding and signal processing
US7420841B2 (en) 2006-08-30 2008-09-02 Qimonda Ag Memory device and method for transforming between non-power-of-2 levels of multilevel memory cells and 2-level data bits
US20080192544A1 (en) * 2007-02-13 2008-08-14 Amit Berman Error correction coding techniques for non-volatile memory
US8065583B2 (en) 2007-07-06 2011-11-22 Micron Technology, Inc. Data storage with an outer block code and a stream-based inner code
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US7848142B2 (en) 2007-10-31 2010-12-07 Micron Technology, Inc. Fractional bits in memory cells
US7742335B2 (en) 2007-10-31 2010-06-22 Micron Technology, Inc. Non-volatile multilevel memory cells
KR100857252B1 (en) 2007-12-27 2008-09-05 (주)인디링스 Flash memory device and flash memory programming method equalizing wear-level
US8255758B2 (en) * 2008-01-21 2012-08-28 Apple Inc. Decoding of error correction code using partial bit inversion
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
KR101618313B1 (en) * 2009-06-15 2016-05-09 삼성전자주식회사 Programming method of nonvolatile memory device
US8910002B2 (en) * 2009-08-24 2014-12-09 OCZ Storage Solutions Inc. NAND flash-based storage device with built-in test-ahead for failure anticipation
US20150348633A1 (en) * 2010-02-11 2015-12-03 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of programming nonvolatile memory devices
US8767459B1 (en) * 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040135709A1 (en) * 2000-12-27 2004-07-15 Cornelius William P. Methods and apparatus for constant-weight encoding and decoding
US20030076718A1 (en) * 2001-09-28 2003-04-24 Stmicroelectronics S.R.I Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor
CN1601654A (en) * 2003-09-25 2005-03-30 松下电器产业株式会社 Semiconductor nonvolatile memory device
US20070047042A1 (en) * 2005-08-30 2007-03-01 Sony Corporation Hologram recording apparatus and hologram recording method
CN101405810A (en) * 2006-01-20 2009-04-08 马维尔国际贸易有限公司 Method and system for error correction in flash memory
WO2008069385A1 (en) * 2006-12-06 2008-06-12 Samsung Electronics Co., Ltd. A multi-level cell memory device and method thereof
CN102099864A (en) * 2008-07-02 2011-06-15 莫塞德技术公司 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same
US20100125701A1 (en) * 2008-11-18 2010-05-20 Ki Tae Park Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same
CN102024501A (en) * 2009-09-18 2011-04-20 株式会社东芝 Memory system and control method for the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111240584A (en) * 2018-11-28 2020-06-05 华邦电子股份有限公司 Control method of memory and non-transient computer readable medium
CN111240584B (en) * 2018-11-28 2023-03-28 华邦电子股份有限公司 Control method of memory and non-transient computer readable medium

Also Published As

Publication number Publication date
US20150179265A1 (en) 2015-06-25
US20150179263A1 (en) 2015-06-25
KR20160079055A (en) 2016-07-05
TWI516035B (en) 2016-01-01
WO2015094452A1 (en) 2015-06-25
US9799397B2 (en) 2017-10-24
KR101885976B1 (en) 2018-08-06
JP6145220B2 (en) 2017-06-07
US9230655B2 (en) 2016-01-05
JP2017504925A (en) 2017-02-09
US20160012883A1 (en) 2016-01-14
DE112014005810B8 (en) 2022-08-04
TW201528692A (en) 2015-07-16
US20170162258A1 (en) 2017-06-08
US9171624B2 (en) 2015-10-27
CN105793927B (en) 2018-06-08
DE112014005810B4 (en) 2022-05-25
DE112014005810T5 (en) 2016-10-06
US9613686B2 (en) 2017-04-04

Similar Documents

Publication Publication Date Title
CN105793927B (en) For the method and apparatus for being encoded and being stored to data
US8830746B2 (en) Optimized threshold search in analog memory cells using separator pages of the same type as read pages
US8773904B2 (en) Optimized threshold search in analog memory cells
US8495465B1 (en) Error correction coding over multiple memory pages
US8869008B2 (en) Adaptation of analog memory cell read thresholds using partial ECC syndromes
US8645794B1 (en) Data storage in analog memory cells using a non-integer number of bits per cell
CN102479556B (en) Nonvolatile semiconductor memory member and its read method
TWI498724B (en) Apparatus and method for protecting data from write failures in memory devices
US8724381B2 (en) Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
US20150067436A1 (en) Nonvolatile Memory System Compression
KR101674339B1 (en) Determining soft data using a classification code
US20120198135A1 (en) Mapping Data to Non-Volatile Memory
JP2021131922A (en) Non-volatile memory with program verify skip
TWI505273B (en) Sparse programming of analog memory cells
US20240154624A1 (en) Flash memory apparatus and storage management method for flash memory
CN115827306A (en) Just-in-time multiplexing scheme for compressed soft bit data in non-volatile memory

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant