CN105789328A - Pattern pair, TFT (Thin Film Transistor) and manufacturing method thereof, and mask plate - Google Patents
Pattern pair, TFT (Thin Film Transistor) and manufacturing method thereof, and mask plate Download PDFInfo
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- CN105789328A CN105789328A CN201610340807.9A CN201610340807A CN105789328A CN 105789328 A CN105789328 A CN 105789328A CN 201610340807 A CN201610340807 A CN 201610340807A CN 105789328 A CN105789328 A CN 105789328A
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- 239000010409 thin film Substances 0.000 title abstract description 5
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000002184 metal Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/54—Absorbers, e.g. of opaque materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Abstract
The embodiment of the invention provides a pattern pair, a TFT (Thin Film Transistor) and a manufacturing method thereof, and a mask plate, relating to the technical field of display. The distance between two adjacent thin-film patterns is adjusted under the condition that the resolution ratio of an exposure machine is not improved. The pattern pair comprises a first strip-shaped pattern and a second strip-shaped pattern; the maximum distance between the first strip-shaped pattern and the second strip-shaped pattern is smaller than 125% of a pre-set resolution ratio. The pre-set resolution ratio is the resolution ratio of the exposure machine for manufacturing the pattern pair.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of pattern to, TFT and preparation method thereof, mask plate.
Background technology
TFT-LCD (ThinFilmTransistorLiquidCrystalDisplay, thin film transistor-liquid crystal display) as a kind of panel display apparatus, have that volume is little, low in energy consumption, radiationless because of it and the feature such as cost of manufacture is relatively low, and be applied to more and more in the middle of high-performance display field.
TFT-LCD generally includes color membrane substrates and array base palte that box is arranged, array base palte is formed with multiple thin layer pattern, for instance be provided with a plurality of parallel data lead 100 as shown in Figure 1 in wiring area.But, along with high PPI (PixelsPerInch, number of pixels) and the designing requirement of narrow frame, the area of wiring area reduces therewith, it is thus desirable to the distance d reduced further between adjacent two data lead-in wires 100, owing to the resolution of this distance d Yu exposure machine is inversely proportional to, therefore to reduce above-mentioned distance d, need to improve the resolution of exposure machine, so cause producing the rising rising this.
Summary of the invention
Embodiments of the invention provide a kind of pattern to, TFT and preparation method thereof, mask plate, it is possible to the distance when not improving exposure machine resolution, between adjacent two Thinfilm patterns.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
The one side of the embodiment of the present invention, it is provided that a kind of pattern pair, including the first strip pattern and the second strip pattern, the ultimate range between described first strip pattern and described second strip pattern is less than the 125% of default resolution；Wherein, described default resolution is the resolution for making the described pattern exposure machine to adopting.
Preferably, the ultimate range between described first strip pattern and the second strip pattern is less than or equal to default resolution；Described default resolution is 4 μm.
The another aspect of the embodiment of the present invention, it is provided that a kind of TFT, the source electrode of described TFT and drain electrode constitute any one pattern pair as above；Wherein, described source electrode is the first strip pattern, and described drain electrode is the second strip pattern.
Preferably, at least one limit in two limits that described source electrode is relative with described drain electrode is tortuous limit.
Preferably, two limits that described source electrode is relative with described drain electrode are tortuous limit；Protuberance on the tortuous limit of described source electrode is symmetrical arranged with the protuberance on the tortuous limit of described drain electrode.
Preferably, two limits that described source electrode is relative with described drain electrode are tortuous limit；Protuberance on the tortuous limit of described source electrode is crisscross arranged with the protuberance on the tortuous limit of described drain electrode.
Preferably, the protuberance on the tortuous limit of described source electrode is triangle, trapezoidal or rectangle with the protuberance on the tortuous limit of described drain electrode.
The another aspect of the embodiment of the present invention, it is provided that a kind of method for making any one TFT above-mentioned, including: on underlay substrate, form metal level；Described metal level being carried out mask exposure etching, forms source electrode and the drain electrode of described TFT, the ultimate range between described source electrode and drain electrode is less than the 125% of default resolution；Wherein, described default resolution is that described mask exposure etching that described metal level is carried out forms the resolution of the exposure machine adopted in the step of pattern pair.
The another further aspect of the embodiment of the present invention, it is provided that a kind of for making any one TFT as above mask plate adopted, described mask plate includes shading region and exposure region, is provided with secondary light shielding part in described exposure region；Ultimate range between adjacent shading region is less than the 125% of default resolution.
Preferably, the ultimate range between adjacent shading region is less than or equal to default resolution；Described default resolution is 4 μm.
Preferably, described secondary light shielding part includes the first sub-light shielding part being arranged on one limit of described exposure region, and is arranged at the second sub-light shielding part on another limit of described exposure region.
Preferably, described first sub-light shielding part and described second sub-light shielding part are oppositely arranged, and have gap between relative described first sub-light shielding part and described second sub-light shielding part.
Preferably, described first sub-light shielding part and described second sub-light shielding part are isosceles triangle, and the waist of described isosceles triangle is 1.5 μm；The relative gap between described first sub-light shielding part and described second sub-light shielding part is 1 μm.
Preferably, described first sub-light shielding part and described second sub-light shielding part are crisscross arranged, and have gap between adjacent described first sub-light shielding part and described second sub-light shielding part.
Preferably, described first sub-light shielding part and described second sub-light shielding part are the square that the length of side is 1.5；Spacing between adjacent two described first sub-light shielding parts or adjacent two described second sub-light shielding parts is 3 μm；1 μm of gap between adjacent described first sub-light shielding part and described second sub-light shielding part.
Preferably, be positioned at that the area of the secondary light shielding part of same exposure region accounts for the area of described exposure region 37%～38%.
The embodiment of the present invention provides a kind of pattern to, TFT and preparation method thereof, mask plate, and described pattern is to including the first strip pattern and the second strip pattern, and the ultimate range between the first strip pattern and the second strip pattern is less than the 125% of default resolution.Wherein, this default resolution is the resolution for making the above-mentioned pattern exposure machine to adopting.Owing to the ultimate range between the first strip pattern and the second strip pattern is less than presetting the 125% of rate respectively, therefore when not improving exposure machine resolution, the area of exposure region of mask plate can be reduced to reduce the distance between the first strip pattern and the second strip pattern, improve the utilization rate of wiring space.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The structural representation of the adjacent two data lead-in wire that Fig. 1 provides for prior art；
The pattern pair that Fig. 2 provides for the embodiment of the present invention prepare schematic diagram；
Fig. 3 is the another kind of structural representation of pattern pair in Fig. 2；
The structural representation of a kind of TFT that Fig. 4 provides for the embodiment of the present invention；
On the source electrode that Fig. 5 provides for the embodiment of the present invention relative with drain electrode while being the structural representation of the TFT on tortuous limit；
The limit that the source electrode that Fig. 6 provides for the embodiment of the present invention is relative with drain electrode is the structural representation of a kind of TFT on tortuous limit；
Fig. 7 is the structural representation of the mask plate for forming the TFT described in Fig. 6；
The limit that the source electrode that Fig. 8 provides for the embodiment of the present invention is relative with drain electrode is the structural representation of the another kind of TFT on tortuous limit；
Fig. 9 is the structural representation of the mask plate for forming the TFT described in Fig. 8；
Figure 10 adopts the practical structures schematic diagram of the TFT that the mask plate shown in Fig. 9 formed；
A kind of method flow diagram making TFT that Figure 11 provides for the embodiment of the present invention；
The structural representation of a kind of mask plate that Figure 12 embodiment of the present invention provides.
Accompanying drawing labelling:
100-data lead；01-pattern pair；10-the first strip pattern；11-the second strip pattern；101-source electrode；Protuberance on the tortuous limit of 1011-source electrode；102-drains；Protuberance on the tortuous limit of 1021-drain electrode；103-semiconductor active layer；104-grid；20-mask plate；201-shading region；202-exposure region；Bis-light shielding parts of 203-；The sub-light shielding part of 2031-first；The sub-light shielding part of 2032-second；R-presets resolution；The width of W-TFT raceway groove；The length of L-TFT raceway groove.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
The embodiment of the present invention provides a kind of pattern to 01, as in figure 2 it is shown, include the first strip pattern 10 and the second strip pattern 11, and the ultimate range d between the first strip pattern 10 and the second strip pattern 11maxLess than default resolution R 125%.
Wherein, presetting resolution T is the resolution for making the above-mentioned pattern exposure machine to adopting.Ultimate range d such as when above-mentioned default resolution R is 4 μm, between the first strip pattern 10 and the second strip pattern 11max< 5 μm.It is further preferred that the ultimate range d between the first strip pattern 10 and the second strip pattern 11maxLess than or equal to above-mentioned default resolution R, i.e. dmax≤ 4 μm, such that it is able to reduce further adjacent two thin layer patterns, namely constitute above-mentioned pattern to 01 the first strip pattern 10 and the distance of the second strip pattern 11.
Above-mentioned pattern can adopt mask plate 20 as shown in Figure 2 to 01, is formed by mask exposure technique.Wherein, mask plate 20 has shading region 201 and exposure region 202.Due to the ultimate range d between the first strip pattern 10 and the second strip pattern 11maxLess than presetting the 125% of rate R respectively, therefore can when not improving exposure machine resolution, reduce the area of the exposure region 202 of mask plate 20, the concrete width H that can reduce exposure region 202, to reduce adjacent two thin layer patterns i.e. distance between the first strip pattern 10 and the second strip pattern 10, improve the utilization rate of wiring space.
It should be noted that the ultimate range d between above-mentioned first strip pattern 10 and the second strip pattern 11maxRefer to, when two limits adjacent as shown in Figure 2 when the first strip pattern 10 and the second strip pattern 11 are straight line, above-mentioned ultimate range dmaxIt is the distance between two limits that the first strip pattern 10 is adjacent with the second strip pattern 11.And as it is shown on figure 3, when two limits adjacent with the second strip pattern 11 when the first strip pattern 10 are non-rectilinear, above-mentioned ultimate range dmaxIt it is the maximum of the spacing on two non-directional limits.
Additionally, the type of TFT is not limited by the present invention, it is possible to can also be top gate type TFT for bottom gate type TFT.
The embodiment of the present invention provides a kind of TFT, and as shown in Figure 4, the source electrode 101 of this TFT and the pattern in drain electrode 102 pie graphs 2 or Fig. 3 are to 01.Wherein, source electrode 101 is above-mentioned first strip pattern 10, and drain electrode 102 is above-mentioned second strip pattern 11.Additionally, this TFT also includes semiconductor active layer 103 and grid 104.
In the case, the ultimate range d between above-mentioned first strip pattern 10 and the second strip pattern 11maxIt is directly proportional to the length L of this TFT channel.Therefore when not improving exposure machine resolution, it is possible to reduce the area of the exposure region 202 of mask plate 20, for instance reduce the width H of exposure region 202, it is possible to reduce the ultimate range d between source electrode 101 and drain electrode 102max, thus reaching the purpose of TFT channel length L.
So, on the one hand, owing to the length L of TFT channel reduces so that the distance between source electrode 101 and drain electrode 102 diminishes, such that it is able to reduce TFT to take the area of sub-pix effective display area, be conducive to improving pixel aperture ratio.On the other hand, owing to the length L of TFT channel reduces, increase the breadth length ratio W/L of TFT channel accordingly, be conducive to improve TFT ON state current (Ion) so that data voltage can promptly and accurately write sub-pix pixel electrode in.
On this basis, in order to improve the breadth length ratio W/L of TFT further.At least one limit in two limits that source electrode 101 is relative with drain electrode 102 is tortuous limit, and in Fig. 5, source electrode 101 is tortuous limit near the limit of drain electrode 102.Wherein, tortuous limit and non-rectilinear limit.So, by arranging above-mentioned tortuous limit, it is possible to increase the width W (adding the length of thick line in Fig. 5) of TFT channel, thus reaching to increase the purpose of TFT channel breadth length ratio W/L.
When below two limits that source electrode 101 is relative with drain electrode 102 being above-mentioned tortuous limit, the pattern of source electrode 101 and drain electrode 102 is described in detail.
Concrete, for instance, as shown in Figure 6, the protuberance 1011 on the tortuous limit of source electrode 101 is symmetrical arranged with the protuberance 1021 on the tortuous limit of drain electrode 102.Wherein, it is used for being formed resolution R=4 μm of the exposure machines of source electrode 101 and drain electrode 102 employing, and ultimate range d between source electrode 101 and drain electrode 102max=4 μm=R < 125% × R.
Additionally, the distance between protuberance 1021 on the tortuous limit of protuberance 1011 on the tortuous limit of the source electrode 101 being oppositely arranged and drain electrode 102 is 1 μm, and above-mentioned protuberance is the isosceles triangle of 3 μ m 1.5 μm.
Based on this, in order under the premise not improving exposure machine resolution, form above-mentioned source electrode 101 and drain electrode 102, can be as shown in Figure 7, a limit of the exposure region 202 that mask plate 20 width is 4 μm arranges the first sub-light shielding part 2031, another limit of this exposure region 202 arranges the second sub-light shielding part 2032.Wherein, the first sub-light shielding part 2031 and the second sub-light shielding part 2032 are oppositely arranged, and have the gap of 1 μm between relative the first sub-light shielding part 2031 and the second sub-light shielding part 2032.First sub-light shielding part 2031 and the second sub-light shielding part 2032 are the isosceles triangle of 3 μ m 1.5 μm.
In the case, in an exposure region 202 area sum is this exposure region 202 area the 37.5% of first sub-light shielding part 2031 and the second sub-light shielding part 2032, such that it is able to form ultimate range dmaxBeing 4 μm, minimum range is source electrode 101 and the drain electrode 102 of 1 μm.
Again such as, as shown in Figure 8, the protuberance 1011 on the tortuous limit of source electrode 101 is crisscross arranged with the protuberance 1021 on the tortuous limit of drain electrode 1021.Wherein, it is used for being formed resolution R=4 μm of the exposure machines of source electrode 101 and drain electrode 102 employing, and ultimate range d between source electrode 101 and drain electrode 102max=2.5 μm of < R=4 μm.
Additionally, the distance between protuberance 1021 on the tortuous limit of protuberance 1011 on the tortuous limit of the source electrode 101 being crisscross arranged and drain electrode 102 is 1 μm, and above-mentioned protuberance is the square of 1.5 μ m 1.5 μm.
Based on this, in order under the premise not improving exposure machine resolution, form above-mentioned source electrode 101 and drain electrode 102, can be as shown in Figure 9, a limit of the exposure region 202 that mask plate 20 width is 4 μm arranges the first sub-light shielding part 2031, another limit of this exposure region 202 arranges the second sub-light shielding part 2032.Wherein, the first sub-light shielding part 2031 and the second sub-light shielding part 2032 are crisscross arranged, and have the gap of 1 μm between adjacent the first sub-light shielding part 2031 and the second sub-light shielding part 2032.Spacing between adjacent two the first sub-light shielding parts 2031 or adjacent two the second sub-light shielding parts 2032 is the square that 3 μm of first sub-light shielding part 2031 and the second sub-light shielding part 2032 are 1.5 μ m 1.5 μm.
In the case, in one exposure region 202 area sum is this exposure region 202 area the 37.5% of first sub-light shielding part 2031 and the second sub-light shielding part 2032, based on this, it is possible to the minima of exposure machine longitudinal direction light intensity is adjusted to more than 0.7125, such that it is able to form ultimate range dmaxBeing 2.5 μm, minimum range is source electrode 101 and the drain electrode 102 of 1 μm, will not stick together between source electrode 101 and drain electrode 102.
In sum, in the process of the source electrode 101 and drain electrode 102 that form the TFT shown in Fig. 6 or Fig. 8, on the one hand, the distance of source electrode 101 and drain electrode 102 can be reduced under avoiding the premise improving exposure machine resolution, to reduce the area occupied of TFT, improve pixel aperture ratio.On the other hand, owing to two limits that source electrode 101 is relative with drain electrode 102 are tortuous limit, therefore can increase the width W of TFT channel, be beneficial to the channel width-over-length ratio W/L improving TFT.
It should be noted that due to diffraction of light effect in the process of exposure, as shown in Figure 10, the limit that source electrode 101 is relative with drain electrode 102 is curve for the source electrode 101 being actually formed and the pattern of drain electrode 102.
The explanation that above-mentioned protuberance 1011 on the tortuous limit of source electrode 101 carries out for isosceles triangle or square with the protuberance 1021 on the tortuous limit of drain electrode 1021, in addition above-mentioned protuberance can also be other triangle or trapezoidal, or rectangle in addition to square, this is not limited by the present invention.
The embodiment of the present invention provides a kind of method for making any one TFT above-mentioned, as shown in figure 11, and including:
S101, on underlay substrate formed metal level.This underlay substrate can be transparency carrier, or is formed with the substrate of thin layer on the transparent substrate.
S102, above-mentioned metal level is carried out mask exposure etching, formed such as Fig. 5, the source electrode 101 of the TFT shown in 6 or 8 and drain electrode 102, the ultimate range d between this source electrode 101 and drain electrode 102maxLess than default resolution R 125%.
It should be noted that the resolution that above-mentioned default resolution R is the exposure machine adopted in above-mentioned steps S102.So, on the one hand, due to the ultimate range d between source electrode 101 and drain electrode 102maxLess than default resolution R 125%, therefore can when not improving exposure machine resolution so that the distance between source electrode 101 and drain electrode 102 diminishes, to reduce the length L of TFT channel, such that it is able to reduce TFT to take the area of sub-pix effective display area, be conducive to improving pixel aperture ratio.On the other hand, owing to the length L of TFT channel reduces, increase the breadth length ratio W/L of TFT channel accordingly, be conducive to improve TFT ON state current (Ion) so that data voltage can promptly and accurately write sub-pix pixel electrode in.
The embodiment of the present invention provides a kind of and makes any one TFT above-mentioned mask plate 20 adopted, as shown in figure 12, this mask plate 20 includes shading region 201 and exposure region 202, it is provided with secondary light shielding part 203 in this exposure region 202, the light exposed in exposure region 202 can be blocked, ultimate range between adjacent shading region 201, i.e. the Breadth Maximum H of this exposure region 202maxLess than default resolution R 125%.Preferably, when default resolution R is 4 μm, the ultimate range between adjacent shading region 201, i.e. the Breadth Maximum H of this exposure region 202maxLess than or equal to default resolution R.
So, on the one hand can when not improving exposure machine resolution, by adopting above-mentioned mask plate can reduce the distance between source electrode 101 and drain electrode 102, to reduce the length L of TFT channel, such that it is able to reduce TFT to take the area of sub-pix effective display area, be conducive to improving pixel aperture ratio.On the other hand, owing to the length L of TFT channel reduces, increase the breadth length ratio W/L of TFT channel accordingly, be conducive to improve TFT ON state current (Ion) so that data voltage can promptly and accurately write sub-pix pixel electrode in.
It is further preferred that the area being positioned at the secondary light shielding part 203 of an exposure region 202 accounts for the 37%～38% of this exposure region 202 area.When the area of this secondary light shielding part 203 accounts for the area of exposure region 202 less than 37%, although be conducive to reducing the distance between source electrode 102 and drain electrode 103, but can cause that the minimum range between source electrode 102 and drain electrode 103 is less than 1 μm, thus being susceptible to adhesion.And when the area of this secondary light shielding part 203 accounts for the area of exposure region 202 more than 38%, although the phenomenon sticked together can be prevented effectively between source electrode 102 and drain electrode 103, but reduce the poor effect of the spacing of source electrode 102 and drain electrode 103.Therefore when the area of secondary light shielding part 203 accounts for the scope that the area of exposure region 202 is positioned at 37%～38%, both can avoid the generation of above-mentioned adhesion phenomenon, be conducive to again reducing the distance between source electrode 101 and drain electrode 103.And the area of secondary light shielding part 203 accounts for the 37.5% of exposure region 202 area for optimum.
On this basis, in order to improve the breadth length ratio W/L of TFT further.Two limits that source electrode 101 is relative with drain electrode 102 are tortuous limit.The width W of TFT channel can be increased, thus reaching to increase the purpose of TFT channel breadth length ratio W/L by above-mentioned tortuous limit.In order to form the source electrode 101 and drain electrode 102 with tortuous limit, above-mentioned secondary light shielding part can as shown in Fig. 7 or Fig. 9, including the first sub-light shielding part 2031 being arranged on 202 1 limits of exposure region, and the second sub-light shielding part 2032 being arranged on another limit of exposure region 202.
When be positioned at the area of secondary light shielding part 203 of an exposure region 202 account for exposure region 202 area 37.5% time, shape and the set-up mode of the first sub-light shielding part 2031 and the second sub-light shielding part 2032 is illustrated.
Such as, as it is shown in fig. 7, the first sub-light shielding part 2031 and the second sub-light shielding part 2032 are oppositely arranged, and there is between relative the first sub-light shielding part 2031 and the second sub-light shielding part 2032 gap of 1 μm.First sub-light shielding part 2031 and the second sub-light shielding part 2032 are the isosceles triangle of 3 μ m 1.5 μm.
In the case, when resolution R=4 μm of exposure machine, adopting the TFT that above-mentioned mask plate 20 is formed as shown in Figure 6, the protuberance 1011 on the tortuous limit of source electrode 101 is symmetrical arranged with the protuberance 1021 on the tortuous limit of drain electrode 102.Source electrode 101 and drain electrode 102 ultimate range dmaxBeing 4 μm, minimum range is 1 μm.
Again such as, as it is shown in figure 9, the first sub-light shielding part 2031 and the second sub-light shielding part 2032 are crisscross arranged, and there is between adjacent the first sub-light shielding part 2031 and the second sub-light shielding part 2032 gap of 1 μm.Spacing between adjacent two the first sub-light shielding parts 2031 or adjacent two the second sub-light shielding parts 2032 is 3 μm.First sub-light shielding part 2031 and the second sub-light shielding part 2032 are the square of 1.5 μ m 1.5 μm.
In the case, when resolution R=4 μm of exposure machine, adopting the TFT that above-mentioned mask plate 20 is formed as shown in Figure 8, the protuberance 1011 on the tortuous limit of source electrode 101 is crisscross arranged with the protuberance 1021 on the tortuous limit of drain electrode 1021.Ultimate range d between source electrode 101 and drain electrode 102maxBeing 2.5 μm, minimum range is 1 μm.
In sum, when adopting such as Fig. 7 or the making TFT of mask plate as described in Figure 9, on the one hand, the distance of source electrode 101 and drain electrode 102 can be reduced under avoiding the premise improving exposure machine resolution, to reduce the area occupied of TFT, raising pixel aperture ratio.On the other hand, owing to two limits that source electrode 101 is relative with drain electrode 102 are tortuous limit, therefore can increase the width W of TFT channel, be beneficial to the channel width-over-length ratio W/L improving TFT.
Need illustrate time, above-mentioned is with the first sub-light shielding part 2031 and the second sub-light shielding part 2032 for isosceles triangle, the explanation that square carries out for example, and above-mentioned sub-light shielding part can also be other triangle or trapezoidal in addition, or rectangle in addition to square, this is not limited by the present invention.
The above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (16)
1. a pattern pair, it is characterised in that including the first strip pattern and the second strip pattern, the ultimate range between described first strip pattern and described second strip pattern is less than the 125% of default resolution；
Wherein, described default resolution is the resolution for making the described pattern exposure machine to adopting.
2. pattern pair according to claim 1, it is characterised in that the ultimate range between described first strip pattern and the second strip pattern is less than or equal to default resolution；Described default resolution is 4 μm.
3. a TFT, it is characterised in that the source electrode of described TFT and drain electrode constitute pattern pair as claimed in claim 1 or 2；
Wherein, described source electrode is the first strip pattern, and described drain electrode is the second strip pattern.
4. TFT according to claim 3, it is characterised in that at least one limit in two limits that described source electrode is relative with described drain electrode is tortuous limit.
5. TFT according to claim 4, it is characterised in that two limits that described source electrode is relative with described drain electrode are tortuous limit；
Protuberance on the tortuous limit of described source electrode is symmetrical arranged with the protuberance on the tortuous limit of described drain electrode.
6. TFT according to claim 4, it is characterised in that two limits that described source electrode is relative with described drain electrode are tortuous limit；
Protuberance on the tortuous limit of described source electrode is crisscross arranged with the protuberance on the tortuous limit of described drain electrode.
7. the TFT according to claim 5 or 6, it is characterised in that the protuberance on the tortuous limit of described source electrode is triangle, trapezoidal or rectangle with the protuberance on the tortuous limit of described drain electrode.
8. the method for making the TFT as described in any one of claim 3-7, it is characterised in that including:
Underlay substrate is formed metal level；
Described metal level being carried out mask exposure etching, forms source electrode and the drain electrode of described TFT, the ultimate range between described source electrode and drain electrode is less than the 125% of default resolution；
Wherein, described default resolution is that described mask exposure etching that described metal level is carried out forms the resolution of the exposure machine adopted in the step of pattern pair.
9., for making the mask plate adopted of the TFT as described in any one of claim 3-7, described mask plate includes shading region and exposure region, it is characterised in that be provided with secondary light shielding part in described exposure region；Ultimate range between adjacent shading region is less than the 125% of default resolution.
10. mask plate according to claim 9, it is characterised in that the ultimate range between adjacent shading region is less than or equal to default resolution；Described default resolution is 4 μm.
11. mask plate according to claim 9, it is characterised in that described secondary light shielding part includes the first sub-light shielding part being arranged on one limit of described exposure region, and is arranged at the second sub-light shielding part on another limit of described exposure region.
12. mask plate according to claim 11, it is characterised in that described first sub-light shielding part and described second sub-light shielding part are oppositely arranged, and have gap between relative described first sub-light shielding part and described second sub-light shielding part.
13. mask plate according to claim 12, it is characterised in that described first sub-light shielding part and described second sub-light shielding part are isosceles triangle, and the waist of described isosceles triangle is 1.5 μm；The relative gap between described first sub-light shielding part and described second sub-light shielding part is 1 μm.
14. mask plate according to claim 11, it is characterised in that described first sub-light shielding part and described second sub-light shielding part are crisscross arranged, and have gap between adjacent described first sub-light shielding part and described second sub-light shielding part.
15. mask plate according to claim 14, it is characterised in that described first sub-light shielding part and described second sub-light shielding part are the square that the length of side is 1.5；
Spacing between adjacent two described first sub-light shielding parts or adjacent two described second sub-light shielding parts is 3 μm；
1 μm of gap between adjacent described first sub-light shielding part and described second sub-light shielding part.
16. according to the mask plate described in any one of claim 9-15, it is characterised in that be positioned at that the area of the secondary light shielding part of same exposure region accounts for the area of described exposure region 37%～38%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610340807.9A CN105789328A (en) | 2016-05-19 | 2016-05-19 | Pattern pair, TFT (Thin Film Transistor) and manufacturing method thereof, and mask plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610340807.9A CN105789328A (en) | 2016-05-19 | 2016-05-19 | Pattern pair, TFT (Thin Film Transistor) and manufacturing method thereof, and mask plate |
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| CN201610340807.9A Pending CN105789328A (en) | 2016-05-19 | 2016-05-19 | Pattern pair, TFT (Thin Film Transistor) and manufacturing method thereof, and mask plate |
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| US20070161184A1 (en) * | 2005-11-23 | 2007-07-12 | Do Young Kim | Liquid crystal display array board and method of fabricating the same |
| CN101562199A (en) * | 2009-06-02 | 2009-10-21 | 友达光电股份有限公司 | Thin-film transistor structure |
| CN102749801A (en) * | 2012-06-29 | 2012-10-24 | 北京京东方光电科技有限公司 | Mask plate |
| CN103149790A (en) * | 2013-02-22 | 2013-06-12 | 京东方科技集团股份有限公司 | Mask plate |
| KR20130131899A (en) * | 2012-05-25 | 2013-12-04 | 엘지디스플레이 주식회사 | Photo mask |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070161184A1 (en) * | 2005-11-23 | 2007-07-12 | Do Young Kim | Liquid crystal display array board and method of fabricating the same |
| CN101562199A (en) * | 2009-06-02 | 2009-10-21 | 友达光电股份有限公司 | Thin-film transistor structure |
| KR20130131899A (en) * | 2012-05-25 | 2013-12-04 | 엘지디스플레이 주식회사 | Photo mask |
| CN102749801A (en) * | 2012-06-29 | 2012-10-24 | 北京京东方光电科技有限公司 | Mask plate |
| CN103149790A (en) * | 2013-02-22 | 2013-06-12 | 京东方科技集团股份有限公司 | Mask plate |
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Application publication date: 20160720 |