CN105789306B

CN105789306B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN105789306B
Application number: CN201510747034.1A
Authority: CN
Inventors: 张哲诚; 林志翰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2015-01-12
Filing date: 2015-11-05
Publication date: 2020-12-08
Anticipated expiration: 2035-11-05
Also published as: CN105789306A

Abstract

The invention provides a FinFET semiconductor device including a fin structure extending in a first direction and extending from an isolation insulating layer. The FinFET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, sidewall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the sidewall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered with the sidewall insulating layer and the interlayer dielectric layer. At least a portion of the gate electrode layer and the gate dielectric layer fill the recess. The invention also provides a method of manufacturing a semiconductor device.

Description

Semiconductor device and method for manufacturing the same

RELATED APPLICATIONS

This application claims priority to U.S. provisional application No. 62/102557 filed on 12/1/2015, and is continued as part of U.S. application No. 14/621,805 filed on 13/2/2015, the contents of which are incorporated herein by reference.

Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device having a fin structure and a manufacturing process thereof.

Background

As the semiconductor industry moves into nanotechnology process nodes in the process of pursuing higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as fin field effect transistors (finfets). FinFET devices typically include semiconductor fins having a higher aspect ratio, and the channel and source/drain regions of the semiconductor transistor device are formed in the fins. The gate is formed over and along the fin structure (e.g., wrapped around), thereby producing faster, more reliable, and better controlled semiconductor transistor devices by virtue of the increased surface area of the channel and source/drain regions. Metal gate structures are commonly used in FinFET devices along with high-k gate dielectrics having a high dielectric constant, and are fabricated by gate replacement techniques.

Disclosure of Invention

According to an aspect of the present invention, there is provided a semiconductor device including: a FinFET device, comprising: a fin structure extending in a first direction and extending from the isolation insulating layer; and a gate stack including a gate electrode layer, a gate dielectric layer, sidewall insulating layers disposed at both vertical sides of the gate electrode layer, and an interlayer dielectric layer disposed at vertical sides of the sidewall insulating layers, the gate stack being disposed over the isolation insulating layer and covering a portion of the fin structure, the gate stack extending in a second direction perpendicular to the first direction, wherein: a recess is formed in an upper surface of the isolation insulating layer not covered with the sidewall insulating layer and the interlayer dielectric layer, and at least a portion of the gate electrode layer and at least a portion of the gate dielectric layer fill the recess.

Preferably, the lateral ends of the concave portions respectively protrude below the sidewall insulating layers.

Preferably, the recess has a curved profile in a cross section along the first direction.

Preferably, a width of an upper portion of the recess in the first direction is largest.

Preferably, a width of a middle portion of the recess in the first direction is largest.

Preferably, a width of a lower portion of the recess in the first direction is largest.

Preferably, the gate electrode includes a metal material, and the metal material exists under the sidewall insulating layer.

Preferably, the gate dielectric layer comprises a high-k dielectric material, and the high-k dielectric material is present under the sidewall insulating layer.

Preferably, the depth of the recess from an interface plane between the isolation insulating layer and the sidewall insulating layer or an interface plane between the isolation insulating layer and the interlayer dielectric layer is in a range of 1nm to 200 nm.

According to another aspect of the present invention, there is provided a semiconductor device including: a FinFET device, comprising: a first fin structure extending in a first direction and extending from the isolation insulating layer; and a first gate stack including a first gate electrode layer, a first gate dielectric layer, a first sidewall insulating layer disposed at both vertical sides of the first gate electrode layer, and a first interlayer dielectric layer disposed at a vertical side of the first sidewall insulating layer, the first gate stack disposed over the isolation insulating layer and covering a portion of the first fin structure, the first gate stack extending in a second direction perpendicular to the first direction; a second fin structure extending in the first direction and extending from the isolation insulating layer; a second gate stack including a second gate electrode layer, a second gate dielectric layer, a second sidewall insulating layer disposed at both vertical sides of the second gate electrode layer, and a second interlayer dielectric layer disposed at a vertical side of the second sidewall insulating layer, the second gate stack disposed over the isolation insulating layer and covering a portion of the second fin structure, the second gate stack extending in the second direction perpendicular to the first direction; and an isolation plug isolating the first gate stack and the second gate stack, wherein: a first recess formed in an upper surface of the isolation insulating layer not covered by the first sidewall insulating layer, the second sidewall insulating layer, and the first and second interlayer dielectric layers, a second recess formed in an upper surface of the isolation insulating layer not covered by the first sidewall insulating layer, the second sidewall insulating layer, and the first and second interlayer dielectric layers, at least a portion of the first gate electrode layer and at least a portion of the first gate dielectric layer filling the first recess, and at least a portion of the second gate electrode layer and at least a portion of the second gate dielectric layer filling the second recess.

Preferably, both lateral ends of the first recess in the first direction respectively protrude below the first sidewall insulating layer.

Preferably, a width of the recess in the first direction is largest at an upper portion of the recess.

Preferably, a width of the recess in the first direction is largest at a middle portion of the recess.

Preferably, a width of the recess in the first direction is largest at a lower portion of the recess.

Preferably, a lateral end of the first recess in the second direction protrudes below the isolation plug.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a fin structure over a substrate, the fin structure extending in a first direction and exposed from an isolation insulating layer; forming a dummy gate structure over a portion of the fin structure, the dummy gate structure including a dummy gate layer, sidewall insulating layers disposed at both vertical sides of the dummy gate layer, and an interlayer dielectric layer disposed at a vertical side of the sidewall insulating layers, the dummy gate structure being disposed over the isolation insulating layer; removing the dummy gate layer to create a space; etching a surface of the isolation insulating layer in the space to form a recess; and forming a gate structure in the space and the recess.

Preferably, a surface of the isolation layer is etched to form the recess, the recess is formed such that a lateral end of the recess protrudes below the sidewall insulating layer, and the recess has a curved profile in a cross section along the first direction.

Drawings

Various aspects of the invention are better understood from the following detailed description when read with the accompanying figures. Note that, in accordance with industry standard practice, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Figures 1A-1J are cross-sectional views of various stages in the formation of a semiconductor structure according to some embodiments of the present invention;

FIGS. 2A and 2B are cross-sectional views of semiconductor structures according to some embodiments of the present invention;

FIGS. 3A and 3B are cross-sectional views of semiconductor structures according to some embodiments of the present invention;

fig. 4A is an exemplary cross-sectional view of a semiconductor FET device (FinFET) having a fin structure according to one embodiment of the present invention, fig. 4B is an exemplary top view of the semiconductor FET device having the fin structure, and fig. 4C is an exemplary perspective view of the semiconductor FET device having the fin structure corresponding to the enclosed portion in fig. 4B;

5A-5E illustrate exemplary perspective views of the encircled portion of FIG. 4C in accordance with some embodiments of the invention;

6A-6G illustrate exemplary cross-sectional views of the encircled portion of FIG. 4C in accordance with some embodiments of the invention; and

fig. 7-17 illustrate an exemplary process for fabricating a FinFET device according to some embodiments of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the inventive subject matter. Specific examples of components or arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed in the first and second features such that the first and second portions are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," etc.) may be used for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "made of can mean" including "or" consisting of.

Embodiments of semiconductor structures and methods of forming the same are provided. The semiconductor structure may include a gate structure formed by a "gate last" process. That is, the dummy gate is first formed and thereafter replaced with a gate structure. After the dummy gate structure is removed, a portion of the isolation insulating layer is also removed so that a subsequently formed gate structure may extend into the isolation insulating layer and thus the performance of the structure may be improved.

Fig. 1A-1J are cross-sectional views of various stages for forming a semiconductor structure 100, according to some embodiments. As shown in fig. 1A, a substrate 102 is raised according to some embodiments. The substrate 102 may be a semiconductor wafer such as a silicon wafer. Alternatively, the substrate 102 may include: another elemental semiconductor (such as germanium); compound semiconductors including group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In one embodiment, the substrate 102 is a silicon layer of an SOI (silicon on insulator) substrate. When an SOI substrate is used, the fin structure may protrude from a silicon layer of the SOI substrate or may protrude from an insulating layer of the SOI substrate. In the latter case, the silicon layer of the SOI substrate is used to form the fin structure. An amorphous substrate such as amorphous Si or amorphous SiC or an insulating material such as silicon oxide may also be used as the substrate 102. The substrate 102 may include various regions that are appropriately doped with impurities (e.g., p-type or n-type conductivity species).

In fig. 1A-3B, a FinFET device may include one gate structure disposed over one fin structure, forming an isolated FinFET. Note that the term "isolation" means a distance from the other FinFET in one of the X and Y axis directions of greater than 5 × (the width of the channel layer of the fin structure). In some embodiments, an isolated FinFET may include multiple gate electrodes for one fin structure or one gate electrode for multiple fin structures.

According to some embodiments, as shown in fig. 1A, a dielectric layer 104 and a mask layer 106 are formed over a substrate 102, and a photosensitive layer 108 is formed over the mask layer 106. The dielectric layer 104 may serve as an adhesion layer between the substrate 102 and the mask layer 106. In addition, the dielectric layer 104 may also serve as an etch stop layer when the mask layer 106 is etched. In some embodiments, the dielectric layer 104 is made of silicon oxide. The dielectric layer 104 may be formed using a thermal oxidation process, although other deposition processes may be used in some other applications.

The mask layer 106 may be used as a hard mask during a subsequent photolithography process. In some embodiments, mask layer 106 is made of silicon nitride. The mask layer 106 may be formed by using Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), although other deposition processes may also be used in some other embodiments.

Next, according to some embodiments, a fin structure 110 is formed by sequentially etching the mask layer 106, the dielectric layer 104, and the substrate 102 using the photosensitive layer 108, as shown in fig. 1B. Thereafter, the photosensitive layer 108 is removed.

According to some embodiments, as shown in fig. 1C, after forming the fin structure 110, an insulating layer 112 is formed to cover the fin structure 110 over the substrate 102. In some embodiments, the insulating layer 112 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), or other low-k dielectric material. The insulating layer 112 may be formed using a High Density Plasma (HDP) CVD process, although other deposition processes may be used in other embodiments.

Next, according to some embodiments, as shown in fig. 1D, the insulating layer 112 is recessed to form an isolation insulating layer 114, such as a shallow trench isolation insulating layer, around the fin structure 110. The insulating layer 112 may be recessed by a wet etching process or a dry etching process. In addition, the mask layer 106 and the dielectric layer 104 are removed.

Thereafter, according to some embodiments, as shown in fig. 1E, a dielectric layer 116 is formed to cover the fin structure 110 and the isolation insulating layer 114, and a dummy gate structure 118 is formed over the fin structure 110.

In some embodiments, dielectric layer 116 is made of silicon nitride, silicon oxide, silicon oxynitride, or other applicable dielectric materials. Dielectric layer 116 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin coating, or other applicable processes. The thickness of the dielectric layer 116 is in the range of about 1nm to 5 nm.

A dummy gate structure 118 is formed across the fin structure 110 and extends over the isolation insulating layer 114. In some embodiments, the dummy gate structures 118 are made of polysilicon. In some embodiments, the thickness of the polysilicon layer is in the range of about 5nm to about 100 nm.

According to some embodiments, after forming the dummy gate structures 118, spacers 120 are formed on both sidewalls of the dummy gate structures 118. As shown in fig. 1E, the dummy gate structure 118 is formed on the first portion 116a of the dielectric layer 116, and the spacer is formed on the second portion 116b of the dielectric layer 116.

Since the spacers 120 are formed on the sidewalls of the dummy gate structures 118, each spacer 120 has a first height H substantially equal to the height of the dummy gate structure 118₁。

In some embodiments, the spacers 120 are made of one or more layers of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials. The spacer 120 may include a single layer or multiple layers.

Next, according to some embodiments, source/drain structures 122 are formed in the fin structure 110, as shown in fig. 1F. More specifically, the portions of the dielectric layer 116 not covered by the dummy gate structures 118 and the spacers 120 are removed. As shown in fig. 1F, a first portion 116a of the dielectric layer 116 underlying the dummy gate structure 118 and a second portion 116b of the dielectric layer 116 are not removed in this step. After removing the exposed dielectric layer 116, portions of the fin structure 110 adjacent to the dummy gate structures 118 are recessed to form recesses on both sides of the fin structure 110. Next, the process is repeated. A strained material is grown in the recess by an epitaxial process. Further, the lattice constant of the strained material may be different from the lattice constant of the substrate 102. In some embodiments, source/drain structure 122 includes one or more layers of Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, and the like.

According to some embodiments, as shown in fig. 1G, after forming the source/drain structures 122, a Contact Etch Stop Layer (CESL)124 is formed over the substrate 102, and an inter-layer dielectric (ILD) layer 126 is formed on the contact stop layer 124. In some embodiments, the contact etch stop layer 124 is made of one or more layers of silicon nitride, silicon oxynitride, and/or other applicable materials. The contact etch stop layer 124 may be formed by plasma enhanced CVD, low pressure CVD, ALD, or other applicable processes.

The interlayer dielectric layer 126 may include multiple layers made of one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, Fluorinated Silicon Glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide. The interlayer dielectric layer 126 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin coating, or other applicable processes.

Next, according to some embodiments, a polishing process is performed on the interlayer dielectric layer 126 and the contact etch stop layer 124 to expose the top surface of the dummy gate structure 118. In some embodiments, a Chemical Mechanical Polishing (CMP) process is performed until the top surface of the dummy gate structures 118 is exposed.

According to some embodiments, after performing a polishing process, the dummy gate structure 118 is removed, forming a trench 128, as shown in fig. 1H. In some embodiments, the dummy gate structure 118 is removed by performing a dry etch process. In some embodiments, the dummy gate structure 118 is removed by performing a dry etch process and a wet etch process. As shown in fig. 1H, the bottom surface of each spacer 120 is substantially flush with the bottom surface of the groove 128. By removing the dummy gate structure 118, the channel layer of the fin structure 110 is exposed. In some embodiments, after removing the dummy gate structures 118, an additional sidewall insulating layer may be formed inside the trenches 128 and on the spacers 120.

According to some embodiments, as shown in fig. 1I, after removing the dummy gate structure 118, the first portion 116a of the dielectric layer 116 exposed by the trench 128 and the upper portion of the isolation insulating layer 114 under the first portion 116a of the dielectric layer 116 are removed. In some embodiments, the first portion 116a of the dielectric layer 116 is removed by a first etching process, and the upper portion of the isolation insulating layer 114 is removed by a second etching process. In some embodiments, the first portion 116a of the dielectric layer 116 and the upper portion of the isolation insulating layer 114 are removed by the same etching process.

As shown in fig. 1I, since the upper portion of the isolation insulating layer is removed, the trench 128 further extends into the isolation insulating layer 114 to form an extension trench 129 such that the bottom surface of each spacer 120 is not flush with (e.g., higher than) the bottom surface of the extension trench 129. In some embodiments, the sidewalls of the portion of the extension trench 129 below the dielectric layer 116 may have a flat profile as shown in fig. 1I. In other embodiments, the sidewalls may have a curved profile as shown later in fig. 5C-5E.

According to some embodiments, as shown in fig. 1J, after removing an upper portion of the isolation insulating layer 114 to form the extension trench 129, a metal gate structure 130 is formed in the extension trench 129. In some embodiments, metal gate structure 130 includes a gate dielectric layer 132, a work function metal layer 134, and a metal gate electrode layer 136.

In some embodiments, the gate dielectric layer 132 is made of one or more layers of high-k dielectric material. Examples of high-k dielectric materials may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, silicon oxides, silicon nitrides, silicon oxynitrides, zirconium oxides, titanium oxides, aluminum oxides, or hafnium oxide-aluminum oxide (HfO)₂-Al₂O₃) And (3) alloying.

According to some embodiments, a work function metal layer 134 is formed over the gate dielectric layer 132. The work function metal layer 134 is tailored to have an appropriate work function. For example, if a P-type work function metal (P-metal) is desired for a PMOS device, one or more layers of TiN, WN, or W may be used. On the other hand, if an N-type work function metal (N metal) is desired for the NMOS device, one or more layers of TiAl, TiAlN, or TaCN may be used.

According to some embodiments, a metal gate electrode layer 136 is formed over the work function metal layer 134. In some embodiments, metal gate electrode layer 136 is made of one or more layers of conductive materials, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials. Gate dielectric layer 132, work function metal layer 134, and metal gate electrode layer 136 may be formed to any suitable thickness by any suitable process.

It should be noted that additional layers, such as liners, interfacial layers, seed layers, adhesion layers, barrier layers, etc., may be formed over and/or under gate dielectric layer 132, work function metal layer 134, and metal gate electrode layer 136. In addition, the gate dielectric layer 132, the work function metal layer 134, and the metal gate electrode layer 136 may include more than one layer of multiple layers made of various materials.

As shown in figure 1J of the drawings,a metal gate structure 130 is formed across fin structure 110 and extends over isolation insulating layer 114. More specifically, the metal gate structure 130 includes a first portion 130a formed over the fin structure 110 and a second portion 130b formed over the isolation insulating layer 114. Since the upper portion of the isolation insulation layer 114 is removed so that the extension trench 129 may extend into the isolation insulation layer 114, the second portion 130b of the metal gate structure 130 formed over the extension trench 129 may also extend into the isolation insulation layer 114. In addition, the second portion 130b of the metal gate structure 130 has a second height H₂Which is greater than the first height H of the spacer 120₁。

More specifically, the second portion 130b includes an extension portion 130c extending into the insulating isolation layer 114. The formation of the extension portion 130c may enlarge the effective area of the metal gate structure 130 and/or may be used to adjust the electrical characteristics of the semiconductor structure 100. As shown in FIG. 1J, the extension 130c has a thickness T₁It may also be defined as a first height H₁And a second height H₂The difference of (a). In some embodiments, the first thickness T of the extension portion 130c₁In the range of about 1nm to about 200 nm. Although the formation of the extension 130c may enlarge the effective area of the structure, the risk of leakage may also increase if the extension 130c is too thick.

Thickness T of extension 130c₁It can be adjusted by changing the etching time for etching the isolation insulating layer 114. In some embodiments, the thickness T of the extension 130c₁In the range of about 3nm to about 30 nm. In some embodiments, the thickness T of the extension 130c₁In the range of about 3nm to about 80 nm. In some embodiments, the thickness T of the extension 130c₁In the range of about 80nm to about 120 nm. In some embodiments, the thickness T of the extension 130c₁In the range of about 120nm to about 150 nm. In some embodiments, the thickness T of the extension 130c₁In the range of about 150nm to about 200 nm. The extension portions 130c having different thicknesses may have different electrical characteristics, and thus the thickness T of the extension portions 130c₁May be varied according to its applicationAnd (6) adjusting the rows. In some embodiments, the bottom surface of gate structure 130 is substantially flush with the bottom surface of fin structure 110 or lower than the bottom surface of fin structure 110. Optionally, the bottom surface of gate structure 130 is higher than the bottom surface of fin structure 110.

Fig. 2A-2B are cross-sectional views of various stages for forming a semiconductor structure 100' according to some embodiments. The methods and materials used to form the semiconductor structure 100' are similar to or the same as the methods and materials used to form the semiconductor structure 100 described in fig. 1A-1J, except that the extended portion of the metal gate structure extends further under the spacers.

More specifically, the processes of fig. 1A to 1H are performed, and thus, the details are not repeated here. According to some embodiments, as shown in fig. 2A, after removing the dummy gate structure 118, the trench 128 is extended further into the isolation insulating layer 114 by etching the dielectric layer 116 and the isolation insulating layer 114 to form an extended trench 129'.

Similar to that shown in fig. 1I, the first portion 116a of the dielectric layer 116 exposed by the trench 128 and the upper portion of the isolation insulating layer 114 below the first portion 116a of the dielectric layer 116 are removed. In addition, some portions of the second portion 116b of the dielectric layer 116 and of the isolation insulating layer 114 below the spacer 120 are also removed. In some embodiments, the sidewalls of the portion of the extension trench 129' below the spacer 120 may have a flat profile as shown in fig. 2A. In other embodiments, the sidewalls may have a curved profile as shown later in fig. 5C-5E and 6D-6F.

According to some embodiments, after the etching process, the extension trench 129 ' extends further below the spacer 120, as shown in fig. 2A, such that the metal gate structure 130 ' formed in the extension trench 129 ' also extends below the spacer 120, as shown in fig. 2B. In some embodiments, the metal gate structure 130' is similar to the metal gate 130 shown in fig. 1J and includes a gate dielectric layer 132, a work function metal layer 134, and a metal gate electrode layer 136.

As shown in fig. 2B, a metal gate structure 130' is formed across fin structure 110 and extends over isolation insulating layer 114. More specifically, the metal gate structure 130 ' includes a first portion 130a ' formed over the fin structure 110 and a second portion 130b ' formed over the isolation insulating layer 114. In addition, the second portion 130b 'further includes an extension portion 130 c' extending into the isolation insulating layer 114 and extending below the spacer 120.

More specifically, the extension portion 130c 'extends to a position below the spacer 120 such that a portion of the extension portion 130 c' overlaps the spacer 120. In some embodiments, the portion of the extension portion 130c 'that overlaps the spacer 120 has a width W' in the range of about 0.5nm to about 10nm, or in other embodiments in the range of 1nm to 5 nm. Forming the extension portion 130 c' extending to a position below the spacer 120 can enlarge the effective area of the structure. However, if the width W' is too large, the risk of bridging also increases.

As shown in fig. 2B, the width of the extension portion 130c ' is greater than the width of the first portion 130a ' of the metal gate structure 130 ' formed over the fin structure 110. In some embodiments, the first portion 130a ' of the metal gate structure 130 ' has a first width W1 ', and the extension portion 130c ' of the metal gate structure 130 ' has a second width W2 ' that is greater than the first width W1 '. In some embodiments, the difference between the first width W1 'and the second width W2' is in the range of about 0.5nm to about 20 nm. The electrical characteristics may be adjusted by changing the second width W2 'of the extension portion 130 c'. However, if the second width W2 'of the extension portion 130 c' is too large, the risk of leakage may increase.

Similar to that shown in fig. 1J, the second portion 130b 'of the metal gate structure 130 has a second height H2' that is greater than the first height H1 of the spacers 120. In addition, extension 130c 'has a thickness T1', which may also be defined as the difference between first height H1 'and second height H2'. In some embodiments, the range of thickness T1 'of extension portion 130 c' is similar to or the same as the range of thickness T1 of extension portion 130c previously described.

Fig. 3A and 3B are cross-sectional views of various stages in forming semiconductor structure 100 "in accordance with some embodiments. The methods and materials used to form the semiconductor structure 100 "are similar to or the same as the methods or materials used to form the previously described semiconductor structures 100 and 100', except that the second portion of the dielectric layer formed under the spacers is completely removed and the extension portion extends under the spacers.

More specifically, the processes shown in fig. 1A to 1H are performed, and thus, the details are not repeated here. According to some embodiments, as shown in fig. 3A, after removing the dummy gate structure 118, the trench 128 is extended further into the isolation insulating layer 114 by etching the dielectric layer 116 and the isolation insulating layer 114 to form an extended trench 129 ″.

Similar to that shown in fig. 1I, the first portion 116a of the dielectric layer 116 exposed by the trench 128 and the upper portion of the isolation insulating layer 114 below the first portion 116a of the dielectric layer 116 are removed. In addition, the second portion 116b of the dielectric layer 116 and the portion of the isolation insulating layer 114 under the spacer 120 are also removed. That is, in this embodiment, the dielectric layer 116 shown in fig. 1F is completely removed. In some embodiments, the sidewalls of the portion of the extension trench 129 ″ that is below the spacer 120 may have a flat profile as shown in fig. 3A. In other embodiments, the sidewalls may have a curved profile as shown later in fig. 5C-5E and 6D-6F.

According to some embodiments, as shown in fig. 3A, after the etching process, the extension trench 129 "extends further below the spacer 120, and a metal gate structure 130" is formed in the extension trench 129 "(as shown in fig. 3B). In some embodiments, the metal gate structure 130 ″ is similar to the metal gate structure 130 shown in fig. 1J and includes a gate dielectric layer 132, a work function metal layer 134, and a metal gate electrode layer 136.

As shown in fig. 3B, a metal gate structure 130 "is formed across fin structure 110 and extends over isolation insulating layer 114. More specifically, the metal gate structure 130 "includes a first portion 130 a" formed over the fin structure 110 and a second portion 130b "formed over the isolation insulating layer 114. In addition, the second portion 130b ″ further includes an extension portion 130c ″ extending into the isolation insulating layer 114 and extending under the spacer 120.

As shown in fig. 3B, the second portion of the dielectric layer 116 formed under the spacer 120 is completely removed, and a portion of the extension portion 130c ″ overlapping the spacer 120 has a width W ″ substantially equal to the width of the spacer 120. In some embodiments, the width W ″ of the portion of the extension portion 130c overlapping the spacer 120 is in the range of about 0.5nm to about 10 nm.

In some embodiments, the first portion 130a "of the metal gate structure 130" has a first width W1 "and the extension portion 130 c" of the metal gate structure 130 "has a second width W2" that is greater than the first width W1 ". In some embodiments, the difference between the first width W1 "and the second width W2" is in the range of about 0.5nm to about 20 nm.

Similar to that shown in fig. 1J, the second portion 130b "of the metal gate structure 130 has a second height H2" that is greater than the first height H1 of the spacers 120. In addition, extension 130c "has a thickness T1," which may also be defined as the difference between first height H1 and second height H2. In some embodiments, the range of thickness T1 "of extension portion 130 c" is similar to or the same as the range of thickness T1 of extension portion 130c previously described.

In planar transistors, the electrical characteristics can be controlled by implantation. However, it becomes difficult for the FinFET transistor to control the electrical characteristics by implantation. Thus, in some embodiments of the present disclosure, metal gate structures, such as

metal gate structures

130, 130', and 130 ", are used to tune the electrical characteristics of the structures.

More specifically, the metal gate structure is formed in a "gate last" process. That is, the dummy gate structure 118 is formed to cross the fin structure 110 and extend over the isolation insulating layer 114, and the spacers 120 are formed on sidewalls of the dummy gate structure 118. Thereafter, the dummy gate structure 118 and a portion of the isolation insulating layer 114 are removed to form extension trenches (such as the

extension trenches

129, 129', 129 "). Accordingly, the metal gate structure formed in the extension trench may have extension portions, such as the

extension portions

130c, 130 c', and 130c ″ that extend into the isolation insulating layer 114.

The extension portion of the metal gate structure provides a larger effective area for the metal gate structure, and thus may improve the performance of the semiconductor structure (such as a FinFET structure). Furthermore, the extension portion may also be used to adjust the electrical characteristics of the semiconductor structure. In some embodiments, the extension portion (such as the extension portion) extends further to a position below the spacer to have a larger effective area. That is, the size of the extension portion may be adjusted according to the application.

It should be noted that although relatively taller and larger metal gate structures may also be formed by forming taller and larger dummy gate structures, the process of forming taller dummy gate structures may be more challenging. For example, fins having a high aspect ratio should be formed, and a large amount of the insulating layer should be etched to form a shallow trench isolation insulating layer. These processes can result in poor uniformity and can reduce the yield of the fabricated structures.

On the other hand, by using the processes described in fig. 1A to 3B, a metal gate structure having a relatively large height may be formed without using the above-described processes. Therefore, the uniformity of the manufacturing structure can be improved. Furthermore, the above-described method can be implemented in the manufacturing process of the present invention without using an additional complicated process (such as masking or alignment). Accordingly, the metal gate structure may be formed without changing or affecting other manufacturing processes. Therefore, the performance of the semiconductor structure can be improved, and the yield can be increased.

Fig. 4A to 24C illustrate an exemplary semiconductor device and a method for manufacturing a semiconductor device according to other aspects of the present invention. It should be noted that the same or similar structures, configurations, dimensions, processes, operations, and/or materials as described above with reference to fig. 1A-3B may be used and may be applied to the following embodiments. Conversely, the same or similar structures, configurations, dimensions, processes, operations, and/or materials described in the following embodiments may be used and may be applied to the embodiments described above with reference to fig. 1A through 3B.

Fig. 4A is an exemplary cross-sectional view of a semiconductor FET device (FinFET) having a fin structure according to one embodiment of the present invention, fig. 4B is an exemplary top view of the semiconductor FET device having the fin structure, and fig. 4C is an exemplary perspective view of the semiconductor FET device having the fin structure. Fig. 4A is a sectional view taken along line Y1-Y1' in fig. 4B, and fig. 4C corresponds to the enclosed portion a in fig. 4B. In these figures, some layers/components are omitted for simplicity. Fig. 4A-4C illustrate the device after formation of a metal gate structure.

The FinFET device 1001 includes a first device region 1001A and a second device region 1001B. The first device region 1001A includes one or more first FinFET devices, while the second device region includes one or more second FinFET devices. The channel type of the first FinFET transistor may be the same or different than the channel type of the second FinFET transistor.

In one embodiment, the first device region 1001A includes P-type MOSFETs and the second device region 100B includes n-type MOSFETs. In other embodiments, the first and second device regions comprise p-type MOSFETs, the first and second device regions comprise n-type MOSFETs, or the first and second device regions comprise both p-type and n-type MOSFETs.

The FinFET device 1001 includes, among other things, a substrate 1010, a fin structure 1020, a gate dielectric layer 1030, and a gate electrode 1040. The material used for the substrate is similar to or the same as the material used to form the substrate 102 depicted in fig. 1A.

Fin structure 1020 is disposed over substrate 1010. Fin structure 1020 may be made of the same material as substrate 1010 and may extend continuously from substrate 1010. In this embodiment, the fin structure is made of Si. The silicon layer of fin structure 1020 may be intrinsic to itself or appropriately doped with n-type impurities or p-type impurities.

In fig. 4A, two fin structures 1020 are disposed in each of the first device region 1001A and the second device region 1001B. However, the number of fin structures is not limited to two (or four). The number may be one, two, three or more than five. In addition, one or more dummy fin structures may be disposed adjacent to both sides of the fin structure 1020 to improve pattern fidelity in the patterning process. In some embodiments, the width W11 of fin structure 1020 is in the range of about 5nm to about 40nm, and in particular embodiments may be in the range of about 7nm to about 15 nm. In some embodiments, the height of the fin structure 1020 along the Z-axis direction is in a range of about 100nm to about 300nm, and in other embodiments may be in a range of about 50nm to about 100 nm.

The lower portion of fin structure 1020 below gate electrode 1040 is referred to as the well layer and the upper portion of fin structure 1020 is referred to as the channel layer. Under the gate electrode 1040, the well layer is embedded in the isolation insulation layer 1050, and the channel layer protrudes from the isolation insulation layer 1050. The lower portion of the channel layer may also be embedded into the isolation insulator layer 1050 to a depth of about 1nm to about 5 nm.

In some embodiments, the well layer has a height in a range of about 60nm to about 100nm, and the channel layer has a height in a range of about 40nm to about 60 nm.

In addition, the space between the fin structures 1020 and/or the space between the fin structures and another element formed over the substrate 1010 is filled with an isolation insulating layer 1050 (or so-called "Shallow Trench Isolation (STI)" layer) including an insulating material and an interlayer dielectric layer 1070 disposed over the isolation insulating layer 1050. The insulating material used to isolate the insulating layer 1050 and the interlayer dielectric layer 1070 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine doped silicate glass (FSG), or a low-K dielectric material. The insulating material used to isolate the insulating layer 1050 may be the same as or different from the material of the interlayer dielectric layer 1070.

The channel layer protruding from the isolation insulator layer 1050 in the fin structure 1020 is covered by the gate dielectric layer 1030, and the gate dielectric layer 1030 is further covered by the gate electrode 1040. The portions of the channel layer not covered by the gate electrode 1040 serve as the source and/or drain of the MOSFET (see fig. 4B). Fin structure 1020 extends in a first direction (e.g., an X-axis direction), while gate electrode 1040 extends in a second direction (e.g., a Y-axis direction) that is perpendicular to the first direction.

In some embodiments, the work function adjustment layer may include a first metal material for a p-channel FinFET (e.g., in the first device region 1001A) and a second metal material for an n-channel FinFET (e.g., in the second device region 1001B). For example, the first metal material for an n-channel FinFET may comprise a metal whose work function substantially matches (align) the work function of the substrate conduction band, or at least substantially matches the work function of the conduction band of the channel layer of the fin structure 1020. Similarly, for example, the second metal material for the p-channel FinFET may comprise a metal having a work function that substantially matches the work function of the substrate valence band, or at least that of the valence band of the channel layer of the fin structure 1020. In some embodiments, the work function adjustment layer may optionally comprise a polysilicon layer. The work function adjusting layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjustment layer may be formed independently for the n-channel FinFET and the p-channel FinFET, so that different metal layers may be used.

By appropriately doping impurities in the source and drain regions, the source and drain regions are also formed in the fin structure not covered by the gate electrode 1040. Alloys of Si or Ge with metals such as Co, Ni, W, Ti, or Ta may be formed on source and drain regions 1025. A Si layer and/or SiGe layer may be epitaxially formed in the source-drain region to form a raised source-drain structure and apply appropriate stress to the channel layer.

Furthermore, in some embodiments, sidewall insulating layers 1080 (spacers) are disposed on both vertical sides of the gate electrode 1040. The gate electrode 1040 and the source/drain regions are covered with an interlayer dielectric layer 1070 and necessary wiring and/or via/contact holes are provided to complete the semiconductor device.

In some embodiments, the width W12 of the gate electrode 1040, including the work function adjustment layer 1042 and the metal gate layer 1045, is in the range of about 20nm to 40 nm. In some embodiments, when a plurality of gate electrodes 1040 are arranged along the width direction (see fig. 4B), the pitch of the gate electrodes is in the range of about 60nm to 100 nm.

As shown in fig. 4A to 4C, adjacent gate electrodes 1040 are separated from each other by an isolation plug 1060 made of an insulating material. In the cross section shown in fig. 4A, the isolation plug 1060 has a tapered shape with a reduced top dimension (width) and a larger bottom dimension (width). The width at the top of the isolation plug is less than about 20nm in some embodiments, and may be in the range of about 5nm to about 15nm in some embodiments. The width at the bottom of the isolation plug is less than about 35nm in particular embodiments, and may be in the range of about 10nm to about 30nm in some embodiments. Here, the top of the isolation plug corresponds to the upper surface of the gate electrode 1040, and the bottom of the isolation plug 1060 corresponds to the bottom of the gate dielectric layer 1030 or the interface between the isolation insulating layer 1050 and the interlayer dielectric layer 1070. The insulating material for the isolation plug 1060 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, and may be the same as or different from the material of the insulating material for the isolation insulating layer 1050 and/or the interlayer dielectric layer 1070.

The insulating material for the isolation plug 1060 may be the same as or different from the insulating material for the isolation insulating layer 1050 and/or the interlayer dielectric layer 1070.

In one embodiment of the present invention, the bottom of gate electrode 1040 is embedded into the isolation insulator layer to a depth D11.

Fig. 5A-5E illustrate exemplary perspective views of the encircled portion B of fig. 4C in accordance with some embodiments of the present invention. Fig. 6A-6F illustrate exemplary cross-sectional views of the encircled portion B of fig. 4C along an X-axis direction that does not intersect the fin structures (e.g., between fin structures), according to some embodiments of the invention.

According to one embodiment of the present invention, a recess 1055 is provided in the upper surface of the isolation insulating layer 1050. The recess 1055 is filled with a material constituting the gate electrode 1040. Accordingly, the height H11 of the gate structure 1041, including the gate electrode 1040 and the gate dielectric layer 1030, is greater than the height H12 of the sidewall insulation layer 1080. In one embodiment, the difference D12 between H11 and H12 is in the range of about 1nm to 200 nm. The minimum value of D12 may be any of 1nm, 3nm, 10nm, 80nm, 120nm, or 150nm, and the maximum value of D12 may be any of 5nm, 30nm, 80nm, 120nm, 150nm, or 200 nm.

As shown in fig. 5A and 6A, in one embodiment of the invention, the width W14 of the recess 1055 in the X-axis direction is substantially the same as the width W13 of the gate structure 1041 including the gate electrode 1040 and the gate dielectric layer 1030. As shown in fig. 6B, in some embodiments, the width W15 at the bottom of the recess may be less than W13. The width W15 may be in some embodiments in the range of about 1/2 of W13 to about 2/3 of W13, and in another embodiment may be in the range of about 2/3 of W13 to about 3/4 of W13. The walls of the recess may have a flat profile (straight walls) or a curved profile (curved walls).

In another embodiment of the present invention, as shown in fig. 5B and 6C, the width W16 of the recess 1055 is greater than the width W13 of the gate structure. The walls of the recess may be substantially flat. Since the width W16 is greater than the width W13, the material comprising the gate structure is disposed below the sidewall insulating layer 1080. The interface between the gate structure 1041 and the isolation insulating layer 1050 is located below the sidewall insulating layer 1080. More specifically, the end portion of the metal material constituting the gate electrode 1040 is located below the sidewall insulating layer 1080. The difference between W16 and W13 may be in the range of about 1nm to about 20nm in some embodiments, or about 2nm to about 10nm in other embodiments, and equal to or less than twice the thickness of the sidewall insulating layer 1080. In other words, aw 11 (the difference between the lateral end of the recess 1055 and the side of the sidewall insulating layer 1080) shown in fig. 6C may be in the range of about 0.5nm to about 10nm or in the range of about 1nm to about 5 nm. In a particular embodiment, an end portion of the metal material comprising the gate electrode 1040 may be located below the interlayer dielectric 1070 beyond the sidewall insulating layer 1080. In this case, however, the width W16, W16a, W16b, or W16c should be adjusted to avoid a short circuit between two adjacent gate electrodes under the interlayer dielectric layer 1070.

As shown in fig. 5C-5E and 6D and 6E, in another embodiment of the invention, the maximum width W16a, W16b, or W16C of the recess 1055 is greater than the width W13 of the gate structure, and the walls of the recess 1055 have a curved profile.

In fig. 5C and 6D, starting from the uppermost surface of isolation insulating layer 1050 (the interface layers between isolation insulating layer 1050 and interlayer dielectric 1070 and/or isolation insulating layer 1050 and sidewall insulating layer 1080), maximum width W16a is located at a depth between 0 and 1/3 of D12.

In fig. 5D and 6E, the maximum width W16b is located at a depth between 1/3 and 2/3 of D12, starting from the uppermost surface of the isolation insulating layer 1050.

In fig. 5E and 6F, the maximum width W16c is located at a depth between 2/3 and D12 of D12 from the uppermost surface of the insulating isolation layer 1050.

By the aforementioned structure of the recess in the isolation insulating layer 1050 and the gate electrode material filled in the recess, the surface area of the channel layer of the fin structure covered by the gate electrode can be enlarged. In the structures of fig. 5A, 6A, and 6B, the surface area may be vertically expanded, and in the structures of fig. 5B to 5E and 6C to 6F, the surface area may be vertically and horizontally expanded.

As shown in fig. 6G, the recess 1055 may also extend below the isolation plug 1060 along the Y-axis direction. In fig. 6G, the gate dielectric layer is not shown. The protrusion aw 11' may be in the range of about 0.5nm to about 10nm or about 1nm to about 5 nm. In some embodiments, aw 11' is zero. In particular embodiments, the protrusion amount Δ W11' may be equal to Δ W11 (see FIG. 6C) or less than Δ W11. However, in another embodiment, the protrusion amount aw 11' may be greater than aw 11. The depth D11' is substantially the same as the depth D12 shown in fig. 6A-6C, and the recess 1055 below the isolation plug 1060 may also have a shape substantially the same as that shown in fig. 5A-6C. However, in another embodiment, the recess 1055 may not extend below the isolation plug 1060.

Fig. 7-14 illustrate cross-sectional views of an exemplary subsequent operation in fabricating a FinFET device, in accordance with one embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the operations shown in fig. 7-14, and that some of the operations described below may be replaced or omitted for additional embodiments of the method. The order of the operations may be interchanged. Further, the general operation of fabricating a metal gate structure over a fin structure by a gate replacement technique is disclosed in U.S. patent publication No. 2013/016176, the contents of which are incorporated herein by reference.

The operations for fabricating a semiconductor device in this embodiment generally include, among other operations, forming first and second fin structures extending in a first direction. Forming a dummy electrode structure. The dummy electrode structure includes a dummy electrode layer, sidewall insulating layers disposed at both vertical sides of the dummy electrode layer, and interlayer dielectric layers disposed at both vertical sides of the sidewall insulating layers, respectively. The dummy electrode structure is disposed over the isolation insulating layer and extends in a second direction perpendicular to the first direction. The dummy electrode layer is patterned such that the dummy electrode layer is divided into at least a first dummy electrode and a second dummy electrode separated by an opening. The first dummy electrode layer covers a portion of the first fin structure, and the second dummy electrode layer covers the second fin structure. The isolation plug is formed by filling the opening with an insulating material. The first and second dummy electrodes are removed such that a first electrode space and a second electrode space are formed and the isolation plug is exposed between the first electrode space and the second electrode space. The surfaces of the isolation layer in the first and second electrode spaces are etched to form a first recess in the first space and a second recess in the second space. First and second gate structures are formed in the first and second electrode spaces, respectively. The lateral end of at least one of the first recess and the second recess extends into the lower part of the sidewall insulating layer along the first direction. At least one of the first recess and the second recess has a curved profile in a cross-section along the first direction.

To fabricate the fin structure, a mask layer is formed over the substrate 1010, for example by thermal oxidation and/or Chemical Vapor Deposition (CVD). For example, substrate 1010 is a p-type silicon substrate with an impurity concentration of about 1.12 x 10¹⁵cm^-3To about 1.68X 10¹⁵cm^-3Within the range of (1). In other embodiments, substrate 1010 is an n-type silicon substrate with an impurity concentration of about 0.905 x 10¹⁵cm^-3To about 2.34X 10¹⁵cm^-3Within the range of (1). For example, in some embodiments, the mask layer includes a pad oxide (e.g., silicon oxide) layer and a silicon nitride layer.

In some embodiments, the pad oxygen layer has a thickness in a range of about 2nm to about 15nm, and the silicon nitride mask layer has a thickness in a range of about 2nm to about 50 nm. A mask pattern is further formed over the mask layer. The mask pattern is, for example, a photoresist pattern formed by photolithography.

The hard mask pattern 1100 of the pad oxygen layer 1106 and the silicon nitride mask layer 1107 are formed by using the mask pattern as an etching mask. In some embodiments, the width of the hard mask pattern is in a range of about 5nm to about 40 nm. In a particular embodiment, the hard mask pattern has a width in a range of about 7nm to about 12 nm.

As shown in fig. 7, the substrate 1010 is patterned into a fin structure 1020 by using the hard mask pattern as an etching mask and by trench etching using a dry etching method and/or a wet etching method. The height of fin structure 1020 is in a range of about 100nm to about 300 nm. In a particular embodiment, the height is in a range of about 50nm to about 100 nm. When the heights of the fin structures are not uniform, the height from the substrate may be measured from a plane corresponding to the average height of the fin structures.

In this embodiment, a bulk silicon wafer is used as a starting material and constitutes the substrate 1010. However, in some embodiments, other types of substrates may be used as substrate 1010. For example, a silicon-on-insulator (SOI) substrate may be used as a starting material, with the insulating layer of the SOI wafer constituting the substrate 1010 and the silicon layer of the SOI wafer being used for the fin structure 1020.

As shown in fig. 8, an isolation insulating layer 1050 is formed over substrate 1010 to completely cover fin structure 1020.

The isolation insulating layer 1050 includes one or more layers of an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. As the name implies, a flowable dielectric material may "flow" during deposition to fill gaps or spaces having high aspect ratios. Typically, various chemicals are added to the silicon-containing precursor to cause the deposited film to flow. In some embodiments, hydrogen-nitrogen bonds (nitrogen hydride bonds) are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, Methyl Silsesquioxane (MSQ), Hydrogen Silicate (HSQ), MSQ/HSQ, hydrogen silazane peroxide (TCPS), hydrogen peroxide Polysilazane (PSZ), Tetraethylorthosilicate (TEOS), or silyl-amines such as Trisilanylamine (TSA). These flowable silicon oxide materials are formed in a multi-pass process. After the flowable film is deposited, it is cured and then annealed to remove undesirable elements to form silicon oxide. When the undesired elements are removed, the flowable film increases in density and shrinks. In some embodiments, a multiple annealing process is performed. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and/or phosphorus. In some embodiments, the isolation insulating layer 1050 may be formed by one or more layers of SOG, SiO, SiON, SiOCN, and/or fluorine doped silicate glass (FSG).

After the isolation insulating layer 1050 is formed, a planarization operation is performed to remove portions of the isolation insulating layer 1050 and the mask layer 1100 including the pad oxide 1106 and the silicon nitride mask layer 1107. Then, the isolation insulating layer 1050 is further removed, thereby exposing an upper portion of the fin structure 1020 to be a channel layer, as shown in fig. 9.

After the isolation insulating layer 1050 is formed, a thermal process (such as an annealing process) may be performed to improve the quality of the isolation insulating layer 1050. In a particular embodiment, the thermal process is performed using a Rapid Thermal Anneal (RTA) for a time period of about 1.5 seconds to about 10 seconds under temperature conditions in a range of about 900 ℃ to about 1050 ℃ in an inert gas ambient (e.g., N2, Ar, or He ambient).

A sacrificial gate dielectric layer 1105 and a polysilicon layer are formed over the isolation insulating layer 1050 and the exposed fin structure 1020, and then a patterning operation is performed to obtain a polysilicon gate layer 1110 made of polysilicon. Sacrificial gate dielectric layer 1105 may be one or more layers of silicon oxide, silicon nitride, or silicon oxynitride formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, the thickness of the polysilicon layer is in the range of about 5nm to about 100 nm.

Sidewall insulating layers 1080 are also formed at both vertical sides of polysilicon gate layer 1110.

In addition, an interlayer dielectric layer 1070 is formed in the spaces between the polysilicon gate layers 1110 and between the sidewall insulating layers 1080 and over the polysilicon gate layers 1110. A planarization process such as an etch-back process and/or a Chemical Mechanical Polishing (CMP) process is performed to obtain the structures shown in fig. 10A to 10C. Fig. 10A is a cross-sectional view, fig. 10B is a top view, and fig. 10C is a perspective view of the FinFET device after formation of polysilicon gate layer 1110 and interlayer dielectric layer 1070. Fig. 10A is a sectional view taken along line Y1-Y1' in fig. 10B, and fig. 10C corresponds to an enclosed portion C in fig. 10B.

As shown in fig. 10B and 10C, in a particular embodiment, the polysilicon gate layer 1110 is formed in a line-space configuration extending in one direction and having a constant pitch. Polysilicon gate layer 1110 may include another line-space configuration extending in another direction perpendicular to the one direction.

As shown in fig. 11, a mask pattern 1120 is formed over the structure shown in fig. 10C. The mask pattern 1120 is formed, for example, by a photoresist layer having slits 1125. In some embodiments, the width of the slits 1125 is in the range of about 5nm to about 100 nm.

As shown in fig. 12, a portion of the polysilicon gate layer is etched by using the mask pattern 1120. In fig. 12 and subsequent figures, one layer 1070A of the interlayer dielectric layer 1070 is omitted to show the etched polysilicon gate layer 1110, while the

other layers

1070B and 1070C are still shown. In some embodiments, the pressure is between 2mTorr and 20mTorr by using a gas (CH)₄、CF₄、CH₂F₂、CHF₃、O₂、HBr、Cl₂、NF₃、N₂And/or He) to perform an etch of the polysilicon gate layer.

The mask pattern 1120 (photoresist pattern) is removed through an ashing process and/or a wet cleaning process.

Fig. 13 shows the structure after forming an opening 1130 that isolates the polysilicon gate layers 1110. In fig. 13, the top surface of the opening 1130 is circular in shape. However, the shape may be a rectangle, a rectangle with rounded corners, or an ellipse according to the size of the structure, the patterning condition of the mask pattern 1120, and/or the etching condition of the polysilicon gate layer 1110.

It should also be noted that the cross-section of the opening 1130 has a tapered shape (which has a larger top dimension and a smaller bottom dimension), a straight shape, or an inverted tapered shape (which has a smaller top dimension and a larger bottom dimension).

An insulating material is formed over the structure shown in fig. 13, for example, by using a CVD process, and the opening 1130 is filled with the insulating material. In some embodiments, the CVD process may include an LPCVD process, a plasma CVD process, and/or a flowable CVD process. In a flowable CVD process, in some embodiments, a gas including SiH may be used₄、NH₃、N₂、O₂、N₂O、Cl₂And/or NO₂And the deposition is performed at a temperature in a range of about 200 ℃ to about 1000 ℃.

After unnecessary portions of the insulating material formed over the polysilicon gate layer, the sidewall insulating layer, and the interlayer dielectric layer are removed by a planarization operation, as shown in fig. 14, an isolation plug 1060 is obtained. The planarization operation may include a CMP and/or etch back process.

After the isolation plug 1060 is formed, the polysilicon gate layer 1110 is removed by dry etching and/or wet etching. As shown in fig. 15, the isolation plug 1060 is exposed by removing the polysilicon gate layer 1110. Since the upper portion of fin structure 1020 is covered by gate oxide 1105, fin structure 1020 is not etched during the polysilicon gate etch process.

As shown in fig. 16 (which is an enlarged view of surrounding portion B in fig. 15), the sacrificial gate dielectric layer 1105 and a part of the isolation insulating layer 1050 are etched away. By this etching, recesses 1055 are formed in the isolation insulating layer 1050 adjacent to the fin structures 1020, and in some embodiments below the sidewall insulating layer 1080. The etching process may include isotropic dry etching. For example, at low pressure conditions of about 1Torr to 100Torr, a process gas (including CH) is used₂F₂、SF₆、O₂、HBr、He、Cl₂、NF₃、CF₄And/or N₂) Transformer Coupled Plasma (TCP).

In one embodiment, the depth of the recess 1055 in the upper surface of the isolation insulating layer 1050 is in the range of about 1nm to about 200 nm. The minimum value of the depth of the recess may be any of 1nn, 3nm, 10nm, 80nm, 120nm, or 150nm, and the maximum value of the depth of the recess may be any of 5nm, 30nm, 80nm, 120nm, 150nm, or 200 nm.

In one embodiment of the present invention, the width of the recess in the X-axis direction is substantially the same as the width of the space formed by the sidewall insulating layer 1080. In some embodiments, the width at the bottom of the recess may be less than the width of the space. In some embodiments, the width of the recess bottom may be in the range of about 1/2 to about 2/3 of the space width, while in other embodiments may be in the range of about 2/3 to about 3/4 of the space width. The walls of the recess may be flat or curved.

In another embodiment of the present invention, the width of the recess 1055 is greater than the width of the space formed by the sidewall insulating layer 1080. The walls of the recess 1055 can be substantially flat. Since the width of the recess is larger than the width of the space, the lateral end (X-axis direction) of the recess 1055 is located below the sidewall insulating layer 1080. The difference between the width of the recess and the width of the space may be in the range of about 1nm to about 10nm in some embodiments, or about 1nm to about 5nm in other embodiments, and equal to or less than twice the thickness of the sidewall insulating layer 1080.

In another embodiment of the present invention, the maximum width of the recess 1055 is greater than the width of the space formed by the sidewall insulating layer 1080, and the recess 1055 has a curved profile. Starting from the uppermost surface of the isolation insulating layer 1050 (the interface plane between the isolation insulating layer 1050 and the interlayer dielectric layer 1070 and/or the isolation insulating layer 1050 and the sidewall insulating layer 1080), the maximum width may be at a depth between 0 and 1/3 of the depth of the recess, at a depth between 1/3 and 2/3 of the depth of the recess, or at a depth between 2/3 of the depth of the recess and the bottom of the recess.

After the operation in fig. 16, a metal gate structure is formed in the space between the isolation plugs (created by removing the polysilicon gate layer 1110) and, in some embodiments, under the sidewall insulating layer 1080, resulting in the structure shown in fig. 17 and fig. 5A-5E.

It should be understood that the device shown in fig. 17 may be subjected to further CMOS processes to form various components such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

It is to be understood that not all advantages need be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

By the above-described structure of the recess in the isolation insulating layer and the gate electrode material filled in the recess, the surface area of the channel layer of the fin structure to be covered by the gate electrode can be enlarged. By the above-described structure of the recess (located below the interface plane between the isolation insulating layer and the interlayer dielectric layer) in the isolation insulating layer and the gate electrode material filled in the recess, the surface area of the channel layer of the fin structure to be covered by the gate electrode can be enlarged. The surface area may be enlarged vertically and/or horizontally, which may improve FinFET performance.

According to one aspect of the present disclosure, a semiconductor device includes a FinFET device. The FinFET device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The FinFET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, sidewall insulating layers disposed at two vertical sides of the gate electrode layer, and an interlayer dielectric layer disposed at a vertical side of the sidewall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the sidewall insulating layer and the interlayer dielectric layer. At least a portion of the gate electrode layer and the gate dielectric layer fill the recess.

According to another aspect of the invention, a semiconductor device includes a FinFET device. The FinFET device includes a first fin structure, a first gate stack, a second fin structure, a second gate stack, and an isolation plug separating the first gate stack and the second gate stack. The first fin structure extends in a first direction and extends from the isolation insulating layer. The first gate stack includes a first gate electrode layer, a first gate dielectric layer, first sidewall insulating layers disposed at both vertical sides of the first gate electrode layer, and a first interlayer dielectric layer disposed at the vertical sides of the first sidewall insulating layers. The first gate stack is disposed over the isolation insulating layer, covers a portion of the first fin structure, and extends in a second direction perpendicular to the first direction. The second fin structure extends in the first direction and extends from the isolation insulating layer. The second gate stack includes a second gate electrode layer, a second gate dielectric layer, a second sidewall insulating layer disposed at both vertical sides of the second gate electrode layer, and a second interlayer dielectric layer disposed at a vertical side of the second sidewall insulating layer. The second gate stack is disposed over the isolation insulating layer, covers a portion of the second fin structure, and extends in a second direction perpendicular to the first direction. The first recess is formed in an upper surface of the isolation insulating layer not covered by the first and second sidewall insulating layers and the first and second interlayer dielectric layers. The second recess is formed in an upper surface of the isolation insulating layer not covered by the first and second sidewall insulating layers and the first and second interlayer dielectric layers. At least a portion of the first gate electrode layer and the first gate dielectric layer fill the first recess, and at least a portion of the second gate electrode layer and the second gate dielectric layer fill the second recess.

According to another aspect of the invention, a semiconductor device includes a FinFET device. The FinFET device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The FinFET device also includes an interlayer dielectric layer disposed over the isolation insulating layer. The FinFET device includes a gate stack that includes a gate electrode layer and a gate dielectric layer. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction substantially perpendicular to the first direction. The FinFET device also includes a sidewall insulating layer disposed on an inner wall of the space formed in the isolation insulating layer. The gate stack is disposed in the space. The bottom of the space is located below the bottom of the interlayer dielectric layer.

According to another embodiment of a semiconductor structure and a method for forming a semiconductor structure, a semiconductor structure includes a fin structure and an isolation insulating layer formed around the fin structure. A gate structure is formed across the fin structure and extends over the isolation insulating layer. In addition, the gate structure includes an extension portion extending into the isolation insulating layer, so that the effective area of the structure is increased. In addition, the electrical characteristics of the semiconductor structure may be adjusted by the extension portion of the gate structure, and the performance and uniformity of the semiconductor structure may be improved.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure also includes an isolation insulating layer formed around the fin structure and a gate structure formed across the fin structure. Further, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation insulating layer, and the second portion of the gate structure includes an extension portion extending into the isolation insulating layer.

The extension portion of the second portion of the gate structure may have a thickness in a range of about 1nm to about 200 nm. The semiconductor structure may further include spacers formed on sidewalls of the second portion of the gate structure. The spacers do not extend into the isolation insulating layer. In some embodiments, a bottom surface of the spacer is not flush with a bottom surface of the second portion of the gate structure above the isolation insulating layer. The spacers may have a first height and the second portion of the gate structure has a second height greater than the first height. A dielectric layer is formed under the spacer and in direct contact with the gate structure. The first portion of the gate structure may have a first width, and the extension portion of the second portion of the gate structure may have a second width greater than the first width. The difference between the first width and the second width is in a range of about 0.5nm to about 20 nm. The gate structure may have a bottom surface that is substantially flush with or lower than a bottom surface of the fin structure.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure also includes an isolation insulating layer formed around the fin structure and a gate structure formed across the fin structure and extending over the isolation insulating layer. The semiconductor structure also includes spacers formed on sidewalls of the gate structure. In addition, the portion of the spacer formed on the sidewall of the gate structure above the isolation insulating layer has a first height, and the portion of the gate structure formed above the isolation insulating layer has a second height greater than the first height.

The difference between the first height and the second height may be in a range of about 1nm to about 200 nm. A dielectric layer may be formed under the spacers and in direct contact with the gate structure. The portion of the gate structure formed over the shallow trench may include an extension portion extending into the isolation insulating layer. The extension portion may further extend to a position below the spacer such that a portion of the extension portion of the gate structure overlaps the spacer.

In some embodiments, a method for fabricating a semiconductor structure is provided. The method for fabricating a semiconductor structure includes: forming a fin structure over a substrate; and forming an isolation insulating layer over the substrate surrounding the fin structure. The method for fabricating the semiconductor structure further includes forming a dummy gate structure across the fin structure. The method for fabricating the semiconductor structure further includes forming spacers on sidewalls of the dummy gate structure. The method for fabricating the semiconductor structure further includes removing the dummy gate structure to form trenches between the spacers. The method for fabricating a semiconductor structure further includes removing a portion of the isolation insulating layer to form an extension trench extending into the isolation insulating layer, and forming a gate structure in the extension trench, wherein a portion of the gate structure extends into the isolation insulating layer.

The spacer over the isolation insulating layer may have a first height, and the gate structure over the isolation insulating layer may have a second height greater than the first height. In some embodiments, the dielectric layer may be formed prior to forming the dummy gate structures and the spacers, such that the dummy gate structures are formed on a first portion of the dielectric layer and the spacers are formed on a second portion of the dielectric layer. Further, the first portion of the dielectric layer may be removed after removing the dummy gate structure. The second portion of the dielectric layer may be in direct contact with the gate structure. Further, in some embodiments, a portion of the second portion may be removed after removing the dummy gate structure. A portion of the extension groove may further extend to a position below the spacer. In forming the gate structure in the trench, a gate dielectric layer may be formed over a bottom surface and sidewalls of the trench, a work function metal layer may be formed over the gate dielectric layer, and a metal gate electrode layer may be formed over the work function metal layer.

In another embodiment, a semiconductor device including a FinFET device is fabricated by the operations set forth above. The FinFET device includes: a fin structure extending in a first direction and extending from the isolation insulating layer; an interlayer dielectric layer disposed over the isolation insulating layer; and a gate stack including a gate electrode layer and a gate dielectric layer. The gate stack is disposed over the isolation insulating layer and covers a portion of the fin structure. The gate stack extends in a second direction perpendicular to the first direction. The FinFET device also includes a sidewall insulating layer disposed on an inner side of the space formed in the isolation insulating layer. The gate stack is disposed within the space. The bottom surface of the space is located below the bottom of the interlayer dielectric layer. In a cross section along the first direction, a vertical cross section between a material constituting the gate stack and the isolation insulating layer under the sidewall insulating layer has a curved shape.

The above discussion of features of the various embodiments is presented to enable a person skilled in the art to better understand various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a FinFET device, comprising:

a fin structure formed over the substrate, extending in a first direction and exposed from the isolation insulating layer; and

a gate stack including a gate electrode layer, a gate dielectric layer, sidewall insulating layers disposed at both vertical sides of the gate electrode layer, and an interlayer dielectric layer disposed at vertical sides of the sidewall insulating layers, the gate stack being disposed over the isolation insulating layer and covering a portion of the fin structure, the gate stack extending in a second direction perpendicular to the first direction,

a source/drain region formed in a portion of the fin structure not covered by the gate stack and extending in a third direction perpendicular to the substrate, wherein the third direction is perpendicular to the first direction and the second direction, wherein:

forming a recess in an upper surface of the isolation insulating layer not covered by the sidewall insulating layer and the interlayer dielectric layer, and at least a portion of the gate electrode layer and at least a portion of the gate dielectric layer fill the recess,

lateral ends of the recesses respectively protrude below the sidewall insulating layers such that sidewalls of the fin structure, in which a channel region is covered with the gate electrode layer, have surface areas enlarged in a horizontal direction and a vertical direction, wherein bottom surfaces of the sidewall insulating layers are in contact with an upper surface of the gate dielectric layer,

a dielectric layer disposed between the isolation insulating layer and at least one of the sidewall insulating layers,

wherein the gate dielectric layer is in direct contact with the dielectric layer and at least one of the sidewall insulating layers,

wherein a lateral end of the recess is located at a region outside the source/drain region in the second direction and at the same level as the source/drain region in the third direction.

2. The semiconductor device of claim 1, wherein the recess has a curved profile in a cross-section along the first direction.

3. The semiconductor device according to claim 2, wherein a width of an upper portion of the recess in the first direction is largest.

4. The semiconductor device according to claim 2, wherein a width of a middle portion of the concave portion in the first direction is largest.

5. The semiconductor device according to claim 2, wherein a width of a lower portion of the recess in the first direction is largest.

6. The semiconductor device according to claim 1, wherein the gate electrode layer comprises a metal material, and wherein the metal material is present under the sidewall insulating layer.

7. The semiconductor device of claim 1, wherein the gate dielectric layer comprises a high-k dielectric material, and the high-k dielectric material is present under the sidewall insulating layer.

8. The semiconductor device of claim 1, wherein a depth of the recess from an interface plane between the dielectric layer and the sidewall insulating layer is in a range of 1nm to 200 nm.

9. A semiconductor device, comprising:

a FinFET device, comprising:

a first fin structure formed over the substrate, extending in a first direction and exposed from the isolation insulating layer; and

a first gate stack including a first gate electrode layer, a first gate dielectric layer, a first sidewall insulating layer disposed at both vertical sides of the first gate electrode layer, and a first interlayer dielectric layer disposed at a vertical side of the first sidewall insulating layer, the first gate stack disposed over the isolation insulating layer and covering a portion of the first fin structure, the first gate stack extending in a second direction perpendicular to the first direction;

a first source/drain region formed in a portion of the first fin structure not covered by the first gate stack and extending in a third direction perpendicular to the substrate, wherein the third direction is perpendicular to the first direction and the second direction;

a second fin structure formed over the substrate, extending in the first direction and exposed from the isolation insulating layer;

a second gate stack including a second gate electrode layer, a second gate dielectric layer, a second sidewall insulating layer disposed at both vertical sides of the second gate electrode layer, and a second interlayer dielectric layer disposed at a vertical side of the second sidewall insulating layer, the second gate stack disposed over the isolation insulating layer and covering a portion of the second fin structure, the second gate stack extending in the second direction perpendicular to the first direction; and

an isolation plug isolating the first gate stack and the second gate stack, wherein:

a first recess formed in an upper surface of the isolation insulating layer not covered by the first sidewall insulating layer, the second sidewall insulating layer, and the first interlayer dielectric layer and the second interlayer dielectric layer,

a second recess formed in an upper surface of the isolation insulating layer not covered by the first sidewall insulating layer, the second sidewall insulating layer, and the first interlayer dielectric layer and the second interlayer dielectric layer,

at least a portion of the first gate electrode layer and at least a portion of the first gate dielectric layer fill the first recess, and

at least a portion of the second gate electrode layer and at least a portion of the second gate dielectric layer fill the second recess, wherein both lateral ends of the first recess in the first direction respectively protrude below the first sidewall insulating layer such that a sidewall of the first channel region of the first fin structure covered by the first gate electrode layer has a surface area that expands in a horizontal direction and a vertical direction, wherein a bottom surface of the first sidewall insulating layer is in contact with an upper surface of the first gate dielectric layer,

a dielectric layer disposed between the isolation insulating layer and at least one of the first sidewall insulating layers,

wherein the first gate dielectric layer is in direct contact with the dielectric layer and at least one of the first sidewall insulating layers,

wherein both lateral ends of the first recess in the first direction are located at a region other than the first source/drain region in the second direction and at the same level as the first source/drain region in the third direction.

10. The semiconductor device according to claim 9, wherein the first recess has a curved profile in a cross section along the first direction.

11. The semiconductor device according to claim 9, wherein a width of the first recess in the first direction is largest at an upper portion of the first recess.

12. The semiconductor device according to claim 9, wherein a width of the first recess in the first direction is largest at a middle portion of the first recess.

13. The semiconductor device according to claim 9, wherein a width of the first recess in the first direction is largest at a lower portion of the first recess.

14. The semiconductor device of claim 9, wherein a lateral end of the first recess in the second direction extends below the isolation plug.

15. A method of manufacturing a semiconductor device, comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and exposed from an isolation insulating layer;

forming a dummy gate structure over a portion of the fin structure, the dummy gate structure including a dummy gate layer and sidewall insulating layers disposed at two vertical sides of the dummy gate layer, the dummy gate structure being disposed over the isolation insulating layer and extending in a second direction perpendicular to the first direction;

forming source/drain regions in portions of the fin structure not covered by the dummy gate structure, the source/drain regions extending in a third direction perpendicular to the substrate, the third direction being perpendicular to the first direction and the second direction;

forming an interlayer dielectric layer at a vertical side of the sidewall insulating layer;

removing the dummy gate layer to create a space;

etching a surface of the isolation insulating layer in the space to form a recess; and

forming a gate structure including a gate electrode layer and a gate dielectric layer in the space and the recess, wherein the recess is formed such that a lateral end of the recess protrudes below the sidewall insulating layer such that a sidewall of the fin structure, in which a channel region is covered by the gate structure, has a surface area that expands in a horizontal direction and a vertical direction, wherein a bottom surface of the sidewall insulating layer is in contact with an upper surface of the gate structure,

forming a dielectric layer covering the fin structure and the isolation insulating layer after forming the fin structure and before forming a dummy gate structure, wherein the dielectric layer is disposed between the isolation insulating layer and at least one of the sidewall insulating layers,

16. The method of claim 15, wherein the recess has a curved profile in a cross-section along the first direction.

17. The method of claim 16, wherein the depth of the recess from the interface plane between the dielectric layer and the sidewall insulating layer is in the range of 1nm to 200 nm.

18. The method of claim 16, wherein a width of the recess in the first direction is greatest at a middle of the recess.