CN105789301B - Fin field effect transistor, fin structure and manufacturing method thereof - Google Patents
Fin field effect transistor, fin structure and manufacturing method thereof Download PDFInfo
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- CN105789301B CN105789301B CN201410827222.0A CN201410827222A CN105789301B CN 105789301 B CN105789301 B CN 105789301B CN 201410827222 A CN201410827222 A CN 201410827222A CN 105789301 B CN105789301 B CN 105789301B
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- silicon fin
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 230000005669 field effect Effects 0.000 title claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 74
- 239000010703 silicon Substances 0.000 claims abstract description 74
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 12
- 235000019441 ethanol Nutrition 0.000 claims description 6
- 239000003792 electrolyte Substances 0.000 claims description 4
- 238000005868 electrolysis reaction Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 230000005518 electrochemistry Effects 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical group [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of a fin structure, which comprises the following steps: providing a semiconductor substrate, wherein a silicon fin is formed on the semiconductor substrate; forming a hole on the surface of the silicon fin; an epitaxial layer is formed on the silicon fin, the epitaxial layer being a group III or group V semiconductor material. According to the invention, partial crystal lattices of the fin are deformed by the holes, and after different groups of epitaxial layers are formed on the fin, partial stress caused by lattice mismatching can be absorbed, so that the stress between the fin and the epitaxial layer is released.
Description
Technical field
The invention belongs to a kind of field of semiconductor manufacture more particularly to fin formula field effect transistor, fin structure and its manufactures
Method.
Background technology
Highly integrated with semiconductor devices, MOSFET channel length constantly shortens, a series of in MOSFET long raceway grooves
Negligible effect becomes more significantly in model, or even as the leading factor of device performance is influenced, this phenomenon is referred to as
For short-channel effect.Short-channel effect can deteriorate the electric property of device, such as cause threshold voltage of the grid decline, power consumption increase with
And the problems such as signal-to-noise ratio decline.
In order to overcome short-channel effect, it is proposed that the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-
FET is the transistor for having fin channel structure, and several surfaces of the thin fin of this kind of devices use are as raceway groove, so as to prevent
Short-channel effect in conventional transistor, while operating current can be increased.
In the manufacturing process of fin formula field effect transistor, the manufacture of fin is very important part, and fin is wished as raceway groove
Its mobility higher is hoped to obtain faster device speed, current fin mainly etches to be formed by silicon substrate, then, can be with
By the semi-conducting material of the extension iii-v on fin, to improve the carrier mobility of raceway groove.
The problem, however, is that since there are the mismatches of lattice between the semi-conducting material and silicon of iii-v, each other it
Between there is stress, it is difficult on silicon fin formed iii-v semiconductor layer.
Invention content
It is an object of the invention to overcome deficiency in the prior art, a kind of fin formula field effect transistor, fin structure are provided
And its manufacturing method, reduce storeroom stress not of the same clan.
To achieve the above object, the technical scheme is that：
A kind of manufacturing method of fin structure, including step：
Semiconductor substrate is provided, silicon fin is formed in the semiconductor substrate；
Hole is formed on silicon fin and substrate surface；
Epitaxial layer is formed on silicon fin and substrate surface, which is the semi-conducting material of III group or V races.
Optionally, the silicon fin is adulterated with p-type, and using electrochemical etching method, hole is formed on the surface of fin.
Optionally, the electrolyte of electrochemical electrolysis method is the mixed solution of HF and ethyl alcohol, and the mixed proportion of HF and ethyl alcohol is
1:1。
Optionally, the semiconductor substrate is silicon substrate, forms fin by etching silicon substrate, and before forming fin, also
Including step：The p-type doping at angle of inclination is carried out to substrate.
Optionally, angle of inclination is 6 °.
Optionally, it after silicon fin surface forms hole, is formed before epitaxial layer on silicon fin, further includes step：In silicon fin
Upper formation epitaxial buffer layer.
In addition, the present invention also provides a kind of manufacturing method of fin formula field effect transistor, using any of the above-described method shape
At fin structure.
In addition, the present invention also provides a kind of fin structures, including：
Semiconductor substrate；
There is hole on the surface of silicon fin on substrate, the silicon fin and substrate；
Epitaxial layer on silicon fin and substrate, the epitaxial layer are the semi-conducting material of III group or V races.
Optionally, further include epitaxial buffer layer between epitaxial layer and silicon fin.
In addition, the present invention also provides a kind of fin formula field effect transistor, including any of the above-described fin structure.
Fin formula field effect transistor, fin structure and its manufacturing method of the present invention, forms hole, hole on the surface of silicon fin
So that the part lattice of silicon fin deforms, after being formed on epitaxial layer not of the same clan, can absorb partially due to lattice not
Stress caused by matching discharges the stress of silicon fin and extension interlayer.
Description of the drawings
It, below will be to attached drawing needed in the embodiment in order to illustrate more clearly of the technical solution that the present invention is implemented
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, other drawings may also be obtained based on these drawings.
Fig. 1 is the manufacturing method flow chart according to the fin structure of the present invention；
Fig. 2-Fig. 6 A are the device in each manufacturing process for manufacture fin formula field effect transistor according to the embodiment of the present invention
Structural schematic diagram, wherein Fig. 2-Fig. 6 is vertical view, and Fig. 2A-6A are the AA of corresponding vertical view to schematic cross-section.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, three-dimensional space that should be comprising length, width and depth in actual fabrication.
The present invention proposes a kind of manufacturing method of fin structure, including：Semiconductor substrate is provided, in the semiconductor substrate
It is formed with silicon fin；Hole is formed on silicon fin surface；Epitaxial layer is formed on silicon fin, which is the semiconductor of III group or V races
Material.
In the present invention, hole is formd on the surface of silicon fin, hole makes the part lattice of silicon fin deform, on it
After forming epitaxial layer not of the same clan, it can absorb partially due to stress caused by lattice mismatches, release silicon fin and extension interlayer
Stress.
Technical solution in order to better understand the present invention and technique effect, below with reference to specific flow diagram figure
1 pair of specific embodiment is described in detail.
First, semiconductor substrate 100 is provided, silicon fin 110 is formed in the semiconductor substrate 100, with reference to figure 2 and Fig. 2A
Shown in (AA of Fig. 2 to schematic cross-section).
In embodiments of the present invention, the semiconductor substrate 100 can be for Si substrates, Ge substrates, SiGe substrate, SOI (absolutely
Silicon on edge body, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc..It is described
Semiconductor substrate can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC etc.,
Can also be laminated construction, such as Si/SiGe etc. can also be other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..
In the present embodiment, the semiconductor substrate is body silicon substrate, and silicon fin is formed by etching body silicon substrate, can be with
Understand, in other embodiments, silicon fin can not be to be formed by etched substrate, for example, growing silicon on substrate
Thick-layer forms silicon fin by etching the thick-layer of silicon.
In the present embodiment, specifically, first, forming mask layer (not shown) on substrate, which can be
For silica, silicon nitride, silicon oxynitride etc. or their lamination, thickness can be
Then, it is masking with the mask layer, the method using RIE (reactive ion etching), etched substrate 100 may be used
To form fin 110, then, wet etching may be used, such as using the mask layer of diluted HF removal silica, thus,
Fin 110 is formed on substrate 100, as shown in Figure 2 A.
Then, in step S02, hole 112 is formed on 110 surface of silicon fin, (AA of Fig. 3 shows to section with reference to figure 3 and Fig. 3 A
It is intended to) shown in.
In the present embodiment, it using electrochemical etching method, etches and portals on the surface of fin, specifically, being adopted in embodiment
The silicon substrate adulterated with p-type, after forming fin so that fin has the doping of p-type, it is preferred that before forming silicon fin, to body silicon
Substrate carries out the doping that angle of inclination is 6 °, and doping particle is, for example, B, Ga or In etc., and then, etching forms the silicon of p-type doping
Fin is then performed etching using electrochemical etching method, and electrolyte is the mixed solution of HF and ethyl alcohol, the mixing ratio of HF and ethyl alcohol
Example is 1:1, above-mentioned device is positioned in electrolyte, after carrying out electrochemical electrolysis, on the surface of substrate 100 and fin 110
Form hole 112, as shown in Fig. 3 and Fig. 3 A, the hole 110 be in irregular distribution, the depth in hole and aperture by etch period and
The conditions such as the concentration of etching solution control, and the density in hole is determined by the density of electric current, after etching, the porosity rate on silicon fin surface
Reach 60% or higher.
In other embodiments, can also using plasma dry etching or reactive ion etching form fin surface
Hole, in etching, by adjusting the carbon fluorine atom number ratio or halogen in the proportioning of etching gas, such as carbon fluorine base gas
Velocity ratio between etching gas and oxidizing gas so that etch as isotropic etching, and change gas flow or match
Than so that lateral etch rate is unequal in Each point in time, to also form porous structure in layer surface.
Then, in step S03, epitaxial layer 120 is formed on fin 110, which is the semiconductor of III group or V races
Material, with reference to shown in figure 4 and Fig. 4 A (AA of Fig. 4 to schematic cross-section).
In the present embodiment, using epi (extension) technique, the growth of epitaxial layer 120, as shown in figs 4 and 4, extension are carried out
In technique, epitaxial material first is filled up into hole 112 and continues epitaxial growth, to form epitaxial layer 120.For silicon fin, the extension
Layer can be the epitaxial layer of the semi-conducting material of III group or V races, for example, GaAs, GaN or GaInP etc., the III group or V races
120 have higher carrier mobility so that device has better performance.
Due to being formed with hole on silicon fin, hole makes the part lattice of silicon fin deform, and is formed on not of the same clan
After epitaxial layer, it can absorb partially due to stress caused by lattice mismatches, discharges the stress of silicon fin and extension interlayer.
More preferably, after forming hole, before formation epitaxial layer, epitaxial buffer layer can be initially formed on silicon fin, and (figure is not
Show), which has the Lattice Matching ability more close with silicon fin compared to epitaxial layer, is directly existed with alleviating
Silicon fin growing epitaxial layers and caused by stress mismatch, such as the epitaxial buffer layer can be SiGe etc..
So far, the fin structure of the embodiment of the present invention is formd.
Then, the following process of device can be completed.As shown in Fig. 5 and Fig. 5 A (AA of Fig. 5 to schematic cross-section), carry out
Isolated material 130, such as the deposit of silica then carry out flatening process, until epitaxial layer 120 is exposed, then,
Carry out part isolated material 130 removal, between fin structure formed isolation 130, as Fig. 6 and Fig. 6 A (AA of Fig. 6 to cut
Face schematic diagram).Then, gate dielectric layer and grid are formed on fin, and forms source-drain area at the both ends of fin, and are subsequently formed
Interlayer dielectric layer and contact and interconnection structure etc..
So far, the fin formula field effect transistor of the embodiment of the present invention is formd.
In addition, the present invention also provides a kind of fin structure, with reference to shown in figure 4 and Fig. 4 A, which includes：Semiconductor serves as a contrast
Bottom 100；Silicon fin 110 on substrate 100 has hole 112 on the surface of the silicon fin 110；Epitaxial layer 120 on silicon fin 110, should
Epitaxial layer is the semi-conducting material of III group or V races.
In an embodiment of the present invention, the semiconductor substrate is body silicon substrate, and the silicon fin is adulterated with p-type.Extension
Layer is the semi-conducting material of III group or V races, for example, GaAs, GaN or GaInP etc..
In irregular distribution, porosity rate can be 60% or higher in hole 110 on silicon fin.
It can also include epitaxial buffer layer between silicon fin and epitaxial layer, such as can be GeSi, to alleviate directly in silicon
Fin growing epitaxial layers and caused by stress mismatch.
In addition, the present invention also provides the fin formula field effect transistor with above-mentioned fin structure, formed between fin structure
There is isolation, gate dielectric layer and grid is formd on fin, and source-drain area is formed at the both ends of fin.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (10)
1. a kind of manufacturing method of fin structure, which is characterized in that including step：
Semiconductor substrate is provided, silicon fin is formed in the semiconductor substrate；
Hole is formed on silicon fin and substrate surface；
Epitaxial layer is formed on silicon fin and substrate surface, which is the semi-conducting material of III group or V races.
2. manufacturing method according to claim 1, which is characterized in that the silicon fin is adulterated with p-type, is carved using electrochemistry
Erosion method forms hole on the surface of silicon fin.
3. manufacturing method according to claim 2, which is characterized in that the electrolyte of electrochemical electrolysis method is HF and ethyl alcohol
The mixed proportion of mixed solution, HF and ethyl alcohol is 1:1.
4. manufacturing method according to claim 2, which is characterized in that the semiconductor substrate is silicon substrate, passes through etching
Silicon substrate forms fin, and further includes step before forming fin：The p-type doping at angle of inclination is carried out to substrate.
5. manufacturing method according to claim 4, which is characterized in that angle of inclination is 6 °.
6. manufacturing method according to claim 1, which is characterized in that after silicon fin surface forms hole, the shape on silicon fin
Further include step before epitaxial layer：
Epitaxial buffer layer is formed on silicon fin.
7. a kind of manufacturing method of fin formula field effect transistor, which is characterized in that using the side such as any one of claim 1-6
Method forms fin structure.
8. a kind of fin structure, which is characterized in that including：
Semiconductor substrate；
There is hole on the surface of silicon fin on substrate, the silicon fin and substrate；
Epitaxial layer on silicon fin and substrate, the epitaxial layer are the semi-conducting material of III group or V races.
9. fin structure according to claim 8, which is characterized in that between epitaxial layer and silicon fin further include epitaxial buffer
Layer.
10. a kind of fin formula field effect transistor, which is characterized in that including fin structure as claimed in claim 8 or 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410827222.0A CN105789301B (en) | 2014-12-25 | 2014-12-25 | Fin field effect transistor, fin structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410827222.0A CN105789301B (en) | 2014-12-25 | 2014-12-25 | Fin field effect transistor, fin structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105789301A CN105789301A (en) | 2016-07-20 |
| CN105789301B true CN105789301B (en) | 2018-09-11 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63182811A (en) * | 1987-01-26 | 1988-07-28 | Seiko Instr & Electronics Ltd | Epitaxial growth method for compound semiconductor |
| CN101317273A (en) * | 2005-12-22 | 2008-12-03 | 国际商业机器公司 | Reduced-resistance FINFET and methods of manufacturing the same |
| CN101989617A (en) * | 2009-07-31 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Fin structure for a semiconductor transistor and its manufacture method |
| CN104009080A (en) * | 2013-02-27 | 2014-08-27 | 台湾积体电路制造股份有限公司 | FinFETs with Strained Well Regions |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7410883B2 (en) * | 2005-04-13 | 2008-08-12 | Corning Incorporated | Glass-based semiconductor on insulator structures and methods of making same |
-
2014
- 2014-12-25 CN CN201410827222.0A patent/CN105789301B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63182811A (en) * | 1987-01-26 | 1988-07-28 | Seiko Instr & Electronics Ltd | Epitaxial growth method for compound semiconductor |
| CN101317273A (en) * | 2005-12-22 | 2008-12-03 | 国际商业机器公司 | Reduced-resistance FINFET and methods of manufacturing the same |
| CN101989617A (en) * | 2009-07-31 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Fin structure for a semiconductor transistor and its manufacture method |
| CN104009080A (en) * | 2013-02-27 | 2014-08-27 | 台湾积体电路制造股份有限公司 | FinFETs with Strained Well Regions |
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| CN105789301A (en) | 2016-07-20 |
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