CN105788641B - Memory device and its operating method - Google Patents
Memory device and its operating method Download PDFInfo
- Publication number
- CN105788641B CN105788641B CN201410802183.9A CN201410802183A CN105788641B CN 105788641 B CN105788641 B CN 105788641B CN 201410802183 A CN201410802183 A CN 201410802183A CN 105788641 B CN105788641 B CN 105788641B
- Authority
- CN
- China
- Prior art keywords
- voltage
- voltages
- threshold voltage
- threshold
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000011017 operating method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 26
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
The invention discloses a kind of memory device and its operating methods.The operating method of memory device includes: to apply an initialization to be biased into multiple storage units, so that these storage units have multiple threshold voltages；And apply multiple write-in voltages respectively to these storage units according to these threshold voltages, so that these storage units change into multiple target threshold voltages by these threshold voltages, wherein these write-in voltages are different from each other.
Description
Technical Field
The invention relates to a memory device and an operation method thereof.
Background
Referring to fig. 14, fig. 14 is a schematic diagram illustrating an original threshold voltage shift. When the memory is not being written to, the correspondence between the number of memory cells and the Threshold Voltage (Vt) is the original Threshold Voltage 80. When the memory has been written, the correspondence between the number of memory cells and the threshold voltage is the target threshold voltage 90. The difference between the original threshold voltage 80 and the target threshold voltage 90 is referred to as the threshold voltage distance (Vt Window) W. In general, the larger the threshold voltage distance W, the better. Further, the width Wp of the target threshold voltage 90 cannot be too large. The width Wp of the target threshold voltage 90 is too large to easily cause the memory to be unreadable.
When writing to a memory cell, a conventional memory uses an Incremental Step Pulse Program (ISPP) algorithm. Incremental step pulse writing is performed by stepping up the word line voltage to write the memory cell. When performing incremental step pulse writing, the memory cell is verified (Verify) once per phase of the write. When the threshold voltage of the memory cell is higher than the verify voltage, the memory cell is not written into the next stage. A memory cell with a slower increase in threshold voltage may require a relatively large number of stages before its threshold voltage can be higher than the verify voltage. That is, the memory cell with the slowly increasing threshold voltage may need to be written with relatively more write voltages before it can be written successfully.
However, when a memory cell is written, the peripheral memory cells are affected. The memory cells that are not originally written into will have their threshold voltage raised because the peripheral memory cells are to be written into. The more times the write voltage is applied, the more the threshold voltage rises. For example, the threshold voltage of the memory cell not being written is changed from the original threshold voltage 80 to the original threshold voltage 80' due to the effect of the peripheral memory cells being written. As a result, the threshold voltage distance W is reduced to the threshold voltage distance W', which results in a decrease in reliability of the memory.
Disclosure of Invention
The invention relates to a memory device and an operation method thereof.
According to the present invention, there is provided a method of operating a memory device, comprising: applying an initialization bias to a plurality of memory cells so that the memory cells have a plurality of threshold voltages; and applying a plurality of writing voltages to the memory cells according to the threshold voltages respectively so that the memory cells are changed from the threshold voltages to a plurality of target threshold voltages, wherein the writing voltages are different from each other.
According to the present invention, a memory device is provided. The memory device includes a memory array, a bias circuit, and control logic. The memory array includes a plurality of memory cells. The bias circuit applies an initialization bias to the memory cells so that the memory cells have a plurality of threshold voltages. The control logic controls the bias circuit to apply a plurality of write voltages to the memory cells respectively according to the threshold voltages, so that the memory cells are changed from the threshold voltages to a plurality of target threshold voltages respectively, wherein the write voltages are different from each other.
In order to better understand the above and other aspects of the present invention, the following detailed description of the preferred embodiments is made with reference to the accompanying drawings, in which:
drawings
FIG. 1 is a block diagram of a memory according to a first embodiment.
Fig. 2 is a flow chart of an operation method according to the first embodiment.
FIG. 3 is a diagram showing the original threshold voltage and n threshold voltages.
FIG. 4 is a diagram of an original threshold voltage and n target threshold voltages.
FIG. 5 is a schematic diagram illustrating the application of n write voltages to n memory cells.
FIG. 6 is a diagram of the original threshold voltage and 6 threshold voltages.
FIG. 7 is a diagram of the original threshold voltage, 1 target threshold voltage and 5 threshold voltages.
FIG. 8 is a diagram of original threshold voltages, 2 target threshold voltages, and 4 threshold voltages.
FIG. 9 is a diagram of the original threshold voltage, the 3 target threshold voltages and the 3 threshold voltages.
FIG. 10 is a diagram of original threshold voltages, 4 target threshold voltages, and 2 threshold voltages.
FIG. 11 is a diagram of the original threshold voltage, 5 target threshold voltages and 1 threshold voltage.
FIG. 12 is a diagram of the original threshold voltage and 6 target threshold voltages.
FIG. 13 is a diagram illustrating voltage variation.
FIG. 14 is a diagram illustrating an original threshold voltage shift.
[ notation ] to show
1: memory device
11: memory array
12: bias circuit
13: control logic
14: decoding and sensing circuit
21-22: step (ii) of
30. 80, 80': original threshold voltage
40(1) -40 (n): threshold voltage
50(1) to 50(n), 90: target threshold voltage
G (1) to G (n): memory cell
Vpgm (1) to Vpgm (n): write voltage
Vs: initialization bias
Δ V (1) to Δ V (n): amount of voltage change
W, W': threshold voltage distance
Detailed Description
First embodiment
Referring to fig. 1, fig. 2, fig. 3, fig. 4 and fig. 5, fig. 1 is a block diagram illustrating a memory according to a first embodiment, fig. 2 is a flowchart illustrating an operating method according to the first embodiment, fig. 3 is a diagram illustrating an original threshold voltage and n threshold voltages, fig. 4 is a diagram illustrating an original threshold voltage and n target threshold voltages, and fig. 5 is a diagram illustrating an application of n write voltages to n memory cells. The memory 1 includes a memory array 11, a bias circuit 12, control logic 13, and a decode and sense circuit 14. The memory array 11 includes a plurality of memory cells and the control logic 13 is, for example, a processor. The decoding and sensing circuit 14 is used for selecting and sensing the memory cells, and the decoding and sensing circuit 14 includes, for example, a column decoder, a row decoder, and a sense amplifier.
The method of operation of the memory 1 comprises the steps of: first, as shown in step 21, the control logic 13 controls the bias circuit 12 to apply the initialization bias Vs to the plurality of memory cells such that the plurality of memory cells have a plurality of threshold voltages.
Then, as shown in step 22, the control logic 13 controls the bias circuit 12 to apply a plurality of write voltages to the memory cells according to the threshold voltages, so that the memory cells are changed from the threshold voltages to a plurality of target threshold voltages, wherein the write voltages are different from each other. And, the write voltages are respectively greater than the threshold voltages of the memory cells.
In step 21, for example, the control logic 13 controls the bias circuit 12 to apply the initialization bias Vs to the n memory cells, so that the n memory cells are changed from the original threshold voltage 30 to the threshold voltages 40(1) to 40(n), respectively. Wherein n is a positive integer greater than 1.
In step 22, for example, the control logic 13 controls the bias circuit 12 to apply the write voltages Vpgm (1) to Vpgm (n) to the memory cells G (1) to G (n), respectively, so that the threshold voltages 40(1) to 40(n) of the memory cells G (1) to G (n) are changed to the target threshold voltages 50(1) to 50(n), respectively. The write voltages Vpgm (1) -Vpgm (n) are different from each other and the write voltages Vpgm (1) -Vpgm (n) are greater than the initialization bias voltage Vs; and the write voltage Vpgm (1) is greater than the threshold voltage 40(1) of memory cell G (1), the write voltage Vpgm (2) is greater than the threshold voltage 40(2) of memory cell G (2), and so on. The write voltage Vpgm (1) is smaller than the write voltage Vpgm (2), and the write voltage Vpgm (2) is smaller than the write voltage Vpgm (3). By analogy, the write voltage Vpgm (n-1) is less than the write voltage Vpgm (n). In short, the larger the threshold voltage offset of a memory cell is, the smaller the corresponding write voltage is. The threshold voltage shift amount represents a shift amount from the original threshold voltage 30 to the threshold voltages 40(1) to 40 (n). That is, in the present embodiment, before the write voltage is applied, a relatively low "initialization bias" is applied in order to generate different threshold voltage offsets for the memory cells.
Note that, although the operation is performed in units of memory cells, the present invention is not limited thereto. In fact, other possible embodiments may perform the operations in units of memory groups, and still be within the spirit of the present invention.
Further, the control logic 13 can select the write voltages Vpgm (1) -Vpgm (n) corresponding to the memory cells G (1) -G (n) in the comparison table, and then control the bias circuit 12 to apply the write voltages Vpgm (1) -Vpgm (n) to the memory cells G (1) -G (n), respectively. The memory cells G (1) to G (n) can be changed from the threshold voltages 40(1) to 40(n) to the target threshold voltages 50(1) to 50(n) by applying the write voltage only once. Even the memory cell G (n) with the minimum change of the threshold voltage of the memory cell can be changed from the threshold voltage 40(n) to the target threshold voltage 50(n) by only applying the write voltage Vpgm (n) once without applying the write voltage for many times. Thus, the reliability degradation caused by the reduction of the Threshold Voltage Window (Threshold Voltage Window) can be avoided.
Referring to fig. 1, 5, 6, 7, 8, 9, 10, 11 and 12, fig. 6 is a schematic diagram of an original threshold voltage and 6 threshold voltages, fig. 7 is a schematic diagram of an original threshold voltage, 1 target threshold voltage and 5 threshold voltages, fig. 8 is a schematic diagram of an original threshold voltage, 2 target threshold voltages and 4 threshold voltages, fig. 9 is a schematic diagram of an original threshold voltage, 3 target threshold voltages and 3 threshold voltages, fig. 10 is a schematic diagram of an original threshold voltage, 4 target threshold voltages and 2 threshold voltages, fig. 11 is a schematic diagram of an original threshold voltage, 5 target threshold voltages and 1 threshold voltage, and fig. 12 is a schematic diagram of an original threshold voltage and 6 target threshold voltages.
For convenience of explanation, the following embodiments are described with n equal to 6 as an example. First, as shown in fig. 1 and 6, an initialization bias Vs is applied to the memory cells, so that the original threshold voltage 30 of the 6 memory cells is changed to the threshold voltages 40(1) to 40(6), respectively. Next, as shown in fig. 5 and 7, a write voltage Vpgm (1) is applied to the memory cell G (1) so that the memory cell G (1) changes from the threshold voltage 40(1) to the target threshold voltage 50 (1). Subsequently, as shown in fig. 5 and 8, the write voltage Vpgm (2) is applied to the memory cell G (2), so that the threshold voltage of the memory cell G (2) is changed from the threshold voltage 40(2) to the target threshold voltage 50 (2). Then, as shown in fig. 5 and 9, the write voltage Vpgm (3) is applied to the memory cell G (3) so that the memory cell G (3) changes from the threshold voltage 40(3) to the target threshold voltage 50 (3).
Next, as shown in fig. 5 and 10, the write voltage Vpgm (4) is applied to the memory cell G (4) so that the memory cell G (4) changes from the threshold voltage 40(4) to the target threshold voltage 50 (4). As shown in fig. 5 and 11, the write voltage Vpgm (5) is applied to the memory cell G (5) such that the threshold voltage of the memory cell G (5) is changed from the threshold voltage 40(5) to the target threshold voltage 50 (5). Then, as shown in fig. 5 and 12, the write voltage Vpgm (6) is applied to the memory cell G (6) so that the memory cell G (6) changes from the threshold voltage 40(6) to the target threshold voltage 50 (6).
Second embodiment
Referring to fig. 1 and fig. 13, fig. 13 is a schematic diagram illustrating a voltage variation. The second embodiment is mainly different from the first embodiment in that the second embodiment does not find out the write voltages Vpgm (1) to Vpgm (n) via a look-up table. In the second embodiment, the control logic 13 calculates the voltage changes Δ V (1) to Δ V (n) from the differences between the threshold voltages 40(1) to 40(n) and the target threshold voltages 50(1) to 50(n), and calculates the write voltages Vpgm (1) to Vpgm (n) from the initialization bias voltage Vs and the voltage changes Δ V (1) to Δ V (n). The write voltages Vpgm (1) to Vpgm (n) are equal to the voltage variations Δ V (1) to Δ V (n), respectively, plus the initialization bias voltage Vs.
For example, when the initialization bias Vs is equal to 10 volts, the threshold voltage 40(1) corresponds to a threshold voltage equal to-1 volt. The target threshold voltage 50(1) corresponds to a threshold voltage equal to 3 volts. The control logic 13 calculates the voltage change Δ V (1) ═ 3- (-1) ═ 4 volts. The control logic 13 calculates the write voltage Vpgm (1) 10+4 14 volts. Similarly, when the initialization bias Vs is equal to 10 volts, the threshold voltage 40(2) corresponds to a threshold voltage equal to-2 volts. The target threshold voltage 50(2) corresponds to a threshold voltage equal to 3 volts. The control logic 13 calculates the voltage change Δ V (1) ═ 3- (-2) ═ 5 volts. The control logic 13 calculates the write voltage Vpgm (2) 10+5 15 volts. By analogy, the control logic 13 can calculate the write voltages Vpgm (3) to Vpgm (n).
The memory and the operating method thereof in the foregoing embodiments only need to apply a write voltage once, so that the plurality of memory cells can all reach the corresponding target threshold voltages. Thus, the reliability degradation caused by the reduction of the threshold voltage Window (threshold voltage Window) can be avoided.
While the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.
Claims (8)
1. A method of operation of a memory device, comprising:
applying an initialization bias to a plurality of memory cells so that the memory cells have a plurality of threshold voltages; and
respectively applying a plurality of writing voltages to the memory cells according to the threshold voltages so that the memory cells are changed from the threshold voltages to a plurality of target threshold voltages, wherein the writing voltages are different from each other;
after the initialization bias voltage is applied to the memory cells, the memory cells are respectively changed from an original threshold voltage to the threshold voltages;
the threshold voltages comprise a first threshold voltage and a second threshold voltage which respectively correspond to a first memory cell and a second memory cell of the memory cells;
the writing voltages include a first writing voltage and a second writing voltage, and the first writing voltage and the second writing voltage are respectively applied to the first memory cell and the second memory cell so that the first memory cell and the second memory cell are respectively changed from the first threshold voltage and the second threshold voltage to a first target threshold voltage and a second target threshold voltage;
a first threshold voltage offset of the first memory cell is greater than a second threshold voltage offset of the second memory cell, and the first write voltage is less than the second write voltage, the first threshold voltage offset being related to a difference between the original threshold voltage and the first threshold voltage, the second threshold voltage offset being related to a difference between the original threshold voltage and the second threshold voltage.
2. The method of operation of claim 1,
the write voltages are greater than the initialization bias voltage; and
the write voltages are respectively greater than the threshold voltages of the memory cells.
3. The method of operation of claim 1, further comprising:
the write voltages corresponding to the memory cells are selected in a look-up table.
4. The method of operation of claim 1, further comprising:
calculating a plurality of voltage variation according to the threshold voltages and the target threshold voltages; and
the write voltages are obtained according to the initialization bias voltage and the voltage variations.
5. A memory device, comprising:
a memory array;
a bias circuit; and
a control logic; wherein,
the memory array includes a plurality of memory cells;
the bias circuit applies an initialization bias to the memory cells, so that the memory cells have a plurality of threshold voltages; and
the control logic controls the bias circuit to apply a plurality of write voltages to the memory cells respectively according to the threshold voltages, so that the memory cells are changed from the threshold voltages to a plurality of target threshold voltages respectively, wherein the write voltages are different from each other;
wherein: after the initialization bias is applied to the memory cells, the memory cells are respectively changed from an original threshold voltage to the threshold voltages;
the threshold voltages comprise a first threshold voltage and a second threshold voltage which respectively correspond to a first memory cell and a second memory cell of the memory cells;
the writing voltages include a first writing voltage and a second writing voltage, and the first writing voltage and the second writing voltage are respectively applied to the first memory cell and the second memory cell so that the first memory cell and the second memory cell are respectively changed from the first threshold voltage and the second threshold voltage to a first target threshold voltage and a second target threshold voltage;
a first threshold voltage offset of the first memory cell is greater than a second threshold voltage offset of the second memory cell, and the first write voltage is less than the second write voltage, the first threshold voltage offset being related to a difference between the original threshold voltage and the first threshold voltage, the second threshold voltage offset being related to a difference between the original threshold voltage and the second threshold voltage.
6. The memory device of claim 5, wherein the write voltages are greater than the initialization bias voltage; and
the write voltages are respectively greater than the threshold voltages of the memory cells.
7. The memory device of claim 5, wherein the control logic selects the write voltages corresponding to the memory cells in a look-up table.
8. The memory device of claim 5, wherein the control logic calculates a plurality of voltage variations according to a difference between the threshold voltages and the target threshold voltages, and obtains the write voltages according to the initialization bias voltage and the voltage variations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410802183.9A CN105788641B (en) | 2014-12-22 | 2014-12-22 | Memory device and its operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410802183.9A CN105788641B (en) | 2014-12-22 | 2014-12-22 | Memory device and its operating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105788641A CN105788641A (en) | 2016-07-20 |
| CN105788641B true CN105788641B (en) | 2019-09-24 |
Family
ID=56384725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410802183.9A Active CN105788641B (en) | 2014-12-22 | 2014-12-22 | Memory device and its operating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105788641B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556144B (en) * | 2018-05-31 | 2021-04-06 | 旺宏电子股份有限公司 | Programming method of memory device |
| US11170853B2 (en) * | 2020-03-04 | 2021-11-09 | Micron Technology, Inc. | Modified write voltage for memory devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8526240B2 (en) * | 2011-08-17 | 2013-09-03 | Ememory Technology Inc. | Flash memory and memory cell programming method thereof |
-
2014
- 2014-12-22 CN CN201410802183.9A patent/CN105788641B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN105788641A (en) | 2016-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8711626B2 (en) | Flash memory apparatus and method for generating read voltage thereof | |
| US9257204B2 (en) | Read voltage setting method, and control circuit, and memory storage apparatus using the same | |
| KR100781041B1 (en) | Flash memory device and method for controlling erase operation of the same | |
| US8045387B2 (en) | Nonvolatile memory device and program method with improved pass voltage window | |
| JP2009020996A (en) | Nonvolatile memory device and reading method | |
| KR20080075749A (en) | Non-volatile memory device having improved read operation and driving method for the same | |
| KR101089967B1 (en) | Non-volatile memory device and method of operating thereof | |
| KR20150029405A (en) | Semiconductor memory device and programming method thereof | |
| KR20170011641A (en) | Semiconductor memory device and operating method thereof | |
| US8743608B2 (en) | Nonvolatile memory apparatus and verification method thereof | |
| KR20170011324A (en) | Semiconductor memory device and operating method thereof | |
| KR20170011644A (en) | Semiconductor memory device and operating method thereof | |
| US20150228332A1 (en) | Method for writing data into flash memory and associated memory device and flash memory | |
| KR20160075064A (en) | Semiconductor memory device and operating method thereof | |
| US20180061503A1 (en) | Memory device and programming method thereof | |
| US9490024B1 (en) | Solid state storage device and reading control method thereof | |
| US20090285020A1 (en) | Method of programming a multi level cell in a non-volatile memory device | |
| KR101775429B1 (en) | Nonvolatile memory device and method of programming the same | |
| US8462554B2 (en) | Over-erase verification and repair methods for flash memory | |
| KR20180016854A (en) | Semiconductor memory device and method for operating the same | |
| CN105788641B (en) | Memory device and its operating method | |
| US8437193B1 (en) | Flash memory data recovery | |
| US9786381B2 (en) | Semiconductor memory device that determines a deterioration level of memory cells and an operation method thereof | |
| CN105989888B (en) | Nonvolatile memory device, method of operating the same, and test system having the same | |
| US10418116B2 (en) | Memory device with control logic configured to group memory blocks, and determine driving voltages to be respectively applied to the groups to control memory operation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |