CN105788633A - Flash memory, memory module, processing system and processing method - Google Patents
Flash memory, memory module, processing system and processing method Download PDFInfo
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Abstract
The invention provides a flash memory, a memory module, a processing system and a processing method. The NAND flash memory (100) comprises a memory array (110) with NAND storage compartments, a controller (150) including a processor and ROM/RAM, and a system clock pulse generating circuit (200) generating an internal system clock pulse. At least a setting command for setting the flash memory is stored in the ROM/RAM, and the processor processes the setting command on the basis of an internal clock pulse signal in the setting period. The controller (150) controls the system clock pulse generating circuit (200) to make the internal system clock pulse signal be generated at a high speed in the setting period.
Description
Technical field
The present invention is the semiconductor storage about a kind of anti-and type flash memory (NANDflashmemory) etc, especially with respect to a kind of flash memory, memory module, process system and processing method that can be arranged flexibly by elastic seasonal pulse method.
Background technology
As the storage medium of the mobile equipment such as portable multi-function terminal (smart mobile phone), flat terminal, utilize and have flash memory.In order to tackle the requirement of this type of low power consumption moving equipment, low power consumption is also required that for flash memory.
Flash memory disclosed in patent documentation 1 (Japanese Patent Laid-Open 2012-190501 publication) monitors from outside supply voltage, when supply voltage being detected lower than specific level, reduce the clock frequency making charge pump for processing, to suppress power consumption.And, flash memory disclosed in patent documentation 2 (Japanese Patent Laid-Open 2013-89138 publication) stop to storage lattice erase process time etc. without the seasonal pulse of state machine of long-term disposal, thus seeking the reduction of power consumption.
Summary of the invention
[inventing problem to be solved]
NAND type flash memory is different from or non-(NOR) type flash memory, and is required the operation of various complexity.Therefore, in NOR type flash memory, generally use the control based on state machine, but in NAND type flash memory, carry out using the control of the processor of executable program data.Routine data is stored in read only memory (ROM, or random access memory (RAM Read-OnlyMemory), Random-accessmemory) in, processor performs from ROM or the RAM routine data read, to control the various process such as memory array cell, peripheral circuit, voltage generation circuit, data input/output.But, even NAND type flash memory, also have and carry out the processor based on state machine.
The process of this kind of processor or the process based on state machine usually synchronously carry out with clock signal.Namely, if the process based on processor, then synchronously the address of program counter is carried out increment with clock signal, from ROM/RAM reading program data one by one, the order of routine data is decoded or processes, if based on the process of state machine, then synchronously perform predetermined process successively with clock signal.Therefore, depending on the frequency of clock signal based on process time of processor or state machine, processor or state machine cannot perform order with the speed that the frequency than clock signal is higher or perform process.
Generally, for NAND type flash memory, himself possesses clock pulse generator in inside, generates built-in system clock signal based on the clock signal produced from clock pulse generator.Or, in the NAND type flash memory of other specifications, from external reception clock signal, use this outside clock signal to generate built-in system clock signal.The frequency of the built-in system clock signal of NAND type flash memory allows for the integrity (noise) of power consumption or signal, and is set in the way of the minimum operation unit of satisfied inside.That is, the frequency of clock signal is more big, then power consumption is more big, and noise is also more big, therefore to consider that these are because usually setting clock frequency.
Fig. 1 is the schematic diagram of the process sequence of the NAND type flash memory of an embodiment in prior art.In the present embodiment, perform operation setting at period T1, perform the pressure of cell array (reading of such as data, program, erase, verify) at ensuing period T2, at ensuing period T3, perform, for the setting verified, to perform verification at ensuing period T4.Processor, at period T1 to T4, uses built-in system clock signal CLK to perform each order.
In NAND type flash memory, process to carry out the pressure to memory array, it is necessary to according to reading, program, erase, verification etc. processes and generate various voltage (such as program voltage Vpp, read voltage Vread, by voltage Vpass, select grid voltage VSGS, VSDG etc.).Generally, flash memory possesses the voltage generation circuit comprising charge pump circuit or level shift circuit etc., uses these circuit to convert the supply voltage supplied from external power terminal to required voltage.In example shown in Fig. 1, illustrate following example: the pressure in order to generate flash memory processes required voltage (Vpp, Vread, Vpass, VSGS, VSDG etc.), at period T1, T3, perform the order of voltage HV1, HV2, HV3, HV4, HV5 after boosting.Corresponding every 1 seasonal pulse of processor and perform 1 order, therefore 5 seasonal pulse of processor needs perform these 5 orders of HV1～HV5.
At period T1, T3, processor performs the order of HV1～HV5, in voltage generation circuit, thus generate pressure process required high voltage, but in order to avoid causing that memory array is adversely affected because of these high voltages, produced high voltage and cell array electrical isolation.When period, T1 terminated, processor at period T2, performs such as to be equivalent to the order of 5 seasonal pulse, thus control flash memory programming, read, erasing etc. processes.At ensuing period T3, being performed the order of HV1～HV5 in the same manner as when period T1 by processor, when period, T3 terminated, at period T4, processor performs such as to be equivalent to the order of 5 seasonal pulse, thus controls verification etc. and processes.
The quantity of the time and the order handled by processor that arrange period T1, T3 is directly proportional, and command number is more many, then time, rapid pulse is more many, and the time of period T1, T3 is more long, and the process time of flash memory is also more long.It is therefore also considered that in arranging period T1, T3, reduce command number by merging several orders.Such as also can as shown in Figure 2 the schematic diagram of process sequence of the NAND type flash memory of another embodiment in prior art (Fig. 2 be), period T1 arrange with in the arranging of period T3, merge the setting command of HV1 and HV2, and merge the setting command of HV3 and HV4, the time rapid pulse thus making period T1, T3 reduces to 3, thus overall time rapid pulse is set to 16.Compared with the situation of Fig. 1, period shortens 4 seasonal pulse, but then, it is necessary to prepares the setting command merging combination possessing HV1 and HV2, HV3 and HV4, HV2 and HV3, HV4 and HV5, correspondingly, causes decoding circuit to increase.
So, in NAND type flash memory of the prior art, the command number that processor can process during arranging is subject to the frequency limitation of system clock signal, therefore, arranges shortage motility.
It is an object of the invention to, solve problem of the prior art, it is provided that a kind of semiconductor storage that can be arranged flexibly by elastic seasonal pulse method.
[solving the technological means of problem]
The present invention provides a kind of flash memory, memory module, process system and processing method.
The NAND type flash memory of the present invention includes: memory array, has NAND storage lattice；Clock signal production part, produces clock signal；Execution unit, receives the clock signal produced by described clock signal production part, and synchronously performs the prespecified process of flash memory with this clock signal；And control parts, arrange in period what described execution unit carried out, control described clock signal production part, so that the frequency high speed of the clock signal produced by described clock signal production part.
Preferably, described execution unit includes memory unit, the storage of described memory unit is for performing the order of the prespecified process of described flash memory, and performs the period for the order arranged at described execution unit, and the frequency of described clock signal is by high speed.It is preferred that described execution unit includes state machine, described state machine performs the prespecified process of described flash memory, and performs the period for the process arranged at described execution unit, and the frequency of described clock signal is by high speed.It is preferred that described control parts judge the presence or absence of described setting based on the signal that enables received from outside terminal.It is preferred that described clock signal production part includes: clock pulse generator, produce clock signal；Multiple circuit, is connected with described clock pulse generator, and described clock signal is doubled；And seasonal pulse selection circuit, it is connected with described clock pulse generator and described multiple circuit, select any one in described clock signal or the clock signal through doubling, clock signal selected by described seasonal pulse selection circuit is supplied to described execution unit, described execution unit, within the period of described setting, performs process based on the clock signal through multiplication.It is preferred that the value that described clock signal is doubled by described control component settings by described multiple circuit, and the control signal output extremely described clock signal production part of the selection of described seasonal pulse selection circuit will be controlled.It is preferred that flash memory includes voltage generation circuit, described voltage generation circuit produces voltage based on the supply voltage supplied from outside terminal, and described execution unit, within the period of described setting, makes described voltage generation circuit produce high voltage.Preferably, described control parts include the table specified with multiple described values arranging multiplication corresponding respectively and the identification component identifying described setting based on described order data, and described multiple circuit is set and the value arranging corresponding multiplication identified by described control parts.
The process system of the present invention is for the setting performed by controller of NAND type flash memory, comprising: the first module, it is determined that the presence or absence of described setting；Second module, when being judged to have described setting, controls clock generating circuit, so that built-in system clock signal only high speed within the period of described setting；And three module, by the described clock signal through high speed, make processor perform the order for described setting.
The processing method of the present invention uses the clock signal in NAND type flash memory, its presence or absence comprising the steps: to judge the setting performed by described anti-and the controller of type flash memory；When being judged to have described setting, control clock generating circuit so that built-in system clock signal only arrange period in high speed；And by the described clock signal through high speed, make processor perform the order for arranging.[invention effect]
According to the present invention, arranging in period, the clock signal through high speed is used to perform setting, therefore, it is possible to suitably set for arranging the process number of accessible setting in period, setting being made to possess motility.And then, compared with prior art, if identical at the process number arranging the setting performed in period, then can shorten the time that period is set, and then the shortening of the access time of flash memory can be realized.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the process sequence of the NAND type flash memory of an embodiment in prior art；
Fig. 2 is the schematic diagram of the process sequence of the NAND type flash memory of another embodiment in prior art；
Fig. 3 is the system structure schematic diagram of the embodiment of the present invention；
Fig. 4 is the structural representation of the NAND type flash memory of the embodiment of the present invention；
Fig. 5 is the structural representation of the NAND string of the embodiment of the present invention；
Fig. 6 is the relation schematic diagram processing and applying between voltage of the flash memory of the embodiment of the present invention；
Fig. 7 is the structural representation of the system clock generation circuit of the embodiment of the present invention；
Fig. 8 is the relation schematic diagram between the kind of the embodiment of the present invention and the value of multiplication；
Fig. 9 is the flow chart that the process of the flash memory of the 1st embodiment to the present invention illustrates；
Figure 10 is the schematic diagram of the process sequence of the controller of the embodiment of the present invention；
Figure 11 is the flow chart that the process of the flash memory of the 2nd embodiment to the present invention illustrates.
Description of reference numerals:
10: system；
20: host apparatus；
30: memory module；
40: storage control；
100: flash memory；
110: memory array；
120: input/output buffer storage；
130: address register；
140: data register；
150: controller；
160: word line selection circuit；
170: page buffer memorizer/sensing circuit；
180: row selection circuit；
190: internal voltage generating circuit；
200: system clock produces circuit；
210: clock pulse generator；
220: multiple circuit；
230: seasonal pulse selection circuit；
Ax: column address information；
Ay: row address information；
C1～C4: control signal；
CLK: built-in system clock signal；
CLKn: clock signal；
GBL0～GBLn: bit line；
HV1～HV5: high voltage；
MC0～MC31: storage lattice；
NU:NAND string location；
S100～S112, S200～S208: step；
SGD, SGS: select gate line；
SL: source electrode line；
T1～T4: period；
TD, TS: select transistor；
WL0～WL31: wordline；
Vers: voltage of erasing；
Vpgm: program voltage；
Vread: read voltage；
Vpass: pass through voltage.
Detailed description of the invention
Hereinafter, embodiments of the present invention are described in detail with reference to the attached drawings.It addition, should be noted that, in accompanying drawing, emphasize for the ease of understanding to represent each several part, with the ratio of actual device differing.
Fig. 3 is the system structure schematic diagram of the embodiment of the present invention.The system 10 of the present embodiment includes host apparatus 20 and is connected to the memory module 30 of this host apparatus 20.Host apparatus 20 is not particularly limited, for electronic installations such as computer, digital camera, printers or be equipped on the chip in chipset.Memory module 30 includes storage control 40 and flash memory 100.Storage control 40 controls the data transmission etc. between host apparatus 20 and flash memory 100.
Fig. 4 is the structural representation of the NAND type flash memory of the embodiment of the present invention.As shown in Figure 4, the flash memory 100 of the present embodiment includes: memory array 110, is formed and is arranged in rectangular multiple storage lattice；Input/output buffer storage 120, is connected to externally input/lead-out terminal I/O, keeps input/output data；Address register 130, receives the address date from input/output buffer storage 120；Data register 140, keeps the data of input/output；Controller 150, producing control signal C1, C2, C3, C4 etc., order data and external control signal (not shown chip enable or address latch enable etc.) that this control signal C1, C2, C3, C4 etc. are based on from input/output buffer storage 120 control each several part；Word line selection circuit 160, is decoded the column address information Ax from address register 130, and carries out the selection of block and the selection etc. of wordline based on decoded result；Page buffer memorizer/sensing circuit 170, keeps the data read via bit line, or keeps routine data etc. via bit line；Row selection circuit 180, is decoded the row address information Ay from address register 130, and carries out the selection etc. of bit line based on this decoded result；Internal voltage generating circuit 190, the voltage generating the reading for carrying out data, program and erasing etc. required (program voltage Vpgm, by voltage Vpass, read voltage Vread, erase voltage Vers etc.)；And system clock produces circuit 200, produce built-in system clock signal CLK.
Fig. 5 is the structural representation of the NAND string of the embodiment of the present invention；As it is shown in figure 5, in 1 memory block, be formed with multiple NAND string location NU being connected in series by multiple storage lattice, in 1 block, it is arranged with n+1 NAND string location NU along column direction.NAND string location NU includes: multiple storage lattice MCi of being connected in series (i=0,1 ..., 31)；Bit line selection transistor TD, is connected to one of them end and namely stores the drain side of lattice MC31；And source electrode line selects transistor TS, it is connected to another end and namely stores the source side of lattice MC0.The drain electrode of bit line selection transistor TD is connected to 1 bit lines GBLi of correspondence, and (i=0,1 ..., n), source electrode line selects the source electrode of transistor TS to be connected to shared source electrode line SL.
The control gate of storage lattice MCi is connected to wordline WLi, selects the grid of transistor TD, TS to be connected to selection gate line SGD, SGS parallel with wordline WLi (i=0,1 ..., 31).Word line selection circuit 160, when selecting block based on column address Ax, optionally drives selection transistor TD, TS via selection signal SGS, the SGD of this block.
Storage lattice typically have metal-oxide-semiconductor structure, and this metal oxide semiconductor (MOS, Metal-Oxide-Semiconductor) structure includes: as the source/drain of N-type diffusion zone, are formed in P well；Tunnel oxide film, is formed on the raceway groove of source/drain interpolar；Floating grid (charge accumulation layer), is formed on tunnel oxide film；And control gate, formed on the floating gate via dielectric film.When floating grid is not accumulated have electric charge time, when being namely written with data " 1 ", threshold value is in negative state, and storage lattice are normal open.When in floating grid, accumulation has electronics, when being namely written with data " 0 ", threshold transitions is just, storage lattice are normal off.Wherein, storage lattice are not limited to store single position, it is possible to store multiple position.
Fig. 6 is the relation schematic diagram processing and applying between voltage of the flash memory of the embodiment of the present invention.When reading process, bit line is applied certain positive voltage, selected wordline is applied certain voltage (such as 0V), non-selected wordline is applied through voltage Vpass (such as 4.5V), positive voltage (such as 4.5V) is applied to selecting gate line SGD, SGS, make bit line selection transistor TD, source electrode line select transistor TS conducting, common source line is applied 0V.When programming (write) and processing, selected wordline is applied high-tension program voltage Vpgm (15V～20V), to non-selected wordline apply in the middle of by voltage (such as 10V), bit line selection transistor TD is made to turn on, make source electrode line select transistor TS to disconnect, and level corresponding with the data of " 0 " or " 1 " is supplied to bit line GBLi.When erasing process, the selected wordline in block is applied 0V, P well is applied the high-tension voltage Vers (such as 20V) that erases, the electronics of floating grid is drawn to substrate, data of thus erasing in units of block.
Internal voltage generating circuit 190 receives the supply voltage supplied from the external power terminal of flash memory.Internal voltage generating circuit 190 comprises charge pump circuit or level shift circuit etc., and the process of these circuit is the setting command performed by controller 150 and is controlled.
Fig. 7 is the structural representation of the system clock generation circuit of the embodiment of the present invention.System clock produces circuit 200 to be had: clock pulse generator 210, produces the built-in system clock signal CLK of frequency f；Multiple circuit 220, doubles to internal system clock signal CLK based on the control signal C4 carrying out self-controller 150, generates the clock signal CLKn of the frequency of f × n (cycle T/n)；And seasonal pulse selection circuit 230, receive the built-in system clock signal CLK from the clock pulse generator 210 and clock signal CLKn from multiple circuit 220, and select built-in system clock signal CLK or clock signal CLKn.Built-in system clock signal CLK or clock signal CLKn selected by seasonal pulse selection circuit 230 are provided to controller 150., should being noted that, clock signal is carry out via seasonal pulse selection circuit 230 to the supply of controller 150 herein, and in other words, the processor of controller 150 is synchronously to perform order with built-in system clock signal CLK or the clock signal CLKn through doubling.Therefore, for other circuit beyond controller 150, supply built-in system clock signal CLK is using as built-in system clock signal all the time.
Controller 150 is to include processor and ROM and/or RAM and constitute.Have program stored therein data in ROM/RAM, and processor is from ROM/RAM reading program data, and performs order contained in routine data.Processor receives and is produced built-in system clock signal CLK or clock signal CLKn produced by circuit 200 by system clock, and synchronously performs order one by one with built-in system clock signal CLK or clock signal CLKn.
Controller 150 is when flash memory 100 as described later carries out specifically process, is namely configured, set the value n of the multiplication of multiple circuit 220, and seasonal pulse selection circuit 230 selects the control signal C4 output of the clock signal CLKn after multiplication produce circuit 200 to system clock.There is no particular restriction for the value n of multiplication, for instance may be greater than the positive number of 1.And, the value n of multiplication need not fix all the time, it is possible to arranges kind and variable according to flash memory.
In preferably form, controller 150 judges the presence or absence of the setting of flash memory 100, when being judged to arrange, controls multiple circuit 220, with by the frequency multiplication of built-in system clock signal CLK to nf.Herein, so-called setting, refer to make the process needed for flash memory processes, be the process without direct relation of the process with memory array 110.More specifically, setting is and the process in the circuit of memory array 110 electrical isolation, for instance be the voltage generation process of internal voltage generating circuit 190.If arranging in period at this kind, even if then performing the order based on high speed time pulse signal CLKn, making internal voltage generating circuit 190 high speed processing, the noise therefore produced is without the harmful effect that the data storing lattice array cause substantivity.
In other preferably form, controller 150 such as can comprise the table being associated with the value n of multiplication according to the kind arranged in ROM/RAM.Fig. 8 is the relation schematic diagram between the kind of the embodiment of the present invention and the value of multiplication.As shown in Figure 8, if the kind arranged is 1, then the value doubled is n1, if the kind arranged is 2, then the value doubled is n2.Controller 150 can identify the kind of setting based on the analysis result of the order received from storage control, and multiple circuit 220 is set and the value arranging corresponding multiplication identified.And, seasonal pulse selection circuit 230 also can receive when the clock signal CLKn of multiplication from multiple circuit 220, selects the clock signal CLKn of multiple circuit 220, regardless of how carrying out the control signal C4 of self-controller 150.
It follows that with reference to the flow chart of Fig. 9 (Fig. 9 is the flow chart that the process of flash memory of the 1st embodiment to the present invention illustrates) so that the process of the flash memory of the present embodiment to be described.In the system 10 shown in Fig. 3, storage control 40 responds the request of host apparatus 20 and flash memory 100 is sent order.This order is received (S100) by the input/output buffer storage 120 of flash memory 100, then, controller 150 order received is analyzed (S102).Controller 150 determines whether to produce to arrange (S104) based on the analysis result of order.Such as, when programming (write) that order is to storage lattice, controller 150 is judged to the setting produced for generating the required voltage of programming.Or, when order is for carrying out the reading of data, block erasure, verification etc. from storage lattice, also it is judged to produce to arrange.But, if produce to arrange, suitably can select according to the process specification of flash memory 100.
When being judged to that generation is arranged, controller 150 produces control signal C4, and this control signal C4 indicates system clock to produce circuit 200 and generates high speed time pulse (S106).Specifically, multiple circuit 220 is set the value n of multiplication by controller 150, generates the clock signal CLKn through multiple circuit 220 multiplication, and makes seasonal pulse selection circuit 230 select clock signal CLKn.
Seasonal pulse selection circuit 230 by through multiplication clock signal CLKn be supplied to controller 150, the processor of controller 150 arrange period in use clock signal CLKn perform the order (S108) for arranging.Clock signal CLKn is provided only to controller 150 by seasonal pulse selection circuit 230, and does not supply to memory array 110.Therefore, will not cause because of clock signal CLKn at a high speed that the data of storage lattice are adversely affected.
It follows that controller 150 judges to arrange whether terminate (S112).Such as, controller 150 is when the process of all orders for arranging completes, it is determined that for arranging end.Or, the time rapid pulse corresponding with the command number for arranging, by enumerator etc., is counted, when this count value reaches during rapid pulse, it is determined that for arranging end by controller 150.
Controller 150 is when being judged to arrange end, and instruction system clock produces circuit 200 and terminates the multiplication (S112) of clock signal.Specifically, controller 150 stops the process of multiple circuit 220 by control signal C4, or stops multiplication, and makes seasonal pulse selection circuit 230 select built-in system clock signal CLK produced by clock pulse generator 210.Thus, controller 150 is supplied general built-in system clock signal CLK.
It follows that Figure 10 is the schematic diagram of the process sequence of the controller of the embodiment of the present invention.Process sequence shown in this Figure 10 is the process sequence corresponding person with Fig. 1 and Fig. 2, and controller 150 performs setting at period T1, T3, performs the process relevant to storage lattice at period T2, period T4.
Controller 150 is receive from storage control 40 should when pressing the period T2 order implemented, it is determined that arranging for needs, period T1 before period T2 performs the process arranged.Therefore, system clock is produced circuit 200 and exports control signal C4 by controller 150, and receives the clock signal CLKn through multiplication from system clock generation circuit 200.Controller 150 can refer to the kind that the table shown in Fig. 8 identifies the setting of period T1, and sets the value of the multiplication corresponding with the kind of this setting.
If such as the value n of multiplication being set as 2 by controller 150, then generate the clock signal CLKn of the frequency of 2f, and provide it to controller 150.Equally, if n=3, n=4, then the clock signal CLKn through high speed of 3f, 4f is generated.Period T1 is being set, is performing the setting command of high voltage HV1 to HV5 successively, but due to clock signal CLKn than built-in system clock signal CLK at a high speed, therefore can shorten and period T1 is set.On the other hand, if arrange period T1 be recognized as with Fig. 1 the period T1 identical time is set, then in the present embodiment, ratio can be performed the period T1 many command number of command number performed is set at Fig. 1.And then, it is supplied only by controller 150 arranging the period T1 clock signal CLKn generated, therefore can avoid the integrity etc. of the data being stored in storage lattice or signal is had undesirable effect.
Arrange period T1 to terminate, at the period T2 that presses, controller 150 is supplied general built-in system clock signal CLK.The term of execution that controller 150 coming based on built-in system clock signal CLK, the pressure of T2 processes required order.
It follows that controller 150 is when receiving check command, it is determined that for needing the setting of verification, arranging period T3, controls system clock and produce circuit 200, to supply the clock signal CLKn through multiplication.When arranging end, again control system clock and produce circuit 200, to supply general built-in system clock signal CLK.In the process sequence of Figure 10, when internal system clock signal CLK being doubled with n=2 (frequency=2 × f, cycle=1/2T), Fig. 1 needs add up to 20 seasonal pulse, on the other hand, in the present embodiment, if converting with the system clock before multiplication, 15 seasonal pulse are just enough.
So, according to the present embodiment, it is being set, by making clock frequency that the process of processor uses than general built-in system clock frequency at a high speed, thus the content of setting can flexibly be set period.Meanwhile, by shortening than the period that arranges of prior art during making to arrange, thus the process high speed of flash memory can be made.
It follows that the 2nd embodiment of the present invention is illustrated.In 1st embodiment, illustrate controller 150 and make the example of clock signal high speed according to the order from storage control in period arranging, and in the 2nd embodiment, controller 150 according to the external control signal from storage control arrange period in make clock signal high speed.
Figure 11 is the flow chart that the process of the flash memory of the 2nd embodiment to the present invention illustrates.The enable signal that arranges as external control signal is sent to flash memory 100 (S200) by storage control 40.Controller 150 determines whether to be externally controlled terminal and receives and arrange enable signal (S202).When be judged to receive arrange enable signal time, controller 150 when 1 embodiment in the same manner as, making system clock control circuit 200 generate high speed time pulse signal (S204) by control signal C4, the clock signal CLKn that controller 150 passes through to generate performs the order (S206) for arranging process.
It follows that controller 150 judges to arrange whether terminate (S208).This decision method and the 1st embodiment are same, when the execution being used for arranging all orders of process completes, or when have passed through consistent with all command numbers for arranging process during rapid pulse, can determine that and terminate for arranging.And, as additive method, controller 150 also can respond and receive for terminating the situation arranging disabling signal arranged from storage control 40, and is judged to that setting terminates.Now, storage control 40 and flash memory 100 utilize the external system seasonal pulse shared synchronously to process, storage control 40 may be based on the built-in system clock signal Tong Bu with external system clock signal time rapid pulse or the time monitor the time of setting.
In described embodiment, system clock shown in Fig. 7 is produced circuit 200 and by multiple circuit 220, the built-in system clock signal CLK from clock pulse generator 210 is doubled, but this is an example, the system clock of the present embodiment produces circuit 200 and is not limited to this kind of structure, it is possible to make clock frequency can be changed into optional frequency.Such as, system clock produces circuit 200 also can comprise phaselocked loop (PLL, PhaseLockedLoop) circuit, and this PLL circuit makes the seasonal pulse from the quartz crystal unit producing benchmark seasonal pulse can be changed into required frequency seasonal pulse.It is preferred that PLL circuit response carrys out the control signal C4 of self-controller 150, only make the clock signal of frequency high speed variable of benchmark seasonal pulse arranging output in period, and during pressing in the seasonal pulse of the general frequency of output.Now, system clock produces circuit and does not need the seasonal pulse selection circuit 230 shown in Fig. 7.And then, the system clock of the present embodiment produces circuit also can not use PLL circuit, and by appropriately combined to one or more frequency dividing circuits or multiple circuit, thus generating the clock signal of required frequency.
And then, in described embodiment, illustrate NAND type flash memory and carry out exectorial example by processor, but be not limited to this, the NAND type flash memory of the present invention can be also not processor, but synchronously perform the state machine of predetermined process sequence with clock signal.When state machine, when perform with predetermined arrange period corresponding when respectively processing, use the seasonal pulse that doubles to realize the high speed of process.Such as, if the process shown in Figure 10, then use multiplication seasonal pulse when performing each process arranging period T1, T3, when the end arranging period T1, T3 being detected, make multiplication seasonal pulse restore.Such as, the system clock generation circuit shown in Fig. 7 detects based on the content handled by state machine and arranges period T1, T3, produces multiplication seasonal pulse during this period.So, even if being the process based on state machine, it is possible to use, in during arranging, the shortening realizing arranging the time through the seasonal pulse of high speed.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein some or all of technical characteristic is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a flash memory, for anti-and type flash memory, it is characterised in that including:
Memory array, has anti-and type storage lattice；
Clock signal production part, produces clock signal；
Execution unit, receives the clock signal produced by described clock signal production part, and synchronously performs the prespecified process of flash memory with described clock signal；And
Control parts, arrange in period what described execution unit carried out, control described clock signal production part, so that the frequency high speed of the clock signal produced by described clock signal production part.
2. flash memory according to claim 1, it is characterized in that, described execution unit includes memory unit, the storage of described memory unit is for performing the order of the prespecified process of described flash memory, and performing the period for the order arranged at described execution unit, the frequency of described clock signal is by high speed.
3. flash memory according to claim 1, it is characterized in that, described execution unit includes state machine, and described state machine performs the prespecified process of described flash memory, and performing the period for the process arranged at described execution unit, the frequency of described clock signal is by high speed.
4. the flash memory according to any one of claims 1 to 3, it is characterised in that described control parts judge the presence or absence of described setting based on the signal that enables received from outside terminal.
5. the flash memory according to any one of claims 1 to 3, it is characterised in that:
Described clock signal production part includes: clock pulse generator, produces clock signal；Multiple circuit, is connected with described clock pulse generator, and described clock signal is doubled；And seasonal pulse selection circuit, it is connected with described clock pulse generator and described multiple circuit, selects any one in described clock signal or the clock signal through doubling,
Clock signal selected by described seasonal pulse selection circuit is supplied to described execution unit,
Described execution unit, within the period of described setting, performs process based on the clock signal through multiplication.
6. flash memory according to claim 5, it is characterized in that, the value that described clock signal is doubled by described control component settings by described multiple circuit, and the control signal output extremely described clock signal production part of the selection of described seasonal pulse selection circuit will be controlled.
7. the flash memory according to any one of claims 1 to 3, it is characterized in that, flash memory includes voltage generation circuit, described voltage generation circuit produces voltage based on the supply voltage supplied from outside terminal, described execution unit, within the period of described setting, makes described voltage generation circuit produce high voltage.
8. flash memory according to claim 6, it is characterized in that, described control parts include the table specified with multiple described values arranging multiplication corresponding respectively and the identification component identifying described setting based on described order data, and described multiple circuit is set and the value arranging corresponding multiplication identified by described control parts.
9. a memory module, it is characterised in that including:
Flash memory described in any one of claim 1 to 8；And
Storage control, is connected with described flash memory,
Flash memory is sent described order data or enables signal by described storage control.
10. process a system, for the setting performed by anti-and the controller of type flash memory, it is characterised in that including:
First module, it is determined that the presence or absence of described setting；
Second module, when being judged to have described setting, controls clock generating circuit, so that built-in system clock signal only high speed within the period of described setting；And
Three module, by the described clock signal through high speed, makes processor perform the order for described setting.
11. process system according to claim 10, it is characterised in that described first module is based on the outside signal that enables received from storage control and carries out judging the presence or absence of described setting.
12. process system according to claim 10, it is characterized in that, described clock generating circuit includes multiple circuit and seasonal pulse selection circuit, described second module controls described clock generating circuit, to set the value of the multiplication of described multiple circuit, and control described seasonal pulse selection circuit, so that the clock signal through multiplication is supplied to described processor.
13. the process system according to any one of claim 10 to 12, it is characterised in that described three module, within the period of described setting, performs the order for described setting, what thus generate flash memory processes required multiple high voltages.
14. a processing method, use the clock signal in anti-and type flash memory, it is characterised in that the treating method comprises following steps:
Judge the presence or absence of described setting instead and performed by the controller of type flash memory；
When being judged to have described setting, control clock generating circuit, so that built-in system clock signal only high speed within the period of described setting；And
By the described clock signal through high speed, processor is made to perform the order for described setting.
15. processing method according to claim 14, it is characterized in that, described clock generating circuit includes multiple circuit and seasonal pulse selection circuit, the step of described control sets the value of the multiplication of described multiple circuit, and control described seasonal pulse selection circuit, so that the clock signal through multiplication is supplied to described processor.
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| CN1442862A (en) * | 2002-02-13 | 2003-09-17 | 夏普公司 | Semiconductor storage equipment and electronic information equipment using said device |
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