CN105761655A - Source electrode driving circuit - Google Patents

Abstract

The invention provides a source electrode driving circuit which comprises a multi-task unit for receiving a Gamma voltage signal and outputting a source electrode driving signal. The multi-task unit comprises a first switch and a second switch. The first switch is used for generating a first output signal according to a first control signal and a second control signal at the first time point in a frame time. The second switch is used for generating a second output signal according to a third control signal and a fourth control signal at the second time point in the frame time. The source electrode driving signal is the sum of the first output signal and the second output signal.

Description

Source electrode drive circuit

Technical field

The present invention relates to a kind of source electrode drive circuit, and the source electrode drive circuit of current peak (peakcurrent) can be reduced particularly to one.

Background technology

Lifting along with the manufacturing technology of display floater, high-resolution display floater, such as resolution is 1920 × 1080 (fullHD) or the display floater of 3840 × 2160 (4K2K), and the large scale display floater of more than 50 inches can produce in a large number.But, for high-resolution display floater, because the relation that number of pixels increases, to maintain original frame rate (framerate), then the driving time of each pixel column in display floater must be shortened by source electrode driver, make source electrode driver must promote its output electric current, so that each pixel in display floater to be charged.

For example, refer to Figure 1A and 1B, it is the relation schematic diagram illustrating stabilization time with current peak.As shown in Figure 1A and 1B, the area (i.e. the integration of Current versus time) of the oblique line portion of Figure 1A and 1B is identical, represents source electrode driver the electricity that pixel is charged is identical, and current peak I in figure ia_PHigher than current peak I in fig. ib_P, and T stabilization time in fig. ib_SIt is longer than T stabilization time in figure ia_S.The driving causing display floater in voltage drop (IRdrop) excessive for Figure 1A occurs abnormal, the problem that the inhibition of electromagnetic interference (electromagneticinterference) is not good and power consumption is too high.Although the current peak I of Figure 1B_PBe little compared with Figure 1A, but stabilization time T_SAlso thus increase, it is possible to cause current potential uncharged to correct in pixel charging time, and cause image display mistake.

Summary of the invention

It is an object of the invention to be in that to provide a kind of source electrode drive circuit, can effectively reduce the current peak of its output electric current when the charging interval of pixel is not significantly increased, and then reduce voltage drop, reduce the impact of electromagnetic interference and save the effect of power consumption.

Above-mentioned purpose according to the present invention, it is proposed to a kind of in order to drive the source electrode drive circuit of display floater.This source electrode drive circuit comprises the multi-task unit receiving gamma voltage (Gammavoltage) signal and output the first source drive signal to the first pixel column of display floater.This multi-task unit comprises the first switch and the second switch.When first switch was put in order to the very first time in the first frame time, produce the first output signal according to the first control signal and the second control signal, and the first switch has to export the first outfan of the first output signal.When second switch is in order to the second time point in the first frame time, produces the second output signal according to the 3rd control signal and the 4th control signal, and the second switch has to export the first outfan of the second output signal.Wherein, the first outfan of the first switch is coupled to the first outfan of the second switch, and the first source drive signal be the first output signal and the second output signal and.

According to one embodiment of the invention, above-mentioned first switch comprises the first cmos transmission gate (CMOStransmissiongate) exporting the first output signal, and above-mentioned second switch comprises the second cmos transmission gate of exporting the second output signal.

According to another embodiment of the present invention, above-mentioned second time point is after point of the above-mentioned very first time, and has for the first time delay between the second time point and very first time point.

According to another embodiment of the present invention, above-mentioned multi-task unit also comprises the 3rd switch.When 3rd switch is in order to three time point in the first frame time, produce the 3rd output signal according to the 5th control signal and the 6th control signal, and the 3rd switch has to export the first outfan of the 3rd output signal.Wherein, the first outfan of the 3rd switch is coupled to the first outfan of the first switch and the first outfan of the second switch, and the first source drive signal be the first output signal, the second output signal with the 3rd export signal and.

According to another embodiment of the present invention, above-mentioned 3rd switch comprises the 3rd cmos transmission gate exporting the 3rd output signal.

According to another embodiment of the present invention, above-mentioned 3rd time point is after above-mentioned second time point, and has for the second time delay between the 3rd time point and the second time point.

According to another embodiment of the present invention, above-mentioned multi-task unit is also in order to export the second source drive signal the second pixel column to display floater.When above-mentioned first switch is also in order to four time point in the second frame time after the first frame time, produce the 4th output signal according to the first control signal and the second control signal, and the first switch also has to export the second outfan of the 4th output signal.When above-mentioned second switch is also in order to five time point in the second frame time, produce the 5th output signal according to the 3rd control signal and the 4th control signal, and the second switch also has to export the second outfan of the 5th output signal.Wherein, the second outfan of the first switch is coupled to the second outfan of the second switch, the second source drive signal be the 4th output signal with the 5th export signal and, and the polarity of the first source drive signal and the second source drive signal is contrary.

According to another embodiment of the present invention, above-mentioned first switch also comprises the 4th cmos transmission gate exporting the 4th output signal, and above-mentioned second switch also comprises to export the 5th the 5th cmos transmission gate exporting signal.

According to another embodiment of the present invention, above-mentioned 5th time point is after above-mentioned 4th time point, and has for the 3rd time delay between the 5th time point and the 4th time point.

According to another embodiment of the present invention, above-mentioned source electrode drive circuit also comprises output buffer, and this output buffer is coupled to the input of multi-task unit.

Accompanying drawing explanation

For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, the explanation of accompanying drawing is as follows:

Figure 1A and 1B is the relation schematic diagram illustrating stabilization time with current peak；

Fig. 2 is the circuit box schematic diagram of the source electrode drive circuit illustrating the embodiment of the present invention；

Fig. 3 A illustrates the circuit diagram of the first switch in Fig. 2；

Fig. 3 B illustrates the circuit diagram of the second switch in Fig. 2；

Fig. 4 illustrates the sequential chart of each signal in Fig. 2；

Fig. 5 A is the curve synoptic diagram illustrating the embodiment of the present invention output electric current with comparative example with the relation of time；

Fig. 5 B is the curve synoptic diagram of the output voltage illustrating comparative example and the relation of time；

Fig. 5 C is the curve synoptic diagram of the output voltage illustrating the embodiment of the present invention and the relation of time；

Fig. 6 is the circuit box schematic diagram of the source electrode drive circuit illustrating the embodiment of the present invention；

Fig. 7 illustrates the circuit diagram of the 3rd switch in Fig. 6；And

Fig. 8 illustrates the sequential chart of each signal in Fig. 6.

Detailed description of the invention

Hereinafter hash out embodiments of the invention.It is understood, however, that embodiment provides many applicable inventive concepts, it may be implemented in certain content miscellaneous.Discussed specific embodiment is intended for illustrating, is not limited to the scope of the present invention.

Refer to the circuit box schematic diagram that Fig. 2, Fig. 2 are the source electrode drive circuits 100 illustrating the embodiment of the present invention.Source electrode drive circuit 100 comprises output buffer 110 and multi-task unit 120.Output buffer 110 receives gamma voltage signal V_G, and the gamma voltage signal V that output is after buffering_I.Multi-task unit 120 is in order to control the output of polarity, and it comprises the first switch 121 and the second switch 122.First switch 121 receives gamma voltage signal V_IWith control signal C1, C2, and according to this produce output signal V_O1、V_O2, and exported this output signal V a bit by outfan O1, O2 respectively_O1、V_O2.Second switch 122 receives gamma voltage signal V_IWith control signal C3, C4, and according to this produce output signal V_O3、V_O4, and exported this output signal V a bit by outfan O3, O4 respectively_O3、V_O4.Output signal V_O1、V_O3And be source drive signal V_D1, and output signal V_O2、V_O4And be source drive signal V_D2.Source drive signal V_D1Input the odd pixel column to display floater (figure does not illustrate) and source drive signal V_D2Input the even pixel row to display floater (figure does not illustrate).Or, source drive signal V_D1Input the even pixel row to display floater (figure does not illustrate) and source drive signal V_D2Input the odd pixel column to display floater (figure does not illustrate).In certain embodiments, source drive signal V_D1And V_D2It is separately input into two adjacent pixel columns of display floater (figure does not illustrate).In certain embodiments, source drive signal V_D1And V_D2Polarity be contrary.That is, source drive signal V_D1And V_D2Polarity respectively positive polarity and negative polarity, or source drive signal V_D1And V_D2Polarity respectively negative polarity and positive polarity.

Refer to Fig. 3 A, Fig. 3 A and illustrate the circuit diagram of the first switch 121 in Fig. 2.First switch 121 comprises cmos transmission gate TG₁、TG₂.Cmos transmission gate TG₁There is N-type transistor NM₁With P-type transistor PM₁.N-type transistor NM₁Gate input control signal C1, and P-type transistor PM₁Gate input control signalControl signalFor the inversion signal of control signal C1, in the present embodiment, control signalIt is by phase inverter INV by control signal C1₁Obtain.In other embodiments, control signalBe by the first switch 121 outside circuit directly provide.N-type transistor NM₁Source electrode and P-type transistor PM₁Drain electrode be electrically connected to intersection point PI₁, and intersection point PI₁In order to input gamma voltage signal V_I.N-type transistor NM₁Drain electrode and P-type transistor PM₁Source electrode be electrically connected to intersection point PO₁, and intersection point PO₁In order to output signal output V_O1.Similarly, cmos transmission gate TG₂There is N-type transistor NM₂With P-type transistor PM₂.N-type transistor NM₂Gate input control signal C2, and P-type transistor PM₂Gate input control signalControl signalFor the inversion signal of control signal C2, in the present embodiment, control signalIt is by phase inverter INV by control signal C2₂Obtain.In other embodiments, control signalBe by the first switch 121 outside circuit directly provide.N-type transistor NM₂Source electrode and P-type transistor PM₂Drain electrode be electrically connected to intersection point PI₂, and intersection point PI₂In order to input gamma voltage signal V_I.N-type transistor NM₂Drain electrode and P-type transistor PM₂Source electrode be electrically connected to intersection point PO₂, and intersection point PO₂In order to output signal output V_O2。

It should be noted that above-mentioned transmission gate TG₁In N-type transistor NM₁, P-type transistor PM₁With intersection point PI₁、PO₁Annexation be corresponding output signal V_O1Level higher than gamma voltage signal V_I.Ability preforming technique personnel can according to different design requirements to above-mentioned transmission gate TG₁In the annexation of each element carry out change or the change of correspondence.For example, if making gamma voltage signal V_ILevel higher than output signal V_O1, can by transmission gate TG₁Change into N-type transistor NM₁Drain electrode and P-type transistor PM₁Source electrode be electrically connected to intersection point PI₁, and intersection point PI₁In order to input gamma voltage signal V_I, and N-type transistor NM₁Source electrode and P-type transistor PM₁Drain electrode be electrically connected to intersection point PO₁, and intersection point PO₁In order to output signal output V_O1.Similarly, at transmission gate TG₂In N-type transistor NM₂, P-type transistor PM₂With intersection point PI₂、PO₂Annexation also can carry out according to different design requirements correspondence change or change.

Refer to Fig. 3 B, Fig. 3 B and illustrate the circuit diagram of the second switch 122 in Fig. 2.Second switch 122 comprises cmos transmission gate TG₃、TG₄.Cmos transmission gate TG₃There is N-type transistor NM₃With P-type transistor PM₃.N-type transistor NM₃Gate input control signal C3, and P-type transistor PM₃Gate input control signalControl signalFor the inversion signal of control signal C3, in the present embodiment, control signalIt is obtained by phase inverter by control signal C3.In other embodiments, control signalBe by the second switch 122 outside circuit directly provide.N-type transistor NM₃Source electrode and P-type transistor PM₃Drain electrode be electrically connected to intersection point PI₃, and intersection point PI₃In order to input gamma voltage signal V_I.N-type transistor NM₃Drain electrode and P-type transistor PM₃Source electrode be electrically connected to intersection point PO₃, and intersection point PO₃In order to output signal output V_O3.Similarly, cmos transmission gate TG₄There is N-type transistor NM₄With P-type transistor PM₄.N-type transistor NM₄Gate input control signal C4, and P-type transistor PM₄Gate input control signalControl signalFor the inversion signal of control signal C4, in the present embodiment, control signalIt is obtained by phase inverter by control signal C4.In other embodiments, control signalBe by the second switch 122 outside circuit directly provide.N-type transistor NM₄Source electrode and P-type transistor PM₄Drain electrode be electrically connected to intersection point PI₄, and intersection point PI₄In order to input gamma voltage signal V_I.N-type transistor NM₄Drain electrode and P-type transistor PM₄Source electrode be electrically connected to intersection point PO₄, and intersection point PO₄In order to output signal output V_O4。

The operation of source electrode drive circuit 100 is described below in conjunction with Fig. 4.When frame time FRAME1 starts, (this time point is defined as t₁), control signal C1 switches to high levle, and control signal C3 is maintained low level.Now, cmos transmission gate TG₁Conducting so that source drive signal V_D1Magnitude of voltage begin to ramp up, and output electric current I_DIt is increased to current peak I_P1.Meanwhile, source drive signal V_D2Magnitude of voltage begin to decline.At T time delay_SDIn, export electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage slow down gradually.In frame time FRAME1, export electric current I_DCorresponding to source drive signal V_D1。

Through T time delay_SDAfter, then come time point t₂.Now, control signal C3 switches to high levle, to turn on cmos transmission gate TG₃.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₃Conducting and be increased to current peak I_P2.In certain embodiments, at T stabilization time_S’Time output electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage all compared with at T time delay_SDTime be fast.

Until through T stabilization time_S’After, namely put t the time of advent₃Time, source drive signal V_D1Rise to high potential, source drive signal V_D2Drop to electronegative potential and output electric current I_DIt is reduced to and levels off to 0.Time delay T_SDWith T stabilization time_S’Summation be source drive signal V_D1T stabilization time passed when being increased to high potential by electronegative potential_S。

At time point t₄Time, control signal C1 and C3 all switches to low level.Control signal C1 and C3 is elapsed time (time point t during high levle₂To time point t₄) it is defined as full driving time T_FD。

Then, when frame time FRAME2 starts, (this time point is defined as t₅), control signal C2 switches to high levle, and control signal C4 is maintained low level.Now, cmos transmission gate TG₂Conducting so that source drive signal V_D2Magnitude of voltage begin to ramp up, and output electric current I_DIt is increased to current peak I_P3.Meanwhile, source drive signal V_D1Magnitude of voltage begin to decline.At T time delay_SDIn, export electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage slow down gradually.In frame time FRAME2, export electric current I_DCorresponding to source drive signal V_D2。

Through T time delay_SDAfter, then come time point t₆.Now, control signal C4 switches to high levle, to turn on cmos transmission gate TG₄.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₄Conducting and be increased to current peak I_P4.In certain embodiments, at T stabilization time_S’Time output electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage all compared with at T time delay_SDTime be fast.

Until through T stabilization time_S’After, namely put t the time of advent₇Time, source drive signal V_D2Rise to high potential, source drive signal V_D1Drop to electronegative potential and output electric current I_DIt is reduced to and levels off to 0.Time delay T_SDWith T stabilization time_S’Summation be source drive signal V_D2T stabilization time passed when being increased to high potential by electronegative potential_S。

At time point t₈Time, control signal C2 and C4 all switches to low level.Control signal C2 and C4 is elapsed time (time point t during high levle₆To time point t₈) for full driving time T_FD.Then, at time point t₉Time, start next frame time.

Following description is at T time delay_SDWith T stabilization time_S’In output electric current I_D.For frame time FRAME1, export electric current I_DAs shown in formula (1):

$I_D\left(t\right)=\frac{\sqrt{V_{\mathrm{ov}}^2+2(V_{\mathrm{ov}}-\mathrm{\ΔV})\frac{1}{R_{L}k}+{\left(\frac{1}{R_{L}k}\right)}^2}-(V_{\mathrm{ov}}-\mathrm{\ΔV}+\frac{1}{R_{L}k})}{R_L},---\left(1\right)$

Wherein, I_DT () represents at time t (t₁≤t<t₃) time output electric current I_D, R_LFor source drive signal V_D1The equivalent resistance of the subsequent conditioning circuit (figure does not illustrate) inputted, V_ov=V_H-V_SS+V_tp, V_HFor gamma voltage signal V_IHigh levle magnitude of voltage, V_SSFor the low level magnitude of voltage of control signal C1～C4, and V_tpFor cmos transmission gate TG₁、TG₂Threshold voltage (thresholdvoltage).At time t between time point t₁With t₂Between (t1≤t < t2) time, parameter k and voltage difference delta V is respectively as shown in formula (2) and formula (3):

$k=k_{\mathrm{SD}}={\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{{\mathrm{TG}}_1};$ And (2)

$\mathrm{\&Delta;V}=(V_H-V_L)e^{\frac{-(t-t_1)}{(R_L+\frac{1}{k_{\mathrm{SD}}{V}_{\mathrm{ov}}})C_L}};---\left(3\right)$

Wherein, μ_nFor cmos transmission gate TG₁Carrier mobility (carriermobility), C_oxFor cmos transmission gate TG₁The capacitance of gate dielectric, C_LFor source drive signal V_D1The equivalent capacitance value of the subsequent conditioning circuit (figure does not illustrate) inputted,For cmos transmission gate TG₁Passage breadth length ratio (channelaspectratio), and V_LFor gamma voltage signal V_ILow level magnitude of voltage.Because of current peak I_P1Occur in time point t₁, therefore current peak I_P1Can by calculating I_D(t₁) and obtain.

Additionally, at time t between time point t₂With t₃Between (t₂≤t<t₃) time, parameter k and voltage difference delta V is respectively as shown in formula (4) and formula (5):

$k=k_{\mathrm{FD}}={\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}[{\left(\frac{W}{L}\right)}_{\mathrm{TG}1}+{\left(\frac{W}{L}\right)}_{\mathrm{TG}3}];$ And (4)

$\mathrm{\&Delta;V}=(V_H-V_L)e^{\frac{-(t_2-t_1)}{(R_L+\frac{1}{k_{\mathrm{SD}}{V}_{\mathrm{ov}}})C_L}+\frac{-(t-t_2)}{(R_L+\frac{1}{k_{\mathrm{FD}}{V}_{\mathrm{ov}}})C_L}};---\left(5\right)$

Wherein,For cmos transmission gate TG₃Passage breadth length ratio.Similarly, because of current peak I_P2Occur in time point t₂, therefore current peak I_P2Can by calculating I_D(t₂) and obtain.In the present embodiment, cmos transmission gate TG₁And TG₃Carrier mobility and the capacitance of gate dielectric equal.Output electric current I in frame time FRAME2_D, parameter k and voltage difference delta V and current peak I_P3And I_P4Also can obtain to the content of formula (5) by simply changing formula (1), therefore be not repeated herein.

It should be noted that current peak I_P1～I_P4, time delay T_SDWith T stabilization time_S’Value be not intended to be limited to fix.Corresponding adjustment can be done according to design requirement.For example, can by changing cmos transmission gate TG₁The design of passage breadth length ratio and adjust current peak I_P1, and can by changing T time delay_SDLength come corresponding adjustment current peak I_P2With T stabilization time_S’Length.

Fig. 5 A is the curve synoptic diagram illustrating the embodiment of the present invention output electric current with comparative example with the relation of time.The embodiment of the present invention is use the multi-task unit comprising two switch, and such as the multi-task unit 120 of Fig. 2, and comparative example is the multi-task unit using and only comprising a switch.Wherein, the switch that two switch that the embodiment of the present invention uses and comparative example use is formed by two cmos transmission gates.The passage breadth length ratio of the cmos transmission gate that the embodiment of the present invention uses and the passage breadth length ratio of cmos transmission gate that uses equal to comparative example.With Fig. 3 A and 3B, cmos transmission gate TG₁Passage breadth length ratio and cmos transmission gate TG₃Passage breadth length ratio and the passage breadth length ratio of one of them cmos transmission gate of being comparative example, and cmos transmission gate TG₂Passage breadth length ratio and cmos transmission gate TG₄Passage breadth length ratio and the passage breadth length ratio of another cmos transmission gate of being comparative example.Fig. 5 A is the analog result of the embodiment of the present invention and comparative example, and in formula (1) to formula (5), R_LIt is set as 10k Ω, C_LIt is set as 100pF, V_HIt is set as 9V, V_LIt is set as 1V, V_SSIt is set as 0V, V_tpIt is set as-1.65V, k_SDIt is set as 21.7 μ A/V², k_SDIt is set as 21.7 μ A/V², k_FDIt is set as 86.7 μ A/V², and time delay T_SDIt is set as 0.8 microsecond.

As shown in Figure 5A, when the time is 0, the embodiment of the present invention first turns on one of them cmos transmission gate (cmos transmission gate TG of such as Fig. 3 A₁) so that output electric current is increased to 450 μ A, and the output electric current of comparative example is increased to 700 μ A.Then, the output electric current of the embodiment of the present invention and comparative example is gradually lowered in time.Through 0.8 microsecond (micro-second；After μ s), the embodiment of the present invention turns on another cmos transmission gate (cmos transmission gate TG of such as Fig. 3 B again₃) so that output electric current is increased to 440 μ A again, and the output electric current of comparative example maintains the trend being gradually lowered.Afterwards, the output electric current with comparative example of the embodiment of the present invention is gradually decrease to 0 in time.

By Fig. 5 A it can be seen that the current peak of the embodiment of the present invention is 450 μ A and 440 μ A, and the current peak of comparative example is 700 μ A.Therefore, compared to comparative example, the embodiment of the present invention can produce relatively low current peak.

Referring to the curve synoptic diagram that Fig. 5 B and 5C, Fig. 5 B is the output voltage illustrating comparative example and the relation of time, and Fig. 5 C is output voltage (the source drive signal V of such as Fig. 2 illustrating the embodiment of the present invention_D1Magnitude of voltage) with the curve synoptic diagram of the relation of time.Comparison diagram 5B and 5C is it can be seen that the output voltage of the embodiment of the present invention rate of climb between 0 second and 0.8 microsecond is slow compared with the output voltage of comparative example, and it only turns on one of them cmos transmission gate owing to the embodiment of the present invention between 0 second and 0.8 microsecond.When 0.8 microsecond, because switching to conducting state when another cmos transmission gate is approximately in 0.8 microsecond so that the rate of climb of output voltage increases.By Fig. 5 B and 5C it can be seen that it is 5.6059 microseconds that the output voltage of comparative example is risen to high levle (9V) required time by low level (1V), and it is 5.8691 microseconds that the output voltage of the embodiment of the present invention is risen to high levle required time by low level.

Compared to comparative example, although the stabilization time of the embodiment of the present invention, (namely output voltage is increased to high levle by low level or is reduced to low level required time by high levle) increased about 5% a little, but the current peak of the embodiment of the present invention can be greatly reduced about 36%.Therefore, the source electrode drive circuit of the present invention can effectively reduce the current peak of its output electric current when the charging interval of pixel is not significantly increased.

In the source electrode drive circuit of the present invention, multi-task unit can comprise multiple switch, and is not limited with two switch of Fig. 2 depicted.For example, refer to the circuit box schematic diagram that Fig. 6, Fig. 6 are the source electrode drive circuits 200 illustrating the embodiment of the present invention.Source electrode drive circuit 200 comprises output buffer 210 and multi-task unit 220.Output buffer 210 receives gamma voltage signal V_G, and the gamma voltage signal V that output is after buffering_I.Multi-task unit 220 is in order to control the output of polarity, and it comprises the first switch the 221, second switch 222 and the 3rd switch 223.First switch 221 receives gamma voltage signal V_IWith control signal C1, C2, and according to this produce output signal V_O1、V_O2, and exported this output signal V a bit by outfan O1, O2 respectively_O1、V_O2.Second switch 222 receives gamma voltage signal V_IWith control signal C3, C4, and according to this produce output signal V_O3、V_O4, and exported this output signal V a bit by outfan O3, O4 respectively_O3、V_O4.3rd switch 223 receives gamma voltage signal V_IWith control signal C5, C6, and according to this produce output signal V_O5、V_O6, and exported this output signal V a bit by outfan O5, O6 respectively_O5、V_O6.Output signal V_O1、V_O3、V_O5And be source drive signal V_D1, and output signal V_O2、V_O4、V_O6And be source drive signal V_D2.Source drive signal V_D1Input the odd pixel column to display floater (figure does not illustrate) and source drive signal V_D2Input the even pixel row to display floater (figure does not illustrate).Or, source drive signal V_D1Input the even pixel row to display floater (figure does not illustrate) and source drive signal V_D2Input the odd pixel column to display floater (figure does not illustrate).In certain embodiments, source drive signal V_D1And V_D2It is separately input into two adjacent pixel columns of display floater (figure does not illustrate).In certain embodiments, source drive signal V_D1And V_D2Polarity be contrary.That is, source drive signal V_D1And V_D2Polarity respectively positive polarity and negative polarity, or source drive signal V_D1And V_D2Polarity respectively negative polarity and positive polarity.

The first switch 221 in Fig. 6 is identical with the first switch 121 in Fig. 2 and the second switch 122 respectively with the circuit structure of the second switch 222, therefore the circuit structure of the first switch 221 and the second switch 222 is not repeated herein.Refer to Fig. 7, Fig. 7 and illustrate the circuit diagram of the 3rd switch 223 in Fig. 6.3rd switch 223 comprises cmos transmission gate TG₅、TG₆.Cmos transmission gate TG₅There is N-type transistor NM₅With P-type transistor PM₅.N-type transistor NM₅Gate input control signal C5, and P-type transistor PM₅Gate input control signalControl signalFor the inversion signal of control signal C5, in the present embodiment, control signalIt is by phase inverter INV by control signal C5₅Obtain.In other embodiments, control signalBe by the 3rd switch 223 outside circuit directly provide.N-type transistor NM₅Source electrode and P-type transistor PM₅Drain electrode be electrically connected to intersection point PI₅, and intersection point PI₅In order to input gamma voltage signal V_I.N-type transistor NM₅Drain electrode and P-type transistor PM₅Source electrode be electrically connected to intersection point PO₅, and intersection point PO₅In order to output signal output V_O5.Similarly, cmos transmission gate TG₆There is N-type transistor NM₆With P-type transistor PM₆.N-type transistor NM₆Gate input control signal C6, and P-type transistor PM₆Gate input control signalControl signalFor the inversion signal of control signal C6, in the present embodiment, control signalIt is by phase inverter INV by control signal C6₆Obtain.In other embodiments, control signalBe by the 3rd switch 223 outside circuit directly provide.N-type transistor NM₆Source electrode and P-type transistor PM₆Drain electrode be electrically connected to intersection point PI₆, and intersection point PI₆In order to input gamma voltage signal V_I.N-type transistor NM₆Drain electrode and P-type transistor PM₆Source electrode be electrically connected to intersection point PO₆, and intersection point PO₆In order to output signal output V_O6。

The operation of source electrode drive circuit 200 is described below in conjunction with Fig. 8.When frame time FRAME1 starts, (this time point is defined as t₁), control signal C1 switches to high levle, and control signal C3 and C5 is maintained low level.Now, cmos transmission gate TG₁Conducting so that source drive signal V_D1Magnitude of voltage begin to ramp up, and output electric current I_DIt is increased to current peak I_P1’.Meanwhile, source drive signal V_D2Magnitude of voltage begin to decline.At T time delay_SD1In, export electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage slow down gradually.In frame time FRAME1, export electric current I_DSystem is corresponding to source drive signal V_D1。

Through T time delay_SD1After, then come time point t₂.Now, control signal C3 switches to high levle, to turn on cmos transmission gate TG₃, and control signal C5 is maintained low level.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₃Conducting and be increased to current peak I_P2’.At T time delay_SD2In, export electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage slow down gradually.In certain embodiments, at T time delay_SD2Time output electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage all compared with at T time delay_SD1Time be fast.

Through T time delay_SD2After, then come time point t₃.Now, control signal C5 switches to high levle, to turn on cmos transmission gate TG₅.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₅Conducting and be increased to current peak I_P3’.In certain embodiments, at T stabilization time_S’Time output electric current I_DThe rate of decay, source drive signal V_D1The rate of climb of magnitude of voltage and source drive signal V_D2The decrease speed of magnitude of voltage all compared with at T time delay_SD1And T_SD2Time be fast.

Until through T stabilization time_S’After, namely put t the time of advent₄Time, source drive signal V_D1Rise to high potential, source drive signal V_D2Drop to electronegative potential and output electric current I_DIt is reduced to and levels off to 0.Time delay T_SD1And T_SD2With T stabilization time_S’Summation be source drive signal V_D1T stabilization time passed when being increased to high potential by electronegative potential_S。

At time point t₅Time, control signal C1, C3 and C5 all switch to low level.Control signal C1, C3 and C5 are elapsed time (time point t during high levle₃To time point t₅) it is defined as full driving time T_FD。

Then, when frame time FRAME2 starts, (this time point is defined as t₆), control signal C2 switches to high levle, and control signal C4 and C6 is maintained low level.Now, cmos transmission gate TG₂Conducting so that source drive signal V_D2Magnitude of voltage begin to ramp up, and output electric current I_DIt is increased to current peak I_P4’.Meanwhile, source drive signal V_D1Magnitude of voltage begin to decline.At T time delay_SD1In, export electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage slow down gradually.In frame time FRAME2, export electric current I_DCorresponding to source drive signal V_D2。

Through T time delay_SD1After, then come time point t₇.Now, control signal C4 switches to high levle, to turn on cmos transmission gate TG₄, and control signal C6 is maintained low level.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₄Conducting and be increased to current peak I_P5’.At T time delay_SD2In, export electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage slow down gradually.In certain embodiments, at T time delay_SD2Time output electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage all compared with at T time delay_SD1Time be fast.

Through T time delay_SD2After, then come time point t₈.Now, control signal C6 switches to high levle, to turn on cmos transmission gate TG₆.Meanwhile, output electric current I_DAlso because of cmos transmission gate TG₆Conducting and be increased to current peak I_P6’.In certain embodiments, at T stabilization time_S’Time output electric current I_DThe rate of decay, source drive signal V_D2The rate of climb of magnitude of voltage and source drive signal V_D1The decrease speed of magnitude of voltage all compared with at T time delay_SD1And T_SD2Time be fast.

Until through T stabilization time_S’After, namely put t the time of advent₉Time, source drive signal V_D2Rise to high potential, source drive signal V_D1Drop to electronegative potential and output electric current I_DIt is reduced to and levels off to 0.Time delay T_SD1And T_SD2With T stabilization time_S’Summation be source drive signal V_D2T stabilization time passed when being increased to high potential by electronegative potential_S。

At time point t₁₀Time, control signal C2, C4 and C6 all switch to low level.Control signal C2, C4 and C6 are elapsed time (time point t during high levle₈To time point t₁₀) for full driving time T_FD.Then, at time point t₁₁Time, start next frame time.

Fig. 2 and Fig. 6 explains for embodiment with switch for two and three respectively, those skilled in the art ought can extend to according to the explanation of above-described embodiment and implement with the switch of more than three, therefore the embodiment of the switch of more than three is also contained by the present invention.For source electrode drive circuit, there is M switch, if the circuit structure of this M switch is identical with the circuit structure of Fig. 3 A depicted, the cmos transmission gate in this M switch of turn in order in a frame time, and the cmos transmission gate in this M switch switches to the time point of conducting state to be sequentially t₁、t₂、…、t_M, then shown in output electric current such as formula (6):

$I_D\left(t\right)=\frac{\sqrt{V_{\mathrm{ov}}^2+2(V_{\mathrm{ov}}-\mathrm{\&Delta;V})\frac{1}{R_L{k}_i}+{\left(\frac{1}{R_L{k}_i}\right)}^2}-(V_{\mathrm{ov}}-\mathrm{\&Delta;V}+\frac{1}{R_L{k}_i})}{R_L},---\left(6\right)$

Wherein 1≤i≤M and i is positive integer, and parameter k_iWith voltage difference delta V respectively as shown in formula (7) and formula (8):

$k_i=\underset{j=1}{\overset{i}{\mathrm{\&Sigma;}}}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_j;$ And (7)

$\mathrm{\&Delta;V}=\left\{\begin{array}{cc}(V_H-V_L)e^{\frac{-(t-t_1)}{(R_L+\frac{1}{k_1{V}_{\mathrm{ov}}})C_L}}& (i=1)\\ (V_H-V_L)e^{[\frac{-(t-t_i)}{(R_L+\frac{1}{k_i{V}_{\mathrm{ov}}})C_L}+\underset{l=1}{\overset{i-1}{\mathrm{\&Sigma;}}}\frac{-(t_{l+1}-t_l)}{(R_L+\frac{1}{k_l{V}_{\mathrm{ov}}})C_L}]}& (1<i\&le;M)\end{array}\right..---\left(8\right)$

In sum, the source electrode drive circuit of the present invention at the current peak of its output electric current of lower effective reduction in the charging interval that pixel is not significantly increased, and then can reduce voltage drop, reduce the impact of electromagnetic interference and save the effect of power consumption.

Although the present invention is disclosed above with embodiment; so it is not limited to the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the defined person of appended claims.

[symbol description]

100,200: source electrode drive circuit

110,210: output buffer

120,220: multi-task unit

121,221: the first switch

122,222: the second switch

223: the three switch

C1～C6,Control signal

I_D: output electric current

FRAME1, FRAME2: frame time

INV₁～INV₆: phase inverter

I_P、I_P1、I_P2、I_P3、I_P4、I_P1’、I_P2’、I_P3’、I_P4’、I_P5’、I_P6': current peak

NM₁～NM₆: N-type transistor

O1～O6: outfan

PI₁～PI₆、PO₁～PO₆: intersection point

PM₁～PM₆: P-type transistor

t₁～t₁₁: time point

T_FD: full driving time

T_S、T_S’: stabilization time

T_SD、T_SD1、T_SD2: time delay

TG₁～TG₆: cmos transmission gate

V_D1、V_D2: source drive signal

V_G、V_I: gamma voltage signal

V_O1～V_O6: output signal

Claims (10)

1. a source electrode drive circuit, in order to drive display floater, described source electrode drive circuit comprises:

Multi-task unit, in order to receive gamma voltage signal, and output the first source drive signal is to the first pixel column of described display floater, and described multi-task unit comprises:

First switch, when putting in order to the very first time in the first frame time, produces the first output signal according to the first control signal and the second control signal, and described first switch has to export the first outfan of described first output signal；And

Second switch, during in order to the second time point in described first frame time, produces the second output signal according to the 3rd control signal and the 4th control signal, and described second switch has to export the first outfan of described second output signal；

Wherein, the first outfan of described first switch is coupled to the first outfan of described second switch, and described first source drive signal be described first output signal with described second output signal and.

2. source electrode drive circuit as claimed in claim 1, wherein said first switch comprises the first cmos transmission gate exporting described first output signal, and described second switch comprises to export the described second the second cmos transmission gate exporting signal.

3. source electrode drive circuit as claimed in claim 1, wherein said second time point is after the described very first time puts, and has for the first time delay between described second time point and point of the described very first time.

4. source electrode drive circuit as claimed in claim 1, wherein said multi-task unit also comprises:

3rd switch, during in order to three time point in described first frame time, produces the 3rd output signal, and described 3rd switch has to export the first outfan of described 3rd output signal according to the 5th control signal and the 6th control signal；

Wherein, first outfan of described 3rd switch is coupled to the first outfan of described first switch and the first outfan of described second switch, and described first source drive signal be described first output signal, described second output signal and described 3rd output signal and.

5. source electrode drive circuit as claimed in claim 4, wherein said 3rd switch comprises the 3rd cmos transmission gate exporting described 3rd output signal.

6. source electrode drive circuit as claimed in claim 4, wherein said 3rd time point is after described second time point, and has for the second time delay between described 3rd time point and described second time point.

7. source electrode drive circuit as claimed in claim 1, wherein:

Described multi-task unit is also in order to export the second source drive signal the second pixel column to described display floater；

When described first switch is also in order to four time point in the second frame time after described first frame time, produce the 4th output signal according to described first control signal and described second control signal, and described first switch also has to export the second outfan of described 4th output signal；And

When described second switch is also in order to five time point in described second frame time, produce the 5th output signal according to described 3rd control signal and described 4th control signal, and described second switch also has to export the second outfan of described 5th output signal；

Wherein, second outfan of described first switch is coupled to the second outfan of described second switch, described second source drive signal be described 4th output signal with described 5th output signal and, and the polarity of described first source drive signal and described second source drive signal is contrary.

8. source electrode drive circuit as claimed in claim 7, wherein said first switch also comprises the 4th cmos transmission gate exporting described 4th output signal, and described second switch also comprises to export the described 5th the 5th cmos transmission gate exporting signal.

9. source electrode drive circuit as claimed in claim 7, wherein said 5th time point is after described 4th time point, and has for the 3rd time delay between described 5th time point and described 4th time point.

10. source electrode drive circuit as claimed in claim 1, also comprises output buffer, and described output buffer is coupled to the input of described multi-task unit.