CN1057502C - Elevator speed detecting device - Google Patents
Elevator speed detecting device Download PDFInfo
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- CN1057502C CN1057502C CN94104791A CN94104791A CN1057502C CN 1057502 C CN1057502 C CN 1057502C CN 94104791 A CN94104791 A CN 94104791A CN 94104791 A CN94104791 A CN 94104791A CN 1057502 C CN1057502 C CN 1057502C
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Abstract
To improve speed detection precision through reduction of the generation of a measurement error component by a method wherein an elevator speed is determined based on the values of an UP/DOWN counter to which two phase pulses displaced in a 90 deg. phase are inputted and a timer counter. An UP/DOWN counter means comprises a pulse processing circuit 20A; an UP/DOWN counter 11; and a gate circuit 16, and a timer counter means comprises a timer counter 13; latch circuits 14 and 15; and a gate circuit 17. An inputted phase A pulse 6a and an inverted pulse 6c have respective rise pulses inputted to a waveform differentiating circuit 40 to generate pulses 40a and 40b. When no phase B pulse 6b is inputted, in a case the rise of a phase A pulse 6a occurs, an UP pulse 41a is generated. When the fall of the phase A pulse 6a occurs, a DOWN pulse 41b is generated, the respective pulses are counted by means of an UD counter 11. This constitution determines an accurate U/D count value even when a noise pulse is generated.
Description
The present invention relates to improvement to apparatus for checking lift speed.
Below with reference to Figure 19, Figure 20 and Figure 21 the formation of the existing elevator control gear that discloses in the clear 60-197572 communique of Japanese Patent Application Laid-Open is described, should only relate to the elevator control that utilizes microcomputer by existing elevator control gear, detect irrelevant with speed of the present invention.Figure 19 represents the formation of apparatus for checking lift speed now.The formation of the microcomputer of the box indicating of Figure 20 apparatus for checking lift speed now.The block scheme of Figure 21 is represented the formation of the velocity checking circuits of apparatus for checking lift speed now.
Among Figure 19, the 1st, the car of elevator, the 2nd, balanced weight, the 3rd, volume is hung on the cable wire of rope sheave 4, and the sagging two ends of cable wire 3 are being connected with balanced weight 2 with car 1 respectively.The 5th, drive the electrical motor (M) of above-mentioned rope sheave 4.The 6th, produce with the miles of relative movement of car 1 according to the rotating speed of electrical motor 5 proportional, the A that the phase phasic difference is 90 ° mutually with the B impulse deviser of two-phase pulse (PG) mutually.The 7th, speed control unit.The 8th, the microcomputer of the calculation process that the pulse of sending according to impulse deviser 6 is stipulated.AP and/AP (/ expression is anti-phase) expression A pulse mutually, BP represents B pulse mutually with/BP, 8g is a speed command.
Among Figure 20, microcomputer 8 is made of CPU8a, ROM8b, RAM8c, input circuit 8d, output circuit 8e and velocity checking circuits 9.
Among Figure 21, velocity checking circuits 9 comprises: the forward-backward counter 11 that the forward position of A phase pulse 6a is counted, pulse 6a and 6b differentiate direction identification circuit 12, the timer counter 13 of counting clock (CLK), latch circuit 14 and 15, the gate circuit 16 and 17 of elevator direct of travel mutually with B mutually according to A.The 18th, the data bus of CPU8a.
Below with reference to Figure 22 the work of above-mentioned apparatus for checking lift speed is now described.The sequential chart of Figure 22 is represented the service condition of apparatus for checking lift speed now.
As long as lift car 1 advances at the beginning, promptly electrical motor 5 one changes, the A that impulse deviser 6 will send 90 ° of phase differences corresponding to the rotating speed of electrical motor 5 mutually with B two-phase pulse mutually.These pulses input to the velocity checking circuits 9 in the microcomputer 8.CPU8a program according to the rules is taken into data by velocity checking circuits 9, calculates the gait of march of lift car 1.
The two-phase pulse that velocity checking circuits 9 is advanced in input at first approach axis is distinguished circuit 12, direction identification circuit 12 output direct of travel signal (rising/decline) 12a.This direct of travel signal 12a and the A forward position of input pulse 6a mutually instigate the forward-backward counter 11 of detection position.On the other hand, timer counter 13 clock CLK is according to the rules carrying out increasing progressively counting always, and its value is also locked by latch circuit 14 in the forward position of each A phase pulse 6a.Figure 22 is the sequential chart of the above-mentioned action of expression.
A mutually and B mutually pulse be corresponding to the rotating speed generation of electrical motor 5, each pulse the amount of movement of cooresponding lift car 1 be made as L.Shown in Figure 22 (a), forward-backward counter 11 carries out the increasing or decreasing counting at A phase leading edge of impulse a, b, c each point.Suppose it is ascent direction, being located at the count value that a orders is m, and the count value of ordering at b point and c is m+1 and m+2 respectively just so.Timer counter 13 is locked by latch circuit 14 at this a, b, three time points of c too, and the value of establishing at this moment is respectively x, y, z.
Speed calculation process to CPU8a describes below.CPU8a handles according to the execution cycle (cpu data read cycle) of common regulation.Therefore supposing between the d-e among Figure 22 the read cycle for the value of the value of above-mentioned forward-backward counter and timer counter, then is certain substantially during this.As shown in the figure, if CPU8a will fetch data at d point and e reading, then forward-backward counter 11 value of ordering at d is m, and the value of ordering at e is m+2.Therefore the amount of movement X of lift car 1 is in the meantime
X＝{(m+2)-m}×L＝2L，
With the corresponding elapsed time T of this amount of movement X be
T＝(z-x)t，
T is the cycle of clock shown in Figure 22 (c).
Therefore, elevator speed V at this moment is
V＝X/T＝2L/{(z-x)t}。
When speed surpassed this value, the A phase pulse count during the d-e just increased, but still can be according to same processing computation speed.The sequential that the value of timer counter reads according to the data to forward-backward counter 11 (the RDOL time among Figure 21) is locked, this be for the value of the timer counter that remains on time for reading point (therefore, for example when reading, the d point can read the value of x definitely) with respect to m.
Not only at above-mentioned high-speed region, and can carry out more correctly also at low-speed region that speed detects, other existing apparatus for checking lift speed are as described below.
With reference to Figure 23 other existing apparatus for checking lift speed that disclose in the flat 4-344466 communique of Japanese Patent Application Laid-Open are described, this communique has proposed the apparatus for checking lift speed in a kind of low-speed region.Figure 23 is the formation block diagram of the velocity checking circuits of other existing apparatus for checking lift speed.
In Figure 23, velocity checking circuits comprises the pulse processing circuit 20 with direction identification function; Input be equivalent to A phase, B phase ,/A mutually with the OR circuit 21 of pulse 20c, 20d, 20e and the 20f in/B each forward position mutually; Latch circuit 22～27 and the gate circuit 28 and 29 that is being connected with data bus 18.Other symbolic representations part of symbol as hereinbefore are identical or suitable.Other component parts as hereinbefore in addition.
Below with reference to Figure 24 the work of other existing apparatus for checking lift speed is described.The sequential chart of Figure 24 is represented the action of other existing apparatus for checking lift speed.
From the A of impulse deviser 6 input mutually with B mutually pulse 6a～6d at first enter pulse processing circuit 20.The signal 20a of this pulse processing circuit 20 outputs and A mutually pulsion phase with, signal 20b be according to A mutually with the B direct of travel signal of pulse differentiation rising/descent direction mutually.And as previously mentioned, signal 20a and 20b make forward-backward counter 11 work.On the other hand, the output 13a of timer counter 13 is locked by latch circuit 14 in the forward position of A phase pulse.
Here, signal 20c, 20d, 20e and the 20f of pulse processing circuit 20 output be respectively A mutually with the B forward position of pulse and the signal that the edge, back produces according to clock CLK input sample mutually, they input to OR circuit 21.Therefore, the output signal 21a of OR circuit 21, as shown in figure 24, export on the forward position and the edge, back of pulse mutually with B mutually at A.And signal 21a is the energizing signal of latch circuit 22～26.
The output 13a of timer counter 13 at first inputs to latch circuit 22, according to A mutually and B latch circuit 23 → 24 → 25 → 26 is passed through successively along the energizing signal that produces in the forward position of pulse and back mutually.The output 22a of latch circuit 22 and the output 26a of latch circuit 26 are all the time by the data of the energizing signal of same phase place locking.Be exactly in the forward position-forward position of A phase pulse, the forward position-forward position of B phase pulse, the back edge-back of the back edge of A phase pulse-edge, back and the pulse of B phase is along the data of each time point locking.Suppose that it is 22a that present latching exported, then a preceding latch data of same phase place is exactly 26a.
Figure 24 has represented this situation chronologically, utilizes Figure 24 that the processing that speed detects is described here.If the amount of movement of the A lift car that each pulse is mutually represented with B mutually is L, A phase between the pulse rising stage, B phase between the pulse rising stage, between A phase pulse decrement phase with B mutually between the pulse decrement phase, owing to be same phase place, so can be taken into more stable waveform (having reduced the influence of the property difference etc. of input circuit cell).Therefore establishing the amount of movement in 1 cycle is L, computation speed.
In Figure 24, suppose CPU8a the cycle between d-e read in data, then only with regard to above-mentioned formation now, owing to there is not the forward position point of A phase pulse, the value of the forward-backward counter that reads at d point and e point and the value of timer counter will be the same, not change.Therefore when elevator speed lowers, just switch to a series of latch circuit computation speeds by Figure 23 bottom.In other words, if CPU8a will be at e point read data, then timer counter 13 is the value that locks on the back edge of B phase pulse at the up-to-date value Y of this time point, is the output 22a of latch circuit 22.At this moment the value of the output 26a of latch circuit 26 becomes the back data X along locking of the preceding B phase pulse of one-period.Value at counting machine is advanced for the elevator amount of movement during the Y is aforesaid L from X, is t as the cycle of establishing clock CLK therefore, and then elevator can be asked by following formula at the speed V of this time point:
V＝L/{(Y-X)t}，
T is the cycle of clock CLK.
Like this, it is always certain to establish miles of relative movement L, CPU8a the A of the time point of read counter mutually with B mutually during the before and after edge of pulse, utilize up-to-date counter lock deposit data computing time, so detection speed more correctly.And when the CPU8a read data, the same with aforementioned conventional example, (during RD4L output) just latchs the data before the one-period earlier when reading up-to-date latch data.
Concerning above-mentioned existing apparatus for checking lift speed, the A that problem is 90 ° of phase differences mutually with B mutually pulse be exactly the detection mode of the best when normally importing.Therefore when this regular pulse, dash such as Trembling Pulse having taken place at low-speed region, or when because of reasons such as interference noise count having taken place, regular pulse might as well, noise count might as well, the capital irrespectively is counted in the forward position of A phase pulse and timer counter 13 under lock and key each other, so the error percentage of detection speed is big, just detection speed correctly.
For example, Figure 25 represents that existing apparatus for checking lift speed has had the situation of noise count.Figure 26 is illustrated in the situation that noise count and Trembling Pulse are dashed has taken place in the existing apparatus for checking lift speed.The pulse that indicates * number among two figure is regular pulse.Also having a problem, is exactly the reasons such as readjustment horizontal balance owing to elevator, and when situation such as variation has taken place when direct of travel, detection speed correctly.
If at this moment existing ask speed as aforementioned routinely, in Figure 25, the value that forward-backward counter 11 is ordered at d becomes m so, and the value of ordering at e becomes m+2 and adds noise count ± α, i.e. m+2 ± d, and the amount of movement X of the lift car 1 during this d-e is as follows:
X＝{(m+2±α)-m}×L＝(2±α)L。
With the corresponding elapsed time T of this amount of movement X, because noise count, become and comprise the time β that has passed through, following expression:
T＝(Z+β-X)t
That is, speed V can be tried to achieve by following formula:
V＝X/T＝(2±α)L/{(Z+β-X)t)。
Therefore, because the error of α and β can not be tried to achieve correct speed V.Especially α only counts the number of noise count, and error can be very big.β can see the noise count that takes place between the forward position of A phase pulse and the A error in the elapsed time between the leading edge of impulse mutually as, can see the time error of a pulse that is the poorest regular pulse as.
In Figure 26, the two all is the latch circuit of shift register for regular pulse of two-phase and noise count, so L alters a great deal with the mode that noise count takes place.As shown in the figure, noise count of every generation just has been counted as half L ' into the amount of movement L of a regular pulse.Ask speed if resemble the aforementioned conventional example, reading a little of CPU, Counter Value is L by the amount of movement that X enters the lift car 1 during the Y, and because The noise, speed V but is
V＝L/{(y-γ)t}。
(y-x) t compares with the regular elapsed time, has produced (the so big error of t of γ-x).In other words,, will pin timer counter 13, make the data displacement on the forward position and the edge, back of noise count if be mixed with noise count, thereby the time that can not measure the one-period of actual pulse.
Purpose of the present invention just is to address the above problem, though obtain taken place that Trembling Pulse is dashed or the situation of noise count under also can reduce error percentage, improve the apparatus for checking lift speed of speed accuracy of detection.
Purpose also is to obtain not to be subjected to the influence of noise count, can detect the apparatus for checking lift speed of the variation (direct of travel will change when the noise count pulse takes place usually) of direct of travel and direct of travel.
First invention of the present invention is a kind of apparatus for checking lift speed, comprising:
Corresponding to the rotation of electrical motor produce have 90 degree phase differences first mutually with second impulse deviser of pulse mutually;
Output based on described first mutually with second mutually pulse direct of travel signal, count pulse and with described first mutually and the pulse processing circuit of the second phase rising edge of a pulse and the cooresponding energizing signal of falling edge;
Consider described direct of travel signal, the forward-backward counter that described count pulse is counted;
The timer conter that clock pulse is counted;
Latch the means that latch of described timer conter output successively by described energizing signal; And
Try to achieve elevator speed in the high-speed region according to the value of described forward-backward counter and described timer conter, and try to achieve the CPU of the elevator speed in the low-speed region according to described forward-backward counter and the described value that latchs means,
It is characterized in that,
Described pulse processing circuit when the first phase pulse is in certain level, according to the positive rise pulse and the falling edge pulse of the second phase pulse, generates the described count pulse of output.
Second invention of the present invention is a kind of apparatus for checking lift speed, comprising:
Corresponding to the rotation of electrical motor produce have 90 degree phase differences first mutually with second impulse deviser of pulse mutually;
Output based on described first mutually with second mutually pulse direct of travel signal, count pulse and with described first mutually and the pulse processing circuit of the second phase rising edge of a pulse and the cooresponding energizing signal of falling edge;
Consider described direct of travel signal, the forward-backward counter that described count pulse is counted;
The timer conter that clock pulse is counted;
Latch the means that latch of described timer conter output successively by described energizing signal; And
Try to achieve elevator speed in the high-speed region according to the value of described forward-backward counter and described timer conter, and try to achieve the CPU of the elevator speed in the low-speed region according to described forward-backward counter and the described value that latchs means,
It is characterized in that,
Described pulse processing circuit, only with described first mutually and second first pulse of alternately importing in the middle of the pulse mutually be effective impulse, when the first phase effective impulse is in certain level,, generate the described count pulse of output according to the positive rise pulse and the falling edge pulse of the second phase effective impulse.
The 3rd invention of the present invention is the apparatus for checking lift speed of first or second invention, it is characterized in that,
Described energizing signal, be only with described first mutually and second mutually in the middle of the pulse alternately first pulse of input be effective impulse, with the energizing signal of described first phase and the second phase effective impulse positive rise and the corresponding output of falling edge.
The 4th invention of the present invention, it is the apparatus for checking lift speed of the 3rd invention, it is characterized in that, also comprise: detect direct of travel according to described clock pulse, described direct of travel signal and described energizing signal, output one sign shows that the direct of travel counter-rotating in its change point direct of travel counter-rotating detects means
Described CPU is according to described sign, makes that when direct of travel reverses described forward-backward counter and the described value that latchs means are invalid, tries to achieve elevator speed in the low-speed region according to previous value.
The 5th invention of the present invention, be the apparatus for checking lift speed of the 4th invention, it is characterized in that described CPU is according to described sign, make that when direct of travel reverses the value of described forward-backward counter and described timer conter is invalid, try to achieve elevator speed in the high-speed region according to previous value.
The related apparatus for checking lift speed of first aspect present invention is to have following part, and asks the device of elevator speed according to the value of following forward-backward counter and following timer counter.
(1) two-phase pulse of 90 ° of the phase differences that produce corresponding to the rotating speed of electrical motor of input, when the pulse of one phase is in certain state, the forward-backward counter that the forward position pulse and the trailing edge of its another phase pulse are counted.
(2) timer counter that clock is counted.
The related apparatus for checking lift speed of second aspect present invention is to have following part, and asks the device of elevator speed according to the value of following forward-backward counter and following timer counter.
(1) two-phase pulse of 90 ° of the phase differences that produce corresponding to the rotating speed of electrical motor of input, only effective impulse is used as in the 1st pulse of alternately importing in these two-phase pulses, when the effective impulse of one phase is in certain state, the forward-backward counter that forward position pulse that the effective impulse of its another phase is dashed and trailing edge are counted.
(2) timer counter that clock is counted.
The related apparatus for checking lift speed of third aspect present invention is to have following part, and asks the device of elevator in the speed of low regime according to following latch data.
(1) two-phase pulse of 90 ° of the phase differences that produce corresponding to the rotating speed of electrical motor of input, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase effective impulse and back along the output of pinning the timer that Measuring Time uses successively, with the timer counter of the latch data that obtains every same phase place.
The related apparatus for checking lift speed of fourth aspect present invention is to have following part, and asks the device of elevator in the speed of low regime according to following latch data and following direct of travel.
(1) two-phase pulse of 90 ° of the phase differences that produce corresponding to the rotating speed of electrical motor of input, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase efficient clock and back along the output of pinning the timer that Measuring Time uses successively, with the timer counter of the latch data that obtains every same phase place.
(2) detect the direct of travel counter-rotating testing circuit of direct of travel according to above-mentioned two-phase pulse and above-mentioned two-phase effective impulse.
The related apparatus for checking lift speed of fifth aspect present invention is to have following part, and the device of asking elevator speed according to the value and the following direct of travel of following forward-backward counter and following timer counter.
(1) two-phase pulse of 90 ° of the phase differences that produce corresponding to the rotating speed of electrical motor of input, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, when the effective impulse of one phase is in certain state, to the forward position pulse of the effective impulse of its another phase and the forward-backward counter that trailing edge is counted.
(2) timer counter that clock is counted.
(3) detect the direct of travel counter-rotating testing circuit of direct of travel according to above-mentioned two-phase pulse and above-mentioned two-phase effective impulse.
In the related apparatus for checking lift speed of first aspect present invention, the two-phase pulse that the phase difference that is produced corresponding to the rotating speed of electrical motor by forward-backward counter means inputs is 90 °, forward position pulse and trailing edge to the pulse of its another phase when the pulse of one phase is in certain state are counted.
By timer counter clock is counted.
In the related apparatus for checking lift speed of second aspect present invention, the two-phase pulse that the phase difference that is produced corresponding to the rotating speed of electrical motor by forward-backward counter input is 90 °, only in these two-phase pulses alternately first pulse of input be used as effective impulse, forward position pulse and trailing edge to the effective impulse of its another phase when the effective impulse of one phase is in certain state are counted.
By timer counter clock is counted in addition.
In the related apparatus for checking lift speed of third aspect present invention, the two-phase pulse that the phase difference that is produced corresponding to the rotating speed of electrical motor by timer counter input is 90 °, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase effective impulse and back along the output of pinning the timer that Measuring Time uses successively, to obtain the latch data of every same phase place.
In the related apparatus for checking lift speed of fourth aspect present invention, the two-phase pulse that the phase difference that is produced corresponding to the rotating speed of electrical motor by timer counter input is 90 °, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase effective impulse and back along the output of pinning the timer that Measuring Time uses successively, to obtain the latch data of every same phase place.
Detect direct of travel by direct of travel counter-rotating testing circuit according to above-mentioned two-phase pulse and above-mentioned two-phase effective impulse in addition.
In the related apparatus for checking lift speed of fifth aspect present invention, the two-phase pulse that the phase difference that is produced corresponding to motor speed by forward-backward counter input is 90 °, only in these two-phase pulses alternately first pulse of input be used as effective impulse, forward position pulse and trailing edge to the effective impulse of its another phase when the effective impulse of one phase is in certain state are counted.
By timer counter clock is counted in addition.
Also detect direct of travel according to above-mentioned two-phase pulse and above-mentioned two-phase effective impulse by direct of travel counter-rotating testing circuit.
In the related apparatus for checking lift speed of first aspect present invention, as mentioned above, the two-phase pulse that possesses 90 ° of phase differences that input produces corresponding to motor speed, forward-backward counter of when the pulse of one phase is in certain state, the forward position pulse and the trailing edge of its another phase pulse being counted and the timer counter that clock is counted, and ask elevator speed according to the value of above-mentioned forward-backward counter and above-mentioned timer counter, even therefore the noise count input is arranged does not handle it yet, effect is to prevent the miscount of counting machine and the mistake breech lock of timer, high Precision Detection speed.
In the related apparatus for checking lift speed of second aspect present invention, as mentioned above, the two-phase pulse that possesses 90 ° of phase differences that input produces corresponding to motor speed, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, forward-backward counter of when the effective impulse of one phase is in certain state, the forward position pulse and the trailing edge of its another phase effective impulse being counted and the timer counter that clock is counted, and ask elevator speed according to the value of above-mentioned forward-backward counter and above-mentioned timer counter, even therefore the noise count input is arranged does not handle its pulse yet, effect is to prevent the miscount of counting machine and the mistake breech lock of timer, high Precision Detection speed.
In the related apparatus for checking lift speed of third aspect present invention, as mentioned above, the two-phase pulse that possesses 90 ° of phase differences that input produces corresponding to motor speed, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase effective impulse and back along the output of pinning the timer that Measuring Time uses successively, timer counter with the latch data that obtains every same phase place, and ask the speed of elevator in low regime according to above-mentioned latch data, even therefore the noise count input is arranged does not handle its pulse yet, effect is to prevent the mistake breech lock of timer, high Precision Detection speed.
In the related apparatus for checking lift speed of fourth aspect present invention, as mentioned above, possesses the two-phase pulse of 90 ° of phase differences that input produces corresponding to motor speed.Only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, in the forward position of above-mentioned two-phase effective impulse and back along the output of pinning the timer that Measuring Time uses successively, timer counter with the latch data that obtains every same phase place, and the direct of travel counter-rotating testing circuit that detects direct of travel according to above-mentioned two-phase pulse and above-mentioned two-phase effective impulse, and ask the speed of elevator in low regime according to above-mentioned latch data and above-mentioned direct of travel, even therefore the noise count input is arranged does not handle it yet, effect is to prevent the mistake breech lock of timer, high Precision Detection speed.In addition, if direct of travel reverses, just make the value of timer counter at this moment invalid, and the last value detection speed that reads in of utilization, therefore when actual direction counter-rotating takes place because of reasons such as readjustment horizontal balances, or when having taken place to relate to the noise of each phase, use wrong timer count value with regard to unlikely, its effect is to carry out speed control reposefully.
In the related apparatus for checking lift speed of fifth aspect present invention, as mentioned above, the two-phase pulse that possesses 90 ° of phase differences that input produces corresponding to motor speed, only effective impulse is used as in first pulse of alternately importing in these two-phase pulses, forward-backward counter of when the effective impulse of one phase is in certain state, the forward position pulse and the trailing edge of its another phase effective impulse being counted and the timer counter that clock is counted and the direct of travel counter-rotating testing circuit that detects direct of travel according to above-mentioned two-phase effective impulse, and the speed of asking elevator according to the value and the above-mentioned direct of travel of above-mentioned forward-backward counter and above-mentioned timer counter, even therefore the noise count input is arranged does not handle its pulse yet, its effect is to prevent the miscount of counting machine and the mistake breech lock of timer, high Precision Detection speed.In addition, if direct of travel reverses, just make the value of forward-backward counter at this moment and timer counter invalid, and the last value detection speed that reads in of use, therefore when actual direction counter-rotating takes place because of reasons such as readjustment horizontal balances, or when having taken place to relate to the noise of each phase, use wrong reversible counting value and timer count value with regard to unlikely, its effect is to carry out speed control reposefully.
Fig. 1 is that the velocity checking circuits of the embodiment of the invention 1 constitutes block diagram.
Fig. 2 is the pulse processing circuit pie graph of the velocity checking circuits of the embodiment of the invention 1.
Fig. 3 is the sequential chart of action in rising when operation of the expression embodiment of the invention 1.
Fig. 4 is the sequential chart of action in decline when operation of the expression embodiment of the invention 1.
Fig. 5 is the sequential chart of the action of the expression embodiment of the invention 1 when lacking the pulse of B phase for a long time.
Fig. 6 is the pulse processing circuit pie graph of the velocity checking circuits of the embodiment of the invention 2.
Fig. 7 is the sequential chart of action in rising when operation of the expression embodiment of the invention 2.
Fig. 8 is the sequential chart of action in decline when operation of the expression embodiment of the invention 2.
Fig. 9 is the sequential chart of the action of the expression embodiment of the invention 2 when lacking the pulse of B phase for a long time.
Figure 10 is that the velocity checking circuits of the embodiment of the invention 3 constitutes block diagram.
Figure 11 is the pie graph of pulse processing circuit in the velocity checking circuits of the embodiment of the invention 3.
Figure 12 is the sequential chart of the action of the expression embodiment of the invention 3.
Figure 13 is the sequential chart of the action of the expression embodiment of the invention 3.
Figure 14 is that the velocity checking circuits of the embodiment of the invention 4 constitutes block diagram.
Figure 15 is the sequential chart of the action of the expression embodiment of the invention 4.
Figure 16 is the sequential chart of the action of the expression embodiment of the invention 4.
Figure 17 be the expression embodiment of the invention 4 from rising to the sequential chart of the action when descending operation.
Figure 18 be the expression embodiment of the invention 4 from dropping to the sequential chart of the action when rising operation.
Figure 19 is the pie graph of apparatus for checking lift speed now.
Figure 20 is that the microcomputer of apparatus for checking lift speed now constitutes block diagram.
Figure 21 is that the velocity checking circuits of apparatus for checking lift speed now constitutes block diagram.
Figure 22 is a sequential chart of representing the action of apparatus for checking lift speed now.
Figure 23 is that the velocity checking circuits of other apparatus for checking lift speed now constitutes block diagram.
Figure 24 is the sequential chart of the action of other apparatus for checking lift speed now of expression.
Figure 25 is a sequential chart of representing the subject matter of apparatus for checking lift speed now.
Figure 26 is the sequential chart of the subject matter of other apparatus for checking lift speed now of expression.
Embodiments of the invention are described with reference to the accompanying drawings.
The formation of the embodiment of the invention 1 is described below with reference to Fig. 1 and Fig. 2.Fig. 1 is that the velocity checking circuits of the embodiment of the invention 1 constitutes block diagram, and Fig. 2 is the pulse processing circuit pie graph of the velocity checking circuits of the embodiment of the invention 1.
As shown in Figure 1, embodiment 1 possesses the pulse processing circuit 20A that the miscount of the forward-backward counter 11 that causes because of noise is revised.Other component parts are identical with the velocity checking circuits 9 of above-mentioned apparatus for checking lift speed now.
As shown in Figure 2, pulse processing circuit 20A possesses: in order to the waveform differential circuit 40 of the leading edge of impulse that detects A phase pulse 6a and rp pulse 6c thereof; Provide the AND circuit 41 of output when importing in order to the differentiated waveform that A phase pulse 6a or its rp pulse 6c are arranged under the situation that does not have B phase pulse 6b input; In order to the OR circuit 42 of output rising pulse 41a and falling pulse 41b and according to A mutually with the B direction identification circuit 43 of the direct of travel of pulse 6a and 6b detection car 1 mutually.
The forward-backward counter that first aspect present invention is related in the invention described above embodiment 1, is made of pulse processing circuit 20A, forward-backward counter 11 and gate circuit 16.The timer counter that first aspect is related, in the foregoing description 1, by timer counter 13, latch circuit 14 and 15, and gate circuit 17 constitutes.
The service condition of embodiments of the invention 1 is described below with reference to Fig. 3, Fig. 4 and Fig. 5.Fig. 3 is the sequential chart of action in rising when operation of the expression embodiment of the invention 1.Fig. 4 is the sequential chart of action in decline when operation of the expression embodiment of the invention 1.Fig. 5 is the sequential chart of the action of the expression embodiment of the invention 1.Explanation about speed calculation is the same with existing embodiment, will not give unnecessary details.
Even if pulse processing circuit 20A is in order to offset the noise count that can take place.Waveform differential circuit 40 is in order to the A phase pulse 6a that detects input and the forward position pulse of rp pulse 6c thereof, production burst 40a and 40b.Shown in Fig. 3 (a)～(c) and Fig. 4 (a)～(c), when also not having B phase pulse 6b input, produce the count pulse of forward-backward counter 11.Promptly under the situation that is not having B phase pulse 6b input (low level),, just obtain the pulse 41a that rises if there is the forward position of A phase pulse 6a to take place, and if the back along taking place of A phase pulse arranged, just obtain falling pulse 41b, counted by forward-backward counter 11 respectively.Like this, shown in Fig. 3 (d) and Fig. 4 (d), even there is noise count that correct reversible counting value (m, m+1, m+2 or m, m-1, m-2) takes place also can obtain.
The state (low level) that does not below just have the pulse of B phase, the counting mode of the forward-backward counter 11 when the pulse generation of A phase is arranged is described.Otherwise, the state (high level) of B phase pulse is arranged, the counting mode of the forward-backward counter 11 the when pulse generation of A phase is arranged is too.But the forward position pulse of A phase at this moment is that counting is descended, and the trailing edge of A phase rises counting.And when the pulse of A phase certain (high or low level),, also can carry out the counting of the same manner with the action opposite with above-mentioned action even the pulse generation of B phase is arranged.
This embodiment 1 causes miscount in order to prevent because of the noise count of easy forward-backward counter 11, rather than comprise that timer counter 13 improves precision, therefore as shown in Figure 5, under situations such as the pulse of B phase has disappeared, the count value of forward-backward counter 11 is normal, but the value of timer counter 13 has error.
Embodiments of the invention 1 as previously mentioned, possess the impulse deviser 6 that produces the two-phase pulse of 90 ° of phase differences in the high velocity of elevator corresponding to the rotating speed of electrical motor 5; Be under certain state (being stabilized in high level or low level) forward position pulse and trailing edge in the pulse of B phase, perhaps be under certain state (being stabilized in high level or low level) the pulse processing circuit 20A that forward position pulse and trailing edge according to the B phase produce count pulse in the pulse of A phase according to the A phase; And the forward-backward counter 11 that above-mentioned count pulse is counted.Even therefore there is the noise count input also it not to be handled, its effect is to prevent forward-backward counter 11 miscounts, high Precision Detection speed.
The formation of the embodiment of the invention 2 is described below with reference to Fig. 6.Fig. 6 is the pulse processing circuit pie graph of the embodiment of the invention 2.Other component parts are identical with the foregoing description 1.
As shown in Figure 6, the pulse processing circuit 20B of present embodiment 2 has increased the circuit that the miscount of the forward-backward counter 11 that causes because of noise count is revised, and possesses the shielding noise count, promptly noise count is not counted, not the circuit of breech lock.That is to say to possess in order to detect the waveform differential circuit 40 of leading edge of impulse; Make pulse synchronizationization behind the differential with clock CLK again, to produce the pulse synchronization circuit (SYNC) 39 of count pulse 39a and 39c; In the AND circuit 41 that when the differentiated waveform of A phase or its anti-phase count pulse 39a and 39c is imported, provides output under the situation that does not have B phase pulse 6b input; The OR circuit 42 of output rising pulse and falling pulse; In case there is noise count to take place just to provide output so that counting and the invalid noise count screened circuit 44 of latch-up signal; And direction identification circuit 43.
Noise count screened circuit 44 comprises output A phase and the differentiated waveform 40a of rp pulse and the OR circuit 45 of 40c; Output B phase and the differentiated waveform 40b of rp pulse and the OR circuit 46 of 40d; Hook switch action type T binary pair 47 and J-K flip flop 48.
The forward-backward counter that second aspect present invention is related in the embodiment 2 of the invention described above, comprises pulse processing circuit 20B, forward-backward counter 11 and gate circuit 16; And the related timer counter of second aspect comprises timer counter 13, latch circuit 14 and 15 and gate circuit 17 in embodiments of the invention 1.
Below with reference to Fig. 7, Fig. 8 and Fig. 9 the service condition of the embodiment of the invention 2 is described.Fig. 7 is the sequential chart of action in rising when operation of the expression embodiment of the invention 2.Fig. 8 is the sequential chart of action in decline when operation of the expression embodiment of the invention 2.Fig. 9 is the sequential chart of the action of the expression embodiment of the invention 2.
Even pulse processing circuit 20B be when having noise count to take place also to it does not count, the circuit of breech lock not.Waveform differential circuit 40 is differentiated pulse 40a～40d with the forward position impulse transfer of A, B two-phase pulse and their the rp pulse 6a～6d of input.On the other hand, A phase and anti-phase differentiated pulse 40a thereof and 40c become the energizing signal of T binary pair 47, and the output of T binary pair 47 becomes the energizing signal of the J-K flip flop 48 of next stage again.And B phase and anti-phase differentiated pulse 40b thereof and 40d become the reset signal of above-mentioned T binary pair 47 and J-K flip flop 48.Count pulse 39a and 39c that the output 44a of noise count screened circuit 44 imports when making high level by AND circuit 41 are effective, and make the count pulse 39a and the 39c that are judged as the noise count input invalid when low level.
The service condition of noise count screened circuit 44 then is described.General if ascent direction, regular pulse will be successively in A phase forward position, B phase forward position, A mutually edge, back and B mutually the back along producing.If descent direction then produces by opposite order.Utilize this point, will be considered as effective impulse by the pulse of above-mentioned order input, and with the pulse of other order (A phase forward position for example, A mutually the back along or the pulse of its opposite order input etc.) all be used as noise, make it invalid.That is if continuous 2 A phase forward positions or trailing edge are imported into, then the output 44a of JK flip-flop 48 just becomes low level from high level, and just the output with AND circuit 41 shields.Thereafter, when B phase forward position or trailing edge input, T binary pair 47 and J-K flip flop 48 just are reset, and the output of AND circuit 41 has become effectively again.At the output 44a of this noise screening circuit 44 is effective (high level), and when not having B phase pulse input (low level), if have the forward position of A phase pulse to take place then be the rising pulse, if the pulse of A phase arranged back along taking place then be falling pulse, counted by forward-backward counter 11 respectively.Usually, the input of pulse be A phase → B phase →/the A phase →/the B phase, or its opposite order, T binary pair 47 only because of A phase pulse hook switch once, when the pulse of B phase is imported, be reset.Therefore, output 44a is a high level.
Like this, as shown in Figure 7 and Figure 8, even have noise count take place also to try to achieve correct reversible counting value (m, m+1, m+2 or m, m-1, m-2).
In addition, the value of timer counter 13 contains as shown in Figure 8 by the timer Puzzle lock deposit data of short pulse (m-2) locking of cpu data read cycle time point and the error percentage (a-b) of regular pulse *, but compare with the error percentage of the timer Puzzle lock deposit data of prior art, precision is to have improved greatly.The error time of existing timer counter with noise count a situation arises 0～+ ∞ between, and the error time of the timer counter of present embodiment 2 only for-T/4～0 (T is the cycle of input pulse 6a～6d).
Moreover, the error of timer counter shown in Figure 5, as shown in Figure 9, also owing to there being noise count screened circuit 44 that continuous A phase forward position or trailing edge from the 2nd are shielded, neither carry out forward-backward counter, do not latch the timer enumeration data yet, therefore can obtain correct reversible counting value and timer count value, correct detection speed.
Embodiments of the invention 2 as previously mentioned, possess the impulse deviser 6 that produces the two-phase pulse of 90 ° of phase differences in the high velocity of elevator corresponding to the rotating speed of electrical motor 5; Only effective impulse is used as in A, B two first pulse that takes place that alternates, and is made, only according to the forward position pulse of a certain phase of effective impulse and the pulse processing circuit 20B of trailing edge generation count pulse from the 2nd input pulse void in whole; And the forward-backward counter 11 that above-mentioned count pulse is counted.Even therefore there is the noise count input also it not to be handled, its effect is to prevent the mistake breech lock of forward-backward counter 11 miscounts and timer counter 13, high Precision Detection speed.
The formation of the embodiment of the invention 3 is described below with reference to Figure 10 and Figure 11.Figure 10 is that the velocity checking circuits of the embodiment of the invention 3 constitutes block diagram.Figure 11 is the pie graph of pulse processing circuit in the velocity checking circuits of the embodiment of the invention 3.
As shown in figure 10, present embodiment 3 is the speed detection modes that increase low regime on the speed detection mode basis of the elevator high velocity of embodiment 1 and embodiment 2, except that possess circuit that the miscount of the forward-backward counter 11 that causes because of noise count is revised and shielding noise count, promptly make it to disregard number, not the circuit of breech lock, also possess and contain the pulse processing circuit 20C that prevents from because of noise count the timer count value to be missed the circuit of breech lock in low regime.
As shown in figure 11, pulse processing circuit 20C comprises: in order to detect the waveform differential circuit 40 of leading edge of impulse; Make pulse synchronizationization behind the differential with clock CLK once more, to generate the pulse synchronization circuit 39 of counting latch pulse 39a～39d; In case there is noise count to take place just to provide output so that counting and the invalid noise count screened circuit 44A of latch-up signal; AND circuit 50; Direction identification circuit 43; AND circuit 41 and OR circuit 42.
And for example shown in Figure 11, noise count screened circuit 44A comprises: the OR circuit 45 of the differentiated waveform of output A phase and rp pulse thereof; The OR circuit 46 of the differentiated waveform of output B phase and rp pulse thereof; Hook switch action type T binary pair 47a and 47b; J-K flip flop 48a and 48b; And OR circuit 49.Here, T binary pair 47a betides the A noise count of pulse mutually with J-K flip flop 48a in order to shielding; T binary pair 47b betides the B noise count of pulse mutually with J-K flip flop 48b in order to shielding.OR circuit 49 output will betide signal that the noise count of above-mentioned A phase pulse shielded and will betide the B signal that shielded of the noise count of pulse mutually, become the output 49a of noise count screened circuit 44A.When this signal 49a was high level, the output of pulse synchronization circuit 39 was actvies, AND circuit 50 output latch pulse 20c～20d.And when signal 49a was low level, the output of pulse synchronization circuit 39 was invalid, the output conductively-closed of AND circuit 50.
The related timer counter of third aspect present invention comprises pulse processing circuit 20C, OR circuit 21, timer counter 13, latch circuit 22～27 and gate circuit 28 and 29 in the embodiment of the invention 3.
Below with reference to Figure 12 and Figure 13 the service condition of embodiments of the invention 3 is described.Figure 12 is the sequential chart of the rising run action of expression embodiments of the invention 3.Figure 13 is the sequential chart of the action of the expression embodiment of the invention 3.
A, B two-phase pulse and the rp pulse thereof of input becomes differentiated pulse 40a～40d by waveform differential circuit 40 with their rising edge signal.On the other hand, A phase and anti-phase differentiated pulse 40a thereof and 40c become the energizing signal of T binary pair 47a, and the output of T binary pair 47a becomes the energizing signal of the J-K flip flop 48a of next stage again.And B phase and anti-phase differentiated pulse 40b thereof and 40d become the reset signal of above-mentioned T binary pair 47a and J-K flip flop 48a.Equally, B phase and anti-phase differentiated pulse 40b thereof and 40d become the energizing signal of T binary pair 47b, and the output of T binary pair 47b becomes the energizing signal of the J-K flip flop 48b of next stage again.And A phase and anti-phase differentiated pulse 40a thereof and 40c become the reset signal of above-mentioned T binary pair 47b and J-K flip flop 48b.When the output 49a of noise count screened circuit 44A was high level, AND circuit 50 made the pulse 39a of input, 39b, and 39c and 39d are effective; And when 49a was low level, AND circuit 50 made the pulse 39a that is judged as the noise count input, 39b, and 39c and 39d are invalid.
The service condition of noise count screened circuit 44A then is described.General if ascent direction, regular pulse will be successively in A phase forward position, B phase forward position, A mutually edge, back and B mutually the back along producing.If descent direction then produces by opposite order.Utilize this point, will be considered as effective impulse by the pulse of above-mentioned order input, and with the pulse of other order (A phase forward position for example, the pulse of back mutually edge of A or the input of its reversed sequence, and B phase forward position, the pulse of back mutually edge of B or the input of its reversed sequence etc.) all be used as noise, make it invalid.That is if continuous 2 A phase forward positions or trailing edge are imported into, then the output 44a of J-K flip flop 48a just becomes low level from high level, and the output of OR circuit 49 just shields the output of AND circuit 50.Thereafter, when B phase forward position or trailing edge input, T binary pair 47a and J-K flip flop 48a just are reset, and the output 49a of noise count screened circuit 44A just becomes high level, so the output of AND circuit 50 has become effectively again.
Equally, if continuous 2 B phase forward positions or trailing edge are imported into, then the output 44b of J-K flip flop 48b just becomes low level from high level, and just the output by OR circuit 49 shields the output of AND circuit 50.Thereafter, when A phase forward position or trailing edge input, T binary pair 47b and J-K flip flop 48b just are reset, and the output 49a of noise count screened circuit 44A just becomes high level, so the output of AND circuit 50 has become effectively again.Usually, the input of pulse be A phase → B phase →/the A phase →/the B phase, or its opposite order.Therefore T binary pair 47a only because of A phase pulse hook switch once, when the pulse of B phase is imported, be reset, the output 44a of J-K flip flop 48a is a high level.On the other hand, T binary pair 47b only because of B phase pulse hook switch once, when the pulse of A phase is imported, be reset, the output 44b of J-K flip flop 48b is a high level.
In sum, A phase pulse when input, the output hook switch of T binary pair 47a once ,/Q becomes low level.The T binary pair 47b and the J-K flip flop 48b of the signal that B phase direction takes place in generation noise count masks are resetted.Then, if B phase pulse input is arranged, then action is with above-mentioned opposite, and the T binary pair 47a and the J-K flip flop 48a of the signal that generation masks the noise count of A phase aspect generation are resetted, the output hook switch of T binary pair 47b once ,/Q becomes low level.At this moment, the output 49a of noise count screened circuit 44A is a high level, is actv..And then then repeat above-mentioned action if any/A phase pulse input.But if/pulse of B phase imports into, be that twice continuous B phase pulse imported, so the output of T binary pair 47b hook switch again, energizing signal enters the JK flip-flop 48b of next stage, the output 44b of J-K flip flop 48b becomes low level, and the output of AND circuit 50 is shielded.After this till the pulse input that A phase aspect is arranged, all conductively-closeds always of the input of B phase aspect pulse.And the output 44a of noise count screened circuit 44A inputs to AND circuit 41, and is identical with the action of previous embodiment 2.
Like this, as shown in figure 12, read the time point of (2) at cpu data,, also can correctly obtain the corresponding time t of miles of relative movement L (y-x) with a pulse representative even there is noise count to take place.But in the value of timer counter 13 error percentage is arranged, the timer counter latch data of the short pulse locking when promptly reading (1) and the error percentage (a-b) of regular pulse * by cpu data.Yet compare with the error percentage of the timer counter latch data of prior art, precision is to have improved greatly.Existing timer counter error time, a situation arises with noise count, 0～+ ∞ between, and the error time of the timer counter of present embodiment 3 only for-T/4～0 (T is the cycle of input pulse 6a～6d).
As shown in Figure 13, owing to be with continuous forward position or trailing edge shielding from the 2nd, breech lock timer enumeration data not is so can obtain correct timer count value, correct detection speed.
Embodiments of the invention 3 as previously mentioned, is characterized in that possessing: the impulse deviser 6 that produces the two-phase pulse of 90 ° of phase differences corresponding to the rotating speed of electrical motor 5; In the output that timer counter 13 is pinned on the forward position and the edge, back of above-mentioned two-phase pulse successively, can use the latch circuit 22-27 of the latch data of every same phase place; And only effective impulse is used as in A, B two first pulse that takes place that alternates, and make pulse processing circuit 20c from the 2nd input pulse void in whole, the only output of pinning above-mentioned timer counter 13 successively on the forward position and the edge, back of actv. two-phase pulse, use the latch data of every same phase place, the speed that also can carry out low regime detects.And it is just 2 the same to detect effect and previous embodiment 1 and enforcement in the speed of high velocity.
The formation of the embodiment of the invention 4 is described below with reference to Figure 14.Figure 14 is that the velocity checking circuits of the embodiment of the invention 4 constitutes block diagram.
Velocity checking circuits shown in Figure 14 is the detection mode that increases low regime on the basis of the detection mode of the elevator high velocity of previous embodiment 1 and embodiment 2, and is provided with counter-rotating and detects sign and be reversed to decline from rising with the direct of travel of expression elevator.This counter-rotating detects sign and is applicable to following situation.For the back mutually edge of A phase forward position, B phase forward position, A, the back mutually edge of B or opposite order, if have noise count to take place in the time point between them on the boundary, then as shown in figure 15, because as broad as long sign during the counter-rotating of actual direction, so this pattern, in comprising that actual direction is reversed in, detect sign with counter-rotating and represent.When counter-rotating takes place, make the value of timer counter invalid, utilize the value detection speed of the last time of timer counter.
As shown in figure 14, present embodiment 4 comprises: in order to the direct of travel counter-rotating testing circuit 30 of the counter-rotating that detects direct of travel; Make the counter-rotating detection signal 30a of direct of travel counter-rotating testing circuit 30 outputs synchronous, to pin the counter-rotating detection latch circuit 31 of this counter-rotating detection signal with the CPU timer counter reading order of RD4L; The output buffer 32 that can read by the CPU reading order of RD6L; And the differential circuit 33 of the differentiated waveform of the forward position waveform when producing the CPU reading order and stop.Other component parts are identical with embodiment 3.The output 33a of differential circuit 33 resets direct of travel counter-rotating testing circuit 30.In other words, counter-rotating detection signal 30a can check out last once RD6L with this time between the RD6L travel direction do not have and reverse.
The related timer counter of fourth aspect present invention comprises pulse processing circuit 20C, OR circuit 21, timer counter 13, latch circuit 22～27 and gate circuit 28 and 29 in embodiments of the invention 4.The related direct of travel counter-rotating testing circuit of fourth aspect comprises that in this embodiment 4 direct of travel counter-rotating testing circuit 30, counter-rotating detect latch circuit 31, output buffer 32 and differential circuit 33.
The service condition of direct of travel counter-rotating testing circuit 30 is described below with reference to Figure 16, Figure 17 and Figure 18.Figure 16 is the sequential chart that moves the action when switching to descends moves in the expression embodiment of the invention 4 from rising.Figure 17 is the sequential chart that contains the action under the noise count situation in the expression embodiment of the invention 4 when the operation that descends switches to the rising operation.Figure 18 is the sequential chart that contains the action under the noise count situation in the expression embodiments of the invention 4 when the operation that descends switches to the rising operation.
Shown in Figure 16 (d), the direct of travel signal 20b of forward-backward counter 11 by direction identification circuit 43 according to be A mutually or B phase pulse decision.Because this travel direction signal 20b is the direction of only distinguishing according to two-phase pulse, so even if be the also indeclinable signal of noise count direction is arranged.On the other hand, shown in Figure 16 (c), generate by pulse processing circuit 20c, by the timer latch-up signal 21a of OR circuit 21 output be noise count the signal that falls of conductively-closed (but for aforementioned A phase forward position, B phase forward position, A mutually the back along, B mutually the back along or the order opposite with it, the pulse of boundary's time point therebetween can not judge it is regular pulse or noise count), therefore shown in Figure 16 (e), with the direct of travel signal 20b pinning of this moment, as the direction detection signal of reality.Shown in Figure 16 (f), detect energizing signal with the change point of this signal as counter-rotating, shown in Figure 16 (g), detect energizing signal according to this counter-rotating and produce counter-rotating detection signal 30a.
This counter-rotating detection signal 30a is lockable when reading timer counter so that it is synchronous with the value of timer counter after reading.This counter-rotating detection signal 30a promptly is eliminated after reading counter-rotating detection sign.At this moment detect sign according to counter-rotating, if detect counter-rotating (CPU reads (1) among Figure 16), just make the value of timer counter invalid, and utilize the value detection speed of timer counter last time.Subsequently, invalid Counter Value is shifted, and the time point (CPU reads (2) among Figure 16) having carried out according to RD5L (26a) reading makes invalid Counter Value effective again again.
Figure 17 and Figure 18 taken place when being the counter-rotating of regular direction to tremble situation of noise detects to go out when reversing with so far method, can detect with the timer error of-T/4, utilizing the detection of reversing to indicate during the direct of travel counter-rotating and adding their confirmation.
The embodiment of the invention 4, as previously mentioned, it is characterized in that having rotating speed corresponding to electrical motor 5 produce 90 ° of phase differences two-phase pulse impulse deviser 6 and in the forward position of above-mentioned two-phase pulse and back along the output of pinning timer counter 13 successively, thereby can use the latch circuit 22～27 of the latch data of every same phase place, according to only A, B two first pulse that takes place that alternates is used as effective impulse and is made second pulse detection direct of travel after the input pulse void in whole that rises, and is provided with the change point of the direct of travel sign as the direct of travel counter-rotating.
Its feature also is when counter-rotating takes place direct of travel, makes the value of forward-backward counter 11 at this moment and timer counter 13 invalid, and utilizes the last value detection speed that reads.
That is to say, high velocity at elevator, when B phase pulse stabilization during at high level or any state of low level, forward position pulse and trailing edge according to the A phase, perhaps when A phase pulse stabilization during at high level or any state of low level, forward position pulse and trailing edge according to the B phase, forward-backward counter 11 is counted, simultaneously only A, the alternate pulse that takes place of B two is used as effective impulse (when the continuous a plurality of pulses input of same phase, only the input pulse void in whole that effectively the 2nd pulse is risen is used as in its first pulse), forward-backward counter 11 is counted.And in the low regime of elevator too, only A, B two pulse that takes place that alternates is used as effectively, the value of pinning timer counter B is with detection speed.
Try to achieve direct of travel from the state of two-phase pulse, and the effective impulse that takes place that alternates gives breech lock according to aforementioned A, B two, is not subjected to noise count to try to achieve correct direct of travel with influencing, be provided with the change point of direct of travel sign as the direct of travel counter-rotating.Read this sign,, just make the value of forward-backward counter 11 at this moment and timer counter 13 invalid, and utilize the last value detection speed that reads if counter-rotating has taken place direct of travel.
Like this, even there is the noise count input also it not to be handled, therefore can prevent the mistake breech lock of forward-backward counter 11 miscounts and timer counter 13, high Precision Detection speed.
Also try to achieve direct of travel from the state of two-phase pulse, and according to aforementioned A, B two effective impulse that takes place that alternates gives breech lock, be not subjected to noise count to try to achieve correct direct of travel with influencing, read with the change point of direct of travel sign as the direct of travel counter-rotating, if counter-rotating has taken place in direct of travel, just make the value of forward-backward counter 11 at this moment and timer counter 13 invalid, and utilize the last value detection speed that reads.Therefore when since actions such as readjustment level when causing actual direction counter-rotating or relating to each mutually noise with regard to the reversible counting value and the timer counter value of unlikely use mistake, can carry out speed control reposefully.
Though the counter-rotating of the direct of travel of the foregoing description 4 detects sign only for the detection that is used for low regime, but not by it, the detection that equally also is applicable to high velocity is (for A phase forward position shown in Figure 15, B phase forward position, A is the edge, back mutually, B is edge, back or order in contrast mutually, and the boundary just can not judge it is regular pulse or noise count in the pulse of the time point between them, therefore is suitable for).In this case, be to make to pin direct of travel signal 20b with the count pulse 20a of forward-backward counter 11, generate direct of travel counter-rotating detection signal 30a. and pin above-mentioned signal 30a by the order RD21 that reads forward-backward counter.
Claims (5)
1. apparatus for checking lift speed comprises:
Corresponding to the rotation of electrical motor produce have 90 degree phase differences first mutually with second impulse deviser of pulse mutually;
Output based on described first mutually with second mutually pulse direct of travel signal, count pulse and with described first mutually and the pulse processing circuit of the second phase rising edge of a pulse and the cooresponding energizing signal of falling edge;
Consider described direct of travel signal, the forward-backward counter that described count pulse is counted;
The timer conter that clock pulse is counted;
Latch the means that latch of described timer conter output successively by described energizing signal; And
Try to achieve elevator speed in the high-speed region according to the value of described forward-backward counter and described timer conter, and try to achieve the CPU of the elevator speed in the low-speed region according to described forward-backward counter and the described value that latchs means,
It is characterized in that,
Described pulse processing circuit when the first phase pulse is in certain level, according to the positive rise pulse and the falling edge pulse of the second phase pulse, generates the described count pulse of output.
2. apparatus for checking lift speed comprises:
Corresponding to the rotation of electrical motor produce have 90 degree phase differences first mutually with second impulse deviser of pulse mutually;
Output based on described first mutually with second mutually pulse direct of travel signal, count pulse and with described first mutually and the pulse processing circuit of the second phase rising edge of a pulse and the cooresponding energizing signal of falling edge;
Consider described direct of travel signal, the forward-backward counter that described count pulse is counted;
The timer conter that clock pulse is counted;
Latch the means that latch of described timer conter output successively by described energizing signal; And
Try to achieve elevator speed in the high-speed region according to the value of described forward-backward counter and described timer conter, and try to achieve the CPU of the elevator speed in the low-speed region according to described forward-backward counter and the described value that latchs means,
It is characterized in that,
Described pulse processing circuit, only with described first mutually and second first pulse of alternately importing in the middle of the pulse mutually be effective impulse, when the first phase effective impulse is in certain level,, generate the described count pulse of output according to the positive rise pulse and the falling edge pulse of the second phase effective impulse.
3. apparatus for checking lift speed as claimed in claim 1 or 2 is characterized in that,
Described energizing signal, be only with described first mutually and second mutually in the middle of the pulse alternately first pulse of input be effective impulse, with the energizing signal of described first phase and the second phase effective impulse positive rise and the corresponding output of falling edge.
4. apparatus for checking lift speed as claimed in claim 3, it is characterized in that, also comprise: detect direct of travel according to described clock pulse, described direct of travel signal and described energizing signal, output one sign shows that the direct of travel counter-rotating in its change point direct of travel counter-rotating detects means
Described CPU is according to described sign, makes that when direct of travel reverses described forward-backward counter and the described value that latchs means are invalid, tries to achieve elevator speed in the low-speed region according to previous value.
5. apparatus for checking lift speed as claimed in claim 4, it is characterized in that, described CPU makes that according to described sign the value of described forward-backward counter and described timer conter is invalid when direct of travel reverses, and tries to achieve elevator speed in the high-speed region according to previous value.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP106526/1993 | 1993-05-07 | ||
| JP5106526A JPH06316385A (en) | 1993-05-07 | 1993-05-07 | Speed detecting device for elevator |
| JP106526/93 | 1993-05-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1101130A CN1101130A (en) | 1995-04-05 |
| CN1057502C true CN1057502C (en) | 2000-10-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN94104791A Expired - Fee Related CN1057502C (en) | 1993-05-07 | 1994-05-07 | Elevator speed detecting device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH06316385A (en) |
| KR (1) | KR970004770B1 (en) |
| CN (1) | CN1057502C (en) |
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| CN105092876B (en) * | 2014-11-20 | 2018-05-18 | 上海富欣智能交通控制有限公司 | The anti-interference pulse counting method of velocity sensor and device |
| CN104501885B (en) * | 2014-12-23 | 2018-12-25 | 中国计量学院 | High-precision low-power consumption natural gas flow measuring method and device based on jet current principle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2054027U (en) * | 1988-02-12 | 1990-03-07 | 中国建筑科学研究院建筑机械化研究所 | Ac control system for speed of elevator |
| CN1067740A (en) * | 1991-05-22 | 1993-01-06 | 三菱电机株式会社 | Apparatus for checking lift speed |
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1993
- 1993-05-07 JP JP5106526A patent/JPH06316385A/en active Pending
-
1994
- 1994-04-25 KR KR1019940008750A patent/KR970004770B1/en not_active IP Right Cessation
- 1994-05-07 CN CN94104791A patent/CN1057502C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2054027U (en) * | 1988-02-12 | 1990-03-07 | 中国建筑科学研究院建筑机械化研究所 | Ac control system for speed of elevator |
| CN1067740A (en) * | 1991-05-22 | 1993-01-06 | 三菱电机株式会社 | Apparatus for checking lift speed |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1101130A (en) | 1995-04-05 |
| KR970004770B1 (en) | 1997-04-03 |
| JPH06316385A (en) | 1994-11-15 |
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