CN105745714A - Removal unit for bodily fluids, in particular blood - Google Patents
Removal unit for bodily fluids, in particular blood Download PDFInfo
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- CN105745714A CN105745714A CN201480063785.5A CN201480063785A CN105745714A CN 105745714 A CN105745714 A CN 105745714A CN 201480063785 A CN201480063785 A CN 201480063785A CN 105745714 A CN105745714 A CN 105745714A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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Abstract
The invention relates to a medical removal unit (1) for blood, comprising a needle carrier (2), at least one cannula (3), which has a distal and a proximal cannula segment (6, 7), and a hose-shaped sleeve (4), which has a closed sleeve end (12) and an open sleeve end (11). The sleeve (4) is fastened to a proximal needle-carrier end (10) by means of the open sleeve end (11) and surrounds the proximal cannula segment (7) in a sealing manner in such a way that an accommodating chamber (13) is formed. An air removal device (14) connects the accommodating chamber (13) to the outer environment in order that air flows out of the accommodating chamber and is formed by at least one outflow channel (15) arranged or formed in the needle carrier (2). A partial segment of the outflow channel (15) comprises a plurality of chambers (27, 28, 29) arranged one after the other and spaced apart from each other in an outflow direction and at least one connection channel (30, 31) that connects chambers (27, 28, 29) arranged immediately adjacent in the outflow direction. The connection channel has a flow cross-section that allows the air to flow through but at least largely prevents or completely stops the bodily fluid, in particular blood, from flowing through.
Description
Technical field
Present application relates generally to storage arrangement.More specifically, the application relates to management and scheduling toleration and the life-span to improve nonvolatile semiconductor flash memory of consistency operation.
Background technology
Nonvolatile memory system such as flash memory has been widely used in consumer products.Flash memory can occur in different forms, for instance using the form of the pocket memory card of delivery between host apparatus or as embedding solid-state disk (SSD) in the host device.
Along with Nonvolatile memery unit narrows down to the less size with the higher capacity of per unit area, due to the unit toleration of programmed and erased circulation, and interference (such as owing to reading or programming) is likely to become more notable.Owing to unit size reduces and the raising of process complexity, the defect level during silicon technology is likely to become higher.Correspondingly, the memorizer meeting height endurability requirement is likely to more difficult, and this is likely to improve further the research and development cost for technology convergent-divergent.
Memorizer is due to main frame write and both experience write/erase cycles of non-host write.Non-host write can include memory maintenance (maintenance) and/or the background operation of background operation/carry out on memory card undertaken by memory card.Owing to the memorizer of this memory maintenance reclaims the life-span that can significantly decrease card.Whenever having standby time and attempting some solution reducing the number of times in the write/erase cycle due to memory maintenance, it is possible to carry out memory maintenance.
Summary of the invention
It is to be expected that the value by some parameter of monitoring and based on those parameters dispatches the toleration of the memory maintenance system enhancement memorizer of the optimization maintained.Such as, temperature can be the exemplary parameter of monitoring.Depend on the environment temperature of card, it is possible to carry out or delay memory maintains.Memory maintenance operations and consistency operation can ranked or classification (such as based on priority in memory maintenance queue) with significantly more efficient scheduling for memory maintenance corresponding to the value of the threshold value of parameter.Such as, at low temperature threshold value place, only carry out high priority and maintain operation, and at higher temperature threshold place, carry out any priority and maintain operation.
Accompanying drawing explanation
Fig. 1 is the block diagram of the main frame being connected with the accumulator system with nonvolatile memory.
The block diagram of the exemplary flash memory Setup Controller that Fig. 2 is used in the system of Fig. 1.
Fig. 3 is the block diagram of interchangeable memory communication system.
Fig. 4 is the exemplary physical memorizer tissue of the system of Fig. 1.
Fig. 5 is the view of the expansion of a part for the physical storage of Fig. 4.
Fig. 6 is the schematic diagram being shown in operation for the charge level in the multilevel cell memory of the data of storage two in a memory cell.
Fig. 7 illustrates the disengaging of the electric charge caught in memory cell tunnel oxidation layer at high-temperature (" HT ") place.
Fig. 8 is an embodiment of the temperature sensor together with main frame.
Fig. 9 is an embodiment of the temperature sensor together with accumulator system.
Figure 10 is the flow chart of the memory maintenance scheduling illustrating simplification.
Figure 11 illustrates example classes and each priority for each classification.
Figure 12 illustrates that exemplary priority determines 1202 factors.
Figure 13 illustrates an embodiment of the scheduling maintaining operation.
Detailed description of the invention
The flash memory system of the aspect being adapted to carry out the present invention illustrates in figs. 1-6.Data are stored to accumulator system 102 and fetch data from flash memory 102 by the host computer system 100 of Fig. 1.Flash memory can be built-in the form that the flash memory in main frame such as drives with the solid-state disk (SSD) being arranged in personal computer.Alternatively, memorizer 102 can be to pass through the form that the accessory 104 and 106 of the adapter of machinery and electricity as shown in Figure 1 is detachably connected to the flash memory card of main frame.Being configured for use as the SSD of inside or the embedding flash memory driven, look can be similar to the schematic diagram of Fig. 1, and one of them is distinctive in that the inside at main frame, the position of accumulator system 102.SSD drives can using the form of the discrete module as the plug-in type replacement driven for spinning disk.As discussed, flash memory can refer to use invalid AND (NAND) unit of storage electron charge.
The example of commercially available detachable flash memory card includes, compact flash (CF), multimedia card (MMC), secure digital (SD), miniSD, memory stick, intelligent medium (SmartMedia), flash memory cards (TransFlash) and miniature SD card.Although each of these cards has machinery and/or the electric interfaces of uniqueness according to its standardized size, but the flash memory system comprised in each can be similar.These cards can obtain from SanDisk Corporation, and SanDisk Corporation is present assignee.SanDisk is additionally provided in the flash driver product line under its Cruzer trade mark, this flash driver is the hand-held accumulator system with little encapsulation, and it has USB (universal serial bus) (USB) plug for being connected with main frame by being inserted into the USB socket of main frame.Each of these memory cards and flash driver includes the controller with HPI and the operation controlling flash memory in them.
The host computer system being likely to use SSD, memory card and flash driver is diversified.They include personal computer (PC), such as desktop or on knee and other portable computer, tablet PC, cell phone, smart phone, personal digital assistant (PDA), digital camera, DV and portable electronic device.Applying for pocket memory card, main frame can include the memory card for one or more types or the flush plug consent of flash driver, or main frame is likely to the adapter that needs memory card to be plugged into.Accumulator system can include Memory Controller and the driver of their own, but also likely to be present the system of the only memorizer that some contrary softwares performed by being connected to its main frame by memorizer control.In some accumulator systems comprising controller, being particularly embedded in those in main frame, memorizer, controller and driver are generally formed on single integrated circuit chip.Main frame can use any communication protocol and memory card communication, and this communication protocol is such as, but not limited to secure digital (SD) agreement, memory stick (MS) agreement and USB (universal serial bus) (USB) agreement.
The host computer system 100 of Fig. 1 can be considered has two critical pieces, when considering storage arrangement 102, is made up of the combination of circuit and software.Application part 108 can be passed through file system module 114 and drive 110 and storage arrangement 102 interface.In PC, for instance, application part 108 can include the processor 112 for running word processing, figure, control or other popular application software.At camera, being directed generally to carry out in the cell phone of the function of single set, application part 108 can be implemented as and takes and store picture, operation of cellular telephone to take the hardware of the software of phone etc. to clap for running operation camera.
The accumulator system 102 of Fig. 1 can include nonvolatile memory such as flash memory 116 and with main frame 100 interface and the system controller 118 controlling memorizer 116, described main frame 100 has been connected to passback delivery data since accumulator system 102.Setup Controller 118 can be changed during data programming and reading between the logical address of data and the physical address of flash memory 116 that main frame 100 uses.Functionally, Setup Controller 118 can include, with the host interface module (HIM) 122 of host system controller logic 110 interface and for host interface module 122 coordinate controller firmware module 124 and flash interface module 128.Flash management logic 126 can be a part for controller firmware 214, and this controller firmware 214 operates for the internal memory management of such as refuse collection.One or more flash interface modules (FIM) 128 can provide the communication interface between controller and flash memory 116.
Flash translation layer (" FTL ") or medium management layer (" MML ") can be integrated in flash management 126 and can process flash error and and HPI.Especially, flash management 126 is the part of controller firmware 124 and MML can be the module in flash management.MML is likely to the interior liabilities to NAND management.Especially, MML can include the algorithm in memory device firmware, and the write from main frame 100 is converted into the write of flash memory 116 by this algorithm.Be likely to need MML because: 1) flash memory is likely to be of limited toleration；2) flash memory 116 is likely to only be written in multiple pages；And/or 3) flash memory 116 is likely to be not written into until it is taken as block erasing.MML understands these the potential restrictions of the flash memory 116 that main frame 100 may not be seen.Correspondingly, MML attempts the write from main frame 100 is converted into the write in flash memory 116.As described below, memory maintenance dispatching algorithm can operate from MML.Flash memory 116 or other memorizer can be multi-level unit (MLC) or single stage unit (SLC) memorizer.It is further described below MLC and SLC memory.SLC or MLC can be involved not as a part for flash memory 116 as a part for Setup Controller 118.As shown in Fig. 8-9, it is possible to there is the temperature sensor of a part for the part as host computer system 100 or accumulator system 102.
Setup Controller 118 can be implemented on single integrated circuit chip such as at the special IC (ASIC) shown in Fig. 2.The processor 206 of Setup Controller 118 can be configured to the multiline procedure processor communicated via the memory interface 204 of the I/O port having for each memorizer bar (bank) in flash memory 116.Setup Controller 118 can include internal clocking 218.Processor 206 communicates with self-correcting code (ECC) module 214, RAM buffer 212, HPI 216 and startup code ROM210 via internal data bus 202.
HPI 216 can provide the data cube computation with main frame.Memory interface 204 can be from one or more FIM128 of Fig. 1.Memory interface 204 allows Setup Controller 118 to communicate with flash memory 116.RAM212 can be static RAM (SRAM).ROM210 can be used to initialize accumulator system 102, such as flash memory device.The accumulator system 102 being initialised can be referred to as card.ROM210 in Fig. 2 can be the region of read only memory, its object is to startup code provides RAM for process program, the initialization of such as accumulator system 102 and startup.ROM can occur in ASIC rather than flash memory dies.
Fig. 3 is the block diagram of interchangeable memory communication system.As discussed with respect to FIG. 1, host computer system 100 communicates with accumulator system 102.Accumulator system 102 includes front end 302 and the rear end 306 coupled with flash memory 116.In one embodiment, front end 302 and rear end 306 can be referred to as Memory Controller and can be the part of Setup Controller 118.Front end 302 can logically include host interface module (HIM) 122 and HIM controller 304.Rear end 306 can logically include flash interface module (FIM) 128 and FIM controller 308.Correspondingly, controller 301 can logically be divided into two modules, HIM controller 304 and FIM controller 308.HIM122 provides the interface function for host apparatus 100, and FIM128 provides the interface function for flash memory 116.Controller 301 can couple with temperature sensor 310.As shown in figures 8-9, temperature sensor 310 can be a part for the part of host computer system 100 or accumulator system 102.Temperature sensor may be located in controller 301 or unit.In any embodiment, the accuracy of temperature sensing can be enhanced when it is the closer to flash memory 116.Temperature sensor 310 and controller 301 communication measurement/temperature of monitoring.FIM controller 308 can include realizing the following algorithm about the study stage described in Fig. 7-10 and implementation phase.
In operation, accumulator system 102 is received data from HIM122 by HIM controller 304 during the write operation of host apparatus 100.The control of the data to reception can be delivered to FIM controller 308 by HIM controller 304, and this can include above-mentioned FTL.FIM controller 308 may determine that how the data of reception to be optimally written on flash memory 116.The data received can be provided FIM128 to write data on flash memory 116 for based on the decision made by FIM controller 308 by FIM controller 308.Especially, depend on the classification of data, its can by differently write (such as to MLC or be retained in renewal block in).
Fig. 4 conceptually illustrates the tissue of the flash memory 116 (Fig. 1) as cell array.Flash memory 116 can include multiple memory cell array, and each of the plurality of memory cell array is individually controlled by single or multiple Memory Controllers 118.Four planes of memory cell or subarray 402,404,406 and 408 can on single integrated memory cell chips, on two chips (two of the plane on each chip) or on four independent chips.Specific arrangements is for inessential discussed below.Certainly, the plane of other quantity such as 1,2,8,16 or more be likely to be present in system.The group of the memory cell that plane is divided into the minimum unit forming erasing independently, hereinafter referred to as block.The module unit of memorizer is illustrated such as block 410,412,414 and 416 by rectangle in the diagram, is arranged in each plane 402,404,406 and 408.Each plane can have any amount of piece.
The block of memory cell is the unit of erasing, and is the memory cell of the minimum number that can physically wipe together.But for the concurrency increased, described piece can with bigger first module unit operation.A block from each plane is logically linked together to form unit's block.Four blocks 410,412,414 and 416 are shown as forming a first block 418.All of unit in unit's block is generally erased together.The block being used to form unit's block needs not be limited to relative position identical in its each plane, as shown in second yuan of block 420 being made up of block 422,424,426 and 428.Whilst it is generally preferred that unit's block extends through all of plane, but for high systematic function, accumulator system can with by any or all capability operation being formed dynamically unit's block in different planes, two or three blocks.This allows the size of unit's block can closely mate the amount of the data of storage in a programming operation that can be used on.
As shown in Figure 5, single block is on the contrary in order to operability purpose is divided into the page of memory cell.The memory cell of each of block 410,412,414 and 416, for instance each is divided into eight pages of P0-P7.Alternatively, can there is the page of 16,32 or more memory cell in each piece.Page is the unit of data programming and reading in block, comprises the data of the minimum number of one-time programming or reading.But, in order to increase the operability concurrency of accumulator system, the such page in two or more pieces can logically be linked as metapage.Metapage 502 figure 4 illustrates, each Physical Page from four blocks 410,412,414 and 416 formed.Metapage 502, it may for example comprise the page P2 in each of four blocks, but the page of metapage is not necessarily required to the identical relative position that has in each piece.Metapage can be the maximum unit of programming.
Memory cell can be operating as the electric charge of two levels of storage so that the data of single position are stored in each cell.This is commonly called binary system or single stage unit (SLC) memorizer.SLC memory can store two states: 0 or 1.Alternatively, memory cell can be operating as in each charge reservoir element or region to store the electric charge of more than two detectable level, thus in each middle storage data more than.This latter configuration is referred to as multi-level unit (MLC) memorizer.Such as, MLC memory can be stored four states and can retain the data of two: 00 or 01 and 10 or 11.Two kinds of memory cell is usable in memorizer, for instance binary system SLC flash memory can be used to data cached and MLC memory can be used to long storage periods.The charge reservoir element of memory cell is most commonly conducting floating gate, but can be alternatively non-conducting dielectric charge-trapping material.As described below, SLC and MLC can have different durability requirements, is accordingly dependent on those durability requirements, and the scheduling maintaining operation reducing loss and minimizing write amplification (" WA ") is likely to more important.
Being operating as in each memory cell in the implementation of the MLC memory of the data of storage two, each memory cell is configured to store the electric charge of four levels of the value corresponding to " 11 ", " 01 ", " 00 " and " 10 ".Each of two of data can represent that the page position of the page of bottom or the page position of the page (upperpage) on top, the page (lowerpage) of its middle and lower part and the page on top stride across a series of memory cells of shared common word line.Generally, the low order of two of data represents that the high significance bit of the page position of the page of bottom and two of data represents the page position of the page on top.
Fig. 6 illustrates an implementation of four charge level of two of the data being used to indicate in a memory cell.Fig. 6 is marked as LM pattern, its can be referred to as middle part pattern place bottom and by about middle part or bottom-bottom at the intermediateness place at middle part further describes.LM intermediateness can also be referred to as the stage of the page programming of bottom.The value of " 11 " is corresponding to the unprogrammed state of memory cell.When programming pulse is applied to memory cell to program the page position of the page of bottom, the level of electric charge is raised the value of " 10 " of the state of the programming of the page position to represent the page corresponding to bottom.The page of bottom may be considered that the logical concept of the position indicated that on multi-level unit (MLC).If MLC is every unit two, logical page (LPAGE) can include all of least significant bit of the unit in the wordline that is grouped together.In other words, the page of bottom is least significant bit.Page position for the page on top, when programming the page position of page of bottom (values of " 10 "), programming pulse is applied to the memory cell of the page position of the page for top, with the desired value depending on the page position of the page on top, the level of electric charge is increased to the value corresponding to " 00 " or " 10 ".But, page position without the page of programming bottom makes memory cell (values of " 11 ") in unprogrammed state, programming pulse is applied to memory cell and raises the level of electric charge to represent the value of " 01 " of the state of the programming of the page position of the page corresponding to top with the page position programming the page on top.
Owing to the main frame in the ordinary life of its application writes and memory maintenance operations, accumulator system experience write/erase operation.Internal storage maintains height write amplification factor (" WAF ") that (that is, non-host write operation or consistency operation) is likely to introduce both MLC and SLC.WAF can be that Flash controller needs the amount of the data wished to write to relative to console controller to write the amount of the data of (owing to data are from a block to any internal reproduction of another block).In other words, WAF is the ratio compared with non-host write operation writes with from main frame.In one example, the MLC write/erase operation reaching half can be due to these internal memory operations.The life-span of card is likely to there is significant impact by this.Correspondingly, the toleration impact reducing the inside write/erase operation due to system is probably important.At higher temperature place, compare relatively low temperature, owing to the high voltage operation flaw in a memory cell of such as programmed and erased produces to be slowed down.Write amplify be likely to be not necessarily relatively low, but the flaw produced is reduced.At high-temperature place, discussed as described above for Fig. 7, it is captured to create the chain reaction producing more traps in flaw that electronics has relatively low probability.Tunnel oxidation layer is it is thus possible to maintain its integrity better at higher temperature place.The error reduced can finally increase the average toleration of the device mentioned in the following Table 1.
Memory maintenance (it is interchangeably referred to as non-host write and/or consistency operation) only can be carried out at Best Times place.Such as, memory maintenance depends on that temperature is possible restricted.One example of memory maintenance includes refuse collection, it is necessary to this refuse collection is to be gathered in the block that is wiped free of discarded data together.Effective data set can be combined and combine discarded data by refuse collection.When block only includes the data discarded, it can be wiped free of so that new data can be written to described piece.The storage that refuse collection is used by minimizing the quantity of the block that part uses and maximizes in block.In other words, refuse collection can be from integration and the gathering with the effective data of the block of the mixing of effective data and discarded data, refuse collection causes more block freely, because there is less block have the mixing of effective and discarded data.
It is at least partially based on WAF and the utilization rate of the estimation for particular card, it is possible to there is some durability requirements for both SLC and MLC.Such as, by comparing the estimation of the utilization rate of the multiple smart phones for 32 GB (GB) SD card on some time period (such as 3 years), it may be determined that exceed the durability requirements of utilization rate pattern of maximum emulation to prevent card failure.Following exemplary table 1 illustrates and operates without the durability requirements on the memorizer of the example simulation in the table 1 of fault for the period of 3 years based on for product.Based on table 1, the SLC durability requirements for 4GB and 8GB capacity compares the significantly higher of 16GB capacity.
| SLC durability requirements | MLC durability requirements | |
| 4GB | 50k | 3k |
| 8GB | 30k | 3k |
| 16GB | 20k | 3k |
| >=32GB | 10k | 3k |
Durability requirements on table 1 memorizer
Durability requirements shown in table 1 is merely illustrative of and can change over.Especially, it is shown that durability requirements be only for explaining that the example of durability requirements and those values can be different for different devices.Along with technical size reduces constantly, toleration is likely to reduction.Based on the utilization rate increased and the toleration of potential reduction, the renewal of dynamically monitoring and consistency operation as described below should be reduce overall losses, reduce fault and improve the method in life-span of memorizer.Finally, the dynamic dispatching based on following parameter (such as temperature) can also reduce power consumption, production cost and Time To Market.
Fig. 7 illustrates the disengaging in memory cell tunnel oxidation layer at the electric charge caught at high-temperature (" HT ") place.Fig. 7 illustrate the disengaging process of the electric charge being in the electrolyte of memory cell at high-temperature (" HT ") can band schematic diagram, this electrolyte such as oxide.As indicated, IPD is IPD, it can include silicon oxide, silicon nitride and silicon oxide three layers.Floating grid (" FG ") is the conductive layer of storage electronics.Polysilicon can be control gate or the wordline of NAND cell, and silicon is the substrate of the whole array building NAND cell thereon.Polysilicon can be the layer formed during manufacturing cell, and silicon is existing wafer, makes NAND chip on this wafer.Due to thermionic emission, the electronics caught in tunnel oxidation layer (" TOX ") is likely to escape and thus compare otherwise for when relatively low temperature (" LT ") place, creating less trap (flaw) in the oxide.
Correspondingly, Fig. 7 illustrates why higher temperature may result in less flaw.At higher temperature place, electronics has more energy to migrate.Programming at higher temperature place reduces the probability of the error during the use of NAND.As described below, the temperature of monitoring can be then used as the triggering determining when to carry out memory maintenance.Such as, low temperature is it could mean that memory maintenance should be limited.Write/erase operation at higher temperature place is likely to introduce lesser amount of electric charge and falls in a memory cell, causes less flaw.Correspondingly, algorithm can based on for based on the threshold value control memory maintenance of the special parameter of temperature with improve memorizer toleration and card the life-span.Target can be in higher temperature place maximum internal memory maintenance.
Fig. 8 is an embodiment of the temperature sensor 806 together with main frame 802.Main frame 802 and accumulator system 804 can be Fig. 1-3 any one shown in main frame or accumulator system, but in fig. 8 in order to succinct and be shown as that not there is extra assembly.Fig. 8 illustrates the temperature sensor 806 of the part as main frame 802.Such as, if main frame is the smart phone holding memory card (such as SD card), smart phone can include the temperature sensor for monitoring temperature.Then main frame 802 can make accumulator system 804 can correspondingly dispatch maintenance with the temperature of accumulator system 804 communication measurement.
Fig. 9 is an embodiment of the temperature sensor 906 together with accumulator system 904.Main frame 902 and accumulator system 904 can be Fig. 1-3 any one shown in main frame or accumulator system, but in fig .9 in order to succinct and be shown as that not there is extra assembly.Fig. 9 illustrates the temperature sensor 906 of the part as accumulator system 904.Especially, temperature sensor can be the intraware of accumulator system.In one embodiment, temperature sensor 906 near memorizer 910 to accurately measure memory temperature.Temperature sensor 906 is the closer to memorizer 910, and this measurement will be more accurate.The temperature of this measurement is communicated to controller 908.Controller 908 can be then depending on temperature scheduling and maintain operation.
It may desirable, in one embodiment AD converter (" ADC ") is for temperature sensor measurement and the temperature information that communicates.Temperature sensor may be connected to instruction control unit, and this instruction control unit can separate with Memory Controller or the part of Memory Controller.
The temperature information measured is then used to follow the tracks of and schedule memory maintenance activity.Algorithm can attempt to maximization memory maintenance activity during higher temperature, but reduces memory maintenance activity during relatively low temperature.
Figure 10 is the schematic diagram illustrating the algorithm for controlling memory maintenance.In block 1002, maintain queue and maintain based on for each priority maintaining operation.As discussed above, maintaining operation can the initial or operation from MML.The example maintaining operation is refuse collection.To be considered as that the extra MML request maintaining operation includes: 1) binary buffer compression, 2) binary buffer regains, 3) MLC compression, 4) control block compression, 5) loss level and/or 6) cluster folds.
Maintain queue can dynamically be resequenced or update.In block 1004, the queue of sequence can be classified as region and operate and can dispatch based on the triggering for regional.Can based on its priority by each maintenance activity classification (that is, range of distribution).General concept is to maintain operation only during standby time and in higher temperature place operation for low priority.Higher priority maintains operation and is likely to need to run regardless of temperature.
Figure 11 illustrates example classes and each priority for each classification.Classification classification can also be referred to as region.Especially, the classification that figure 11 illustrates is for each classification maintaining operation.It is foreground 1102 that limit priority maintains operation, and it is the maintenance operation run in foreground (namely, it is not necessary to wait standby time).These limit priorities maintain operation can be undertaken by controlling main frame.The second area with next limit priority is standby time 1104.These maintain operation and run during standby time.3rd region with lower priority is both standby time and high-temperature 1106.Maintaining of lower priority operates only by during standby time and in higher temperature place operation.In other words, during standby time, do not run lower priority maintain operation, but the higher temperature staying in place's standby time can be waited.This can reduce error by running more maintenance operation at higher temperature place.4th region can be optional and instruction can consider interchangeable parameter.Temperature is only for sequence and maintains an example of the parameter considered operated and can there is extra example.Such as, the appearance of power supply can be another parameter considered.In other words, minimum priority maintains operation and only during the standby time at higher temperature place, and can run when there being power supply to connect.Other exemplary parameter may include that 1) degree of filling that blocks；2) the loss horizontal factor of the block of heat counting it is referred to as；3) frequency of clock；And/or 4) level of VCC power supply.
Categorizing system is designed so that maintaining operation (it can be referred to as event) should carry out during suitable classification.Region 1 event should not go to region 2, and region 2 event should not go to region 3.Especially, for the event in region should in this region can time during complete.But, the migration between region is not rigid restriction and some events is likely to not complete in the region of they distribution.Such as, if within its several days, do not gone in region 1108, then low priority event is likely to become higher priority and be pulled to region 1106 or 1104 or 1102 in time.The history of the amount of the amount being tracked as the maintenance activity that each region produces and the free time found in each area.These two elements may be used to determine whether the border in region.So, we can predict whether particular event can be processed in the region of its distribution and thus become more accurate in definition zone boundary over time.
Referring back to Figure 10, in block 1006, the history of operant activity and available free time can be maintained and be used to the scheduling in future and determine.The history of operant activity can include the factor determined for priority that figure 12 illustrates.Figure 12 illustrates that exemplary priority determines 1202 factors.Asking the time in the of 1204 from first is the timer started when specific request is added in queue.This represents specific and maintains how long operation has been treated in queue.Request counting 1206 is the counting of the quantity for a specific request maintaining operation or event.From the request of MML based on priority processing, MML can send the more multi-request for specific operation based on even at first User Activity before processed.Priority factor 1208 can be based on history and controls the value of priority.Different refuse collection events can have different priority rate of changes.Such as, some events can be low priority one month and some events can be only low priority a few minutes.The event with rate of change faster is more prone to make system become more urgent and thus control main frame to carry out refuse collection in foreground.In order to keep the tracking of the event to these types, it is possible to there is the priority factor variable for each type of event.When each event is forced to execution in foreground, its priority can increase by one.This help system correspondingly balances all events.The time required for 1210 that completes is probably the further factor considered for priority.
Priority determines that 1202 can make based on any one or more of the factor shown in Figure 12.In one embodiment, priority can be calculated by below equation:
Priority=(time from the first request) * (request counting) * (priority factor).
This formula can be previously used for each maintenance operation adding it to maintenance queue.Queue is dynamically updated based on the priority value for the operation in queue.Priority based on the distribution for the operation in queue can be assigned to the region/classification shown in Figure 11 further, and it determines when to dispatch those operations.Scheduling figure 13 illustrates further.
Figure 13 illustrates an embodiment of the scheduling maintaining operation.In block 1302, storage arrangement (that is, blocks) in normal condition and temperature sensor is to activate.In block 1304, make decision that is whether idle about card or that process Host Command energetically.If card is not idle, then as can be only performed region 1 maintenance operation in block 1306.In other words, when memorizer is not idle, only performs limit priority and maintain operation.When such as card is for leaving unused in block 1304, block 1310 is made the decision about temperature.In one embodiment, it is possible to there is the threshold temperature value determined.As discussed further below, it is possible to there is multiple threshold value, the plurality of threshold value has the multiple priority values based on those threshold values；But, Figure 13 illustrates the embodiment for single temperature threshold.When temperature is lower than threshold temperature value, then as performed to maintain operation in block 1312 in the 1-2 of region.Owing to temperature is low, do not perform lower priority and maintain operation (those in the 3+ of region).When temperature is higher than threshold value in block 1310, block 1314 is made the decision whether occurred about power supply.The appearance of power supply is can be used to scheduling to maintain the other exemplary parameter of operation.When occurring without power supply, then from the event of region 1-3 as performed in block 1316.Block 1316 illustrates standby time and high-temperature.In alternative embodiments, only exist three regions and the parameter uniquely analyzed is temperature.When there is power supply in block 1314, then all of event can perform in block 1318.Block 1318 is standby time, has high-temperature, and has power supply.
In alternative embodiments, temperature survey can be used to priority measurement.As discussed above, temperature is classified as high or low (such as, in the binary condition of threshold value above and below).However, it is possible to there is multiple threshold value.For example, it may be possible to there is low, to neutralize high temperature condition (two threshold temperatures) decision.Then the maintenance operation carried out can be classified as the extra region considering different temperature values.For example, it is possible to existence is other classification or the region of idle and middle temperature in fig. 11.Classification attempts to carry out great majority at higher temperature place and maintains operation and maintain operation in relatively low temperature place restriction.Can only run higher priority during relatively low temperature and maintain operation.In alternative embodiments, it is possible to exist and maintain operation for classifying and determine that those operate the value of any amount of temperature threshold that can when be scheduled.Example in Figure 11-13 is used for single temperature threshold, but it is merely illustrative of.
" computer-computer-readable recording medium ", " machine readable media ", " propagation-signal " medium and/or " signal-bearing medium " can include any device, and this device includes, store, communicate, propagate or transport software is for being used by the executable system of instruction, equipment or device or being connected with the executable system of instruction, equipment or device.Machine-readable media can optionally, but be not limited to, electronics, magnetic, optics, electromagnetism, infrared or semiconductor system, unit or propagation medium.The non-exhaustive list of the example of machine-readable media will include: have the electrical connection " electronics " of one or more wire, Portable magnetic or CD, volatile memory such as random access memory " RAM ", read only memory " ROM ", Erasable Programmable Read Only Memory EPROM (EPROM or flash memory) or optical fiber.Machine-readable media is additionally may included on it to print the tangible medium of software, and software can be stored as image or other form (such as, pass through optical scanning) electronically, then compiling and/or translation or other process.The medium processed can be then stored in computer and/or machine memory.
In alternative embodiments, special hardware implementation mode such as special IC, programmable logic array and other hardware unit can be configured to realize the one or more of method described here.Equipment and the systematic difference that can include various embodiment can include multiple electronics and computer system widely.One or more embodiments described here can use the hardware module of two or more specific interconnection or have can between the modules or the device of the relevant control communicated by module or data signal realize function or the part as special integrated circuit.Correspondingly, native system comprises software, firmware and hardware implementation mode.
The explanation of embodiment described here is intended to provide being commonly understood by of the structure to various embodiments.Illustrate to be not intended as the complete description of all elements for the equipment and system using structure described here or method.After browsing the disclosure, many other embodiments can be apparent to those skilled in the art.Other embodiments can use the disclosure or obtain from the disclosure so that can make without departing from the scope of the present disclosure structure and logic replacement and change.Additionally, illustrating is only representational and possible not drawn on scale.Some ratio in this explanation is likely to be exaggerated, and other ratio is likely to reduced.Correspondingly, the disclosure and accompanying drawing are considered to be exemplary rather than restrictive.
Claims (19)
1. a flash memory device, including:
Non-volatile storage, has the array of the memory block of store data；
Temperature sensor, contiguous described non-volatile storage；And
Controller, with described non-volatile storage and described temperature sensor communication, described controller is configured to:
Temperature value is received from described temperature sensor；
Producing the memory maintenance queue for the memory maintenance operations that will carry out with described non-volatile storage, wherein said operation is organized in based on priority in described queue；And
Low priority operation is carried out when described temperature value is more than temperature threshold and during standby time.
2. device as claimed in claim 1, wherein carries out high priority operation regardless of described temperature value.
3. device as claimed in claim 2, wherein for the priority of each of described operation based on from described operation by the time receiving, complete at least one of time, the number of times submitting described operation to or priority factor that described operation needs.
4. device as claimed in claim 3, wherein said priority includes being multiplied of the number of times submitted to described operation by the described time receiving from described operation and priority factor.
5. device as claimed in claim 3, wherein said priority factor is based on the historical data maintaining operation.
6. device as claimed in claim 5, wherein said historical data includes the relative quantity of maintenance activity.
7. the method maintaining operation for schedule memory in flash memory device, including:
In there is the non-volatile storage device of block of controller and memorizer, described controller:
Receive temperature value；
The memory maintenance queue of the generation operation for carrying out on the block of described memorizer, wherein, described operation is organized in based on priority in described queue；And
Lower priority operation is carried out when described temperature value is more than temperature threshold and during standby time.
8. method as claimed in claim 7, wherein said temperature value is the environment temperature of described flash memory device.
9. method as claimed in claim 7, wherein said temperature sensor is positioned at main frame place.
10. method as claimed in claim 7, wherein said temperature sensor is arranged in described non-volatile storage device and communicates with described controller.
11. method as claimed in claim 7, wherein carry out high priority operation regardless of described temperature value.
12. method as claimed in claim 11, wherein for the priority of each of described operation based on from described operation by the time receiving, complete at least one of time, the number of times submitting described operation to or priority factor that described operation needs.
13. method as claimed in claim 12, wherein said priority includes being multiplied of the number of times submitted to by the described time receiving and described operation from described operation and priority factor.
14. method as claimed in claim 12, wherein said priority factor is based on the historical data maintaining operation.
15. a flash memory device, including:
Non-volatile storage, has the array of the memory block of store data；
Temperature sensor, contiguous described non-volatile storage；And
Controller, with described non-volatile storage and described temperature sensor communication, described controller is configured to:
Monitor the standby time of described flash memory device；
Monitor the temperature of the flash memory device from described temperature sensor；And
Lower priority memory maintenance operations is performed during described standby time and when the temperature of monitoring is more than temperature threshold.
16. flash memory device as claimed in claim 15, the monitoring of wherein said temperature includes receiving temperature from temperature sensor.
17. flash memory device as claimed in claim 16, wherein said flash memory device also includes described temperature sensor, and described temperature sensor and described controller couple and be configured to monitor described temperature and by described temperature communications to described controller.
18. flash memory device as claimed in claim 15, wherein said controller is also configured to
Perform higher priority regardless of described temperature and maintain operation.
19. flash memory device as claimed in claim 15, wherein said controller is also configured to
Receive the instruction whether power supply occurs；And
During described standby time and when the temperature of monitoring is more than temperature threshold and when occurring when power supply, perform minimum priority and maintain operation.
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| US14/086,355 | 2013-11-21 | ||
| US14/086,355 US9535614B2 (en) | 2013-11-21 | 2013-11-21 | Temperature based flash memory system maintenance |
| PCT/US2014/060469 WO2015076950A1 (en) | 2013-11-21 | 2014-10-14 | Temperature based flash memory system maintenance |
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| US (1) | US9535614B2 (en) |
| KR (1) | KR101923284B1 (en) |
| CN (1) | CN105745714B (en) |
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| WO (1) | WO2015076950A1 (en) |
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| DE112014005346T5 (en) | 2016-07-28 |
| CN105745714B (en) | 2019-02-01 |
| KR20160113580A (en) | 2016-09-30 |
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| KR101923284B1 (en) | 2018-11-28 |
| US20150143026A1 (en) | 2015-05-21 |
| WO2015076950A1 (en) | 2015-05-28 |
| US9535614B2 (en) | 2017-01-03 |
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