CN105718357A - Memory monitoring method - Google Patents
Memory monitoring method Download PDFInfo
- Publication number
- CN105718357A CN105718357A CN201610041986.6A CN201610041986A CN105718357A CN 105718357 A CN105718357 A CN 105718357A CN 201610041986 A CN201610041986 A CN 201610041986A CN 105718357 A CN105718357 A CN 105718357A
- Authority
- CN
- China
- Prior art keywords
- address
- page
- instruction
- trap
- monitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3034—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a storage system, e.g. DASD based or network based
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a memory monitoring method, which comprises the following steps: 1, recording information about an address to be monitored and information about a page where the address to be monitored is located, and setting an attribute of the page where the address to be monitored is located to be read-only; 2, if a page missing abnormity is triggered by a CPU, an attribute of a page where an address causing the page missing abnormity is located to be readable and writable, and if the address causing the page missing abnormity is found to be the address to be monitored in a processing process, acquiring and recording related information of a calling stack, and inserting a trap instruction; 3, executing the trap instruction by the CPU to trigger trap abnormity processing to recover the attribute of the page where the address to be monitored to be read-only, and clearing the trap instruction. According to the method, whether a certain segment of memory is modified or not is monitored, a monitored address range is larger, a process is simple, and practical operability is high.
Description
Technical field
The present invention relates to calculator memory technical field, in particular to a kind of method of internal memory monitoring.
Background technology
In computer application field, will monitoring whether certain section of internal memory is written over, the internal memory monitoring software being generally adopted specialty realizes.But after its detection is destroyed, it is necessary to could find mistake when internal memory release or Resources allocation, cause can not reporting mistake in time, not there is real-time, so meeting strong influence program remove mistake progress.Therefore, the problem being presently required solution is how to monitor whether internal memory is written in real time, and does not destroy currently running system.
In current internal memory monitoring technology, the mode of Hardware Breakpoint and software breakpoint is generally adopted to realize the monitor in real time of internal memory.Hardware Breakpoint processing speed is fast, but can monitor address scope little, and whether support that data breakpoint is relevant with processor.
Software breakpoint can increase breakpoint quantity and get final product monitor address scope, and what generally adopt is that page protection mechanism realizes.But the page protection mechanism adopted at present, it is common that by being joined by scattered monitor address in certain physics debugging page, triggers page fault during reading and writing data in debugging page, and process is more complicated, therefore adopts this method actual operation not strong.
Summary of the invention
For the defect existed in prior art, a kind of method that it is an object of the invention to provide internal memory monitoring, monitor whether certain section of internal memory is written over, can monitor address scope relatively big, process is simple, and actual operation is strong.
For reaching object above, the present invention takes a kind of method of internal memory monitoring, including step: S1. records address information to be monitored and monitor address place page information, is set to read-only by the attribute of monitor address place page；If S2. CPU triggers page fault, being set to read-write by place, the address page attribute causing page fault, if finding in processing procedure, the address causing page fault is monitor address, then obtain and record call stack relevant information, and inserting trap instruction；S3.CPU goes to trap instruction, triggers trap abnormality processing, reverts to read-only by the attribute of monitor address place page, and removes trap instruction.
On the basis of technique scheme, in step S1, arranging a monitor address information table, monitor address information table is for depositing all monitor address information within the scope of monitor address.
On the basis of technique scheme, in step S1, arranging a page address information table, page address information table is used for depositing all monitor address places page information.
On the basis of technique scheme, in step S2, when the page address of read only attribute is carried out write operation by the program of address to be monitored, then CPU triggers page fault.
On the basis of technique scheme, it is present instruction that the page address of read only attribute is carried out the instruction of write operation by the program of address to be monitored, inserting the concrete action of trap instruction is, by next instruction of present instruction according to the trap instruction that the CPU platform modifying of application is correspondence.
On the basis of technique scheme, if it is not monitor address that CPU detects the address causing page fault in processing procedure, directly by next instruction of present instruction according to the trap instruction that the CPU platform modifying of application is correspondence.
On the basis of technique scheme, described in when being revised as the trap instruction of correspondence, the instruction address of logging trap instruction and the command information being modified.
On the basis of technique scheme, in step S3, remove trap instruction, i.e. by the trap relevant information recorded, trap instruction is reduced to the instruction being modified.
The beneficial effects of the present invention is: record address information to be monitored and monitor address place page information so that except monitor address, the access of other internal storage datas will not trigger exception, without influence on system；When read-only memory page is read and write, then triggering page fault and process, what energy was real-time records call stack information when internal memory is rewritten, and is effectively improved the real-time of certain section of internal memory monitoring.The suitability of the present invention is wide, it is adaptable to most of embedded systems.
Accompanying drawing explanation
Fig. 1 is the flow chart of the method for embodiment of the present invention internal memory monitoring；
Fig. 2 is the detail flowchart of step S2 in Fig. 1.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention is described in further detail.
As it is shown in figure 1, the method for internal memory monitoring of the present invention, specifically include following steps:
S1., one monitor address information table and a page address information table are set, record address (i.e. monitor address) information to be monitored and monitor address place page information respectively, wherein, within the scope of monitor address, monitor address information table is used for depositing all of monitor address information, and page address information table is used for depositing all monitor address places page information.Further, the attribute of monitor address place page is set to read-only.
If S2. CPU triggers page fault, being set to read-write by place, the address page attribute causing page fault, if finding in processing procedure, the address causing page fault is monitor address, then obtain and record call stack relevant information, and inserting trap instruction.
As in figure 2 it is shown, concrete step is as follows:
S201., when the page address of read only attribute is carried out write operation by the program of address to be monitored, CPU triggers page fault.
S202. place, the address page attribute causing page fault is set to read-write.
S203. check whether the address causing page fault is address to be detected, i.e. in monitor address information table, whether find the address causing page fault of correspondence, if so, enter S204；If it is not, enter S205.
S204. analyze actual registers information, obtain call stack information record, enter S205.
S205. by next instruction of present instruction, it is corresponding trap instruction according to the CPU platform modifying of application.Wherein, present instruction is: the page address of read only attribute is carried out the instruction of write operation by the program of address to be monitored.Furthermore, it is desirable to the instruction address of logging trap instruction and the command information that is modified.
S3., when CPU goes to trap instruction, trigger trap abnormality processing, the attribute of monitor address place page is reverted to read-only.And remove trap instruction, i.e. by the trap relevant information recorded, trap instruction is reduced to the instruction being modified.
Above-mentioned steps S1 to S3 is the process inserting breakpoint, when breakpoint deleted by needs, is deleted by monitor address from monitor address information table, and is set to read-write by attribute corresponding in the page address information of place page.
The present invention is not limited to above-mentioned embodiment, for those skilled in the art, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, and these improvements and modifications are also considered as within protection scope of the present invention.The content not being described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (8)
1. the method for an internal memory monitoring, it is characterised in that include step:
S1. record address information to be monitored and monitor address place page information, the attribute of monitor address place page is set to read-only；
If S2. CPU triggers page fault, being set to read-write by place, the address page attribute causing page fault, if finding in processing procedure, the address causing page fault is monitor address, then obtain and record call stack relevant information, and inserting trap instruction；
S3.CPU goes to trap instruction, triggers trap abnormality processing, reverts to read-only by the attribute of monitor address place page, and removes trap instruction.
2. the method for internal memory monitoring as claimed in claim 1, it is characterised in that: in step S1, arranging a monitor address information table, monitor address information table is for depositing all monitor address information within the scope of monitor address.
3. the method for internal memory monitoring as claimed in claim 1, it is characterised in that: in step S1, arranging a page address information table, page address information table is used for depositing all monitor address places page information.
4. the method for internal memory monitoring as claimed in claim 1, it is characterised in that: in step S2, when the page address of read only attribute is carried out write operation by the program of address to be monitored, then CPU triggers page fault.
5. the method for internal memory monitoring as claimed in claim 4, it is characterized in that: it is present instruction that the page address of read only attribute is carried out the instruction of write operation by the program of address to be monitored, inserting the concrete action of trap instruction is, by next instruction of present instruction according to the trap instruction that the CPU platform modifying of application is correspondence.
6. the method for internal memory monitoring as claimed in claim 5, it is characterized in that: if it is not monitor address that CPU detects the address causing page fault in processing procedure, directly by next instruction of present instruction according to the trap instruction that the CPU platform modifying of application is correspondence.
7. the method for the internal memory monitoring as described in claim 5 or 6, it is characterised in that: described in when being revised as the trap instruction of correspondence, the instruction address of logging trap instruction and the command information being modified.
8. the method for internal memory monitoring as claimed in claim 1, it is characterised in that: in step S3, remove trap instruction, i.e. by the trap relevant information recorded, trap instruction is reduced to the instruction being modified.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610041986.6A CN105718357B (en) | 2016-01-22 | 2016-01-22 | A kind of method of internal memory monitoring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610041986.6A CN105718357B (en) | 2016-01-22 | 2016-01-22 | A kind of method of internal memory monitoring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105718357A true CN105718357A (en) | 2016-06-29 |
| CN105718357B CN105718357B (en) | 2018-12-28 |
Family
ID=56154932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610041986.6A Active CN105718357B (en) | 2016-01-22 | 2016-01-22 | A kind of method of internal memory monitoring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105718357B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255746A (en) * | 2017-12-29 | 2018-07-06 | 北京元心科技有限公司 | Memory rewrites detection method and device |
| CN111400096A (en) * | 2020-03-16 | 2020-07-10 | 杭州涂鸦信息技术有限公司 | Memory mirroring method based on linux page missing mechanism and system and device thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1924826A (en) * | 2005-09-02 | 2007-03-07 | 中兴通讯股份有限公司 | Detecting method for illegal memory reading and writing |
| CN101561775A (en) * | 2009-05-12 | 2009-10-21 | 华为技术有限公司 | Method and device for monitoring memory |
| CN102388368A (en) * | 2011-09-20 | 2012-03-21 | 华为技术有限公司 | Method and device for monitoring memory |
| US8688917B2 (en) * | 2008-12-30 | 2014-04-01 | Intel Corporation | Read and write monitoring attributes in transactional memory (TM) systems |
| CN105159838A (en) * | 2015-08-27 | 2015-12-16 | 华为技术有限公司 | Memory access method and computer system |
-
2016
- 2016-01-22 CN CN201610041986.6A patent/CN105718357B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1924826A (en) * | 2005-09-02 | 2007-03-07 | 中兴通讯股份有限公司 | Detecting method for illegal memory reading and writing |
| US8688917B2 (en) * | 2008-12-30 | 2014-04-01 | Intel Corporation | Read and write monitoring attributes in transactional memory (TM) systems |
| CN101561775A (en) * | 2009-05-12 | 2009-10-21 | 华为技术有限公司 | Method and device for monitoring memory |
| CN102388368A (en) * | 2011-09-20 | 2012-03-21 | 华为技术有限公司 | Method and device for monitoring memory |
| CN105159838A (en) * | 2015-08-27 | 2015-12-16 | 华为技术有限公司 | Memory access method and computer system |
Non-Patent Citations (3)
| Title |
|---|
| 何川，陈莉君: ""Linux内核中的内存访问监控框架的设计与实现"", 《微电子学与计算机》 * |
| 朱世鸿等: "《80*86微机原理和接口技术》", 30 November 2014, 合肥：中国科学技术大学出版社 * |
| 麦库斯克: "《4.4BSD操作系统设计与实现》", 31 January 2012, 北京：机械工业出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255746A (en) * | 2017-12-29 | 2018-07-06 | 北京元心科技有限公司 | Memory rewrites detection method and device |
| CN111400096A (en) * | 2020-03-16 | 2020-07-10 | 杭州涂鸦信息技术有限公司 | Memory mirroring method based on linux page missing mechanism and system and device thereof |
| CN111400096B (en) * | 2020-03-16 | 2023-05-02 | 杭州涂鸦信息技术有限公司 | Memory mirroring method based on linux page-missing mechanism and system and device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105718357B (en) | 2018-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10268695B2 (en) | Snapshot creation | |
| US8448013B2 (en) | Failure-specific data collection and recovery for enterprise storage controllers | |
| US9690642B2 (en) | Salvaging event trace information in power loss interruption scenarios | |
| CN111756575A (en) | Performance analysis method and device of storage server and electronic equipment | |
| US20080222215A1 (en) | Method for Deleting Virus Program and Method to Get Back the Data Destroyed by the Virus | |
| CN104636435A (en) | Cloud terminal screen recording method | |
| CN112017723B (en) | Power failure test method and device for memory, readable storage medium and electronic equipment | |
| US20120246518A1 (en) | Operating a computer system | |
| US20070079292A1 (en) | Management of watchpoints in debuggers | |
| CN101251822A (en) | Supervising method of internal memory being rewrited | |
| CN113268427B (en) | Crash analysis method and system for binary program | |
| US20120260138A1 (en) | Error logging in a storage device | |
| US20130110785A1 (en) | System and method for backing up test data | |
| CN105700999A (en) | method and system for recording processor operation | |
| CN103927126B (en) | The collocation method of a kind of Disk Array and assembling and disk insertion process method | |
| CN105718330A (en) | Linux system backup data recovery method and device | |
| CN113987507A (en) | Heap memory vulnerability detection method and device, storage medium and electronic equipment | |
| US20150160994A1 (en) | Investigation program, information processing apparatus, and information processing method | |
| CN109117297A (en) | Fault positioning method and device for solid state disk | |
| CN105718357A (en) | Memory monitoring method | |
| CN109542341B (en) | Read-write IO monitoring method, device, terminal and computer readable storage medium | |
| CN104978241B (en) | A kind of data reconstruction method and device of COW type file systems | |
| CA2950688A1 (en) | System and method for recording the beginning and ending of job level activity in a mainframe computing environment | |
| US8370815B2 (en) | Electronic device and method for debugging programs | |
| US20110202903A1 (en) | Apparatus and method for debugging a shared library |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180323 Address after: 430074 Wuhan, Hongshan Province District Road, Department of mail, No. 88 hospital Applicant after: Fenghuo Communication Science &. Technology Co., Ltd. Applicant after: WUHAN FIBERHOME TECHNICAL SERVICES CO., LTD. Address before: 430074 East Lake Development Zone, Hubei, Optics Valley Venture Street, No. 67, No. Applicant before: Fenghuo Communication Science &. Technology Co., Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |