CN105717752A - Manufacturing methods for high-aspect-ratio dielectric nanostructure and semiconductor material - Google Patents
Manufacturing methods for high-aspect-ratio dielectric nanostructure and semiconductor material Download PDFInfo
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- CN105717752A CN105717752A CN201410734929.7A CN201410734929A CN105717752A CN 105717752 A CN105717752 A CN 105717752A CN 201410734929 A CN201410734929 A CN 201410734929A CN 105717752 A CN105717752 A CN 105717752A
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Abstract
The invention discloses manufacturing methods for a high-aspect-ratio dielectric nanostructure and a semiconductor heterogeneous material. According to the manufacturing for the nanostructure, a nanoscale resolution pattern is formed on a dielectric film surface on a substrate through miniature projection type exposure; then the pattern is transferred to the dielectric film to form the high-aspect-ratio medium nanostructure, wherein the aspect ratio of the dielectric nanostructure is greater than 1. Compared with other patterning technologies, the pattern formed by the method takes a photoetching pattern as the unit, and large-area unit repetition is realized through programming step control; therefore, the pattern is high in consistency and rapid in patterning speed, the large-area pattern can be obtained, and the pattern is flexibly controlled; compatibility with the semiconductor process production mode is achieved; and therefore, the substrate patterning technology can promote the industrial production of hetero-epitaxy based on an aspect ratio dislocation capturing technology.
Description
Technical field
The application belongs to technical field of manufacturing semiconductors, particularly relates to the manufacture method of a kind of high-aspect-ratio medium nanostructured and semi-conducting material.
Background technology
Utilize depth-to-width ratio dislocation capture technique to obtain high-quality hetero epitaxial materials to become III-V semiconductor growing and be subject to the attention of vast material scholar in a kind of extremely promising method of Si substrate.In this kind of heteroepitaxial growth technology, except Material growth technology itself, another obtain high-quality epitaxial layer it is crucial that high-aspect-ratio compact medium pattern must be obtained on required substrate.At present, in order to obtain high-aspect-ratio medium nanostructured pattern, the preparation method reported includes: (1) electron beam exposure；(2) interference lithography；(3) nano impression；(4) ball photoetching is received in Al anodic oxidation (5)；Said method (1) is consuming time, expensive, is not suitable for large area mass and uses, manufactures not compatible with large-area chips；Method (2) is although can large area prepare, but is subject to optical interference impact, and it is more single that it can form first-rate quality pattern, and in order to realize different pattern on the same substrate, it is necessary to multiexposure, multiple exposure so that technique is loaded down with trivial details, the yield rate of first-rate quality pattern is relatively low.(4) and (5) be self-assembly process, it is possible to forming two dimension rule shape pattern at a low price, but pattern is single, and it is homogeneous to be difficult to obtain large area, poor controllability.Itself be not suitable for the high occasion of mass reliability requirement to use.And nanometer embossing, although the requirements such as controlled, the mass of rule can be met, but existing nano-imprinting apparatus seems seldom to be equipped with crystal orientation alignment function, is unfavorable for crystal orientation being required, high crystal growth uses.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of high-aspect-ratio medium nanostructured and semi-conducting material, to overcome deficiency of the prior art.
For achieving the above object, the present invention provides following technical scheme:
The embodiment of the present application discloses the manufacture method of a kind of high-aspect-ratio medium nanostructured, micro projection exposure is adopted to form nanometer resolution pattern on the deielectric-coating surface being positioned on substrate, then this pattern is transferred on deielectric-coating, forming the medium nanostructured with high-aspect-ratio, the depth-to-width ratio of described medium nanostructured is more than 1.
Preferably, in the manufacture method of above-mentioned high-aspect-ratio medium nanostructured, the degree of depth of described medium nanostructured is less than 2 μm, and the width of described medium nanostructured is less than 1000nm.
Preferably, in the manufacture method of above-mentioned high-aspect-ratio medium nanostructured, described medium nanostructured is one-dimensional grating structure or two-dimensional mesh grating texture.Can also be other photoengraving patterns.
Preferably, in the manufacture method of above-mentioned high-aspect-ratio medium nanostructured, the material of described substrate is Si or GaAs, it is also possible to for other cheap crystalline substrate.
Preferably, in the manufacture method of above-mentioned high-aspect-ratio medium nanostructured, the material of described deielectric-coating is SiO2、SiN、Al2O3Or TiO2。
The embodiment of the present application also discloses the manufacture method of a kind of semi-conducting material, including adopting the method described in claim 1 to make the medium nanostructured with high-aspect-ratio on substrate, grows the epitaxial layer of lattice mismatch in described medium nanostructured.
Preferably, in the manufacture method of above-mentioned semi-conducting material, the material of described epitaxial layer adopts the material that the device of III-V material or other lattice mismatches needs.
Preferably, in the manufacture method of above-mentioned semi-conducting material, with reticle pattern for unit, repeat over the substrate to make to obtain large-area medium nanostructured.
Compared with prior art, it is an advantage of the current invention that: the present invention proposes to adopt projection exposure technology, it is achieved substrate high-aspect ratio pattern.First mask pattern is amplified according to a certain percentage (such as 5 times or 10 times) and prepares the reticle used by projection lithography, then at deposited on substrates deielectric-coating, utilize corresponding micro projection exposure photoetching process, nanometer resolution pattern is formed on deielectric-coating surface, and further this pattern is transferred on deielectric-coating, it is thus achieved that the patterned substrate of needs.Compared to other patterning techniques above-mentioned, it is with reticle pattern for unit that the method forms pattern, the repetition of large area unit is realized by programming step motion control, therefore, pattern concordance is good, one-tenth figure speed fast, can realize large area and pattern is controlled flexibly, mutually compatible with semiconductor technology production model, therefore, this underlay pattern technology contributes to pushing the hetero-epitaxy based on depth-to-width ratio dislocation capture technique to industrialized production.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the application, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The Making programme schematic diagram that Fig. 1 a-1f show in the specific embodiment of the invention high-aspect-ratio nanostructured.
Detailed description of the invention
The embodiment of the present application discloses the manufacture method of a kind of high-aspect-ratio medium nanostructured, and it is at deposited on substrates deielectric-coating, adopts reduced projection formula exposure technology to form pattern on this deielectric-coating, utilizes its shrink technology, it is achieved substrate nano-scale patterns.This kind of patterning techniques mass, pattern are controlled, compatible with quasiconductor integrated artistic, are suitable for the hetero-epitaxy based on depth-to-width ratio dislocation capture technique is generalized to production and application.
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.The example of these preferred implementations has illustrated in the accompanying drawings.Shown in accompanying drawing and the embodiments of the present invention that describe with reference to the accompanying drawings merely exemplary, and the present invention is not limited to these embodiments.
At this, in addition it is also necessary to explanation, in order to avoid having obscured the present invention because of unnecessary details, illustrate only in the accompanying drawings and according to the closely-related structure of the solution of the present invention and/or process step, and eliminate other details little with relation of the present invention.
The manufacture method of high-aspect-ratio medium nanostructured includes:
(1), shown in ginseng Fig. 1 a, it is provided that a substrate, the material of this substrate is preferably Si；
(2), mask pattern is amplified according to a certain percentage (such as 5 times or 10 times) and prepares the reticle used by projection lithography；
(3), joining shown in Fig. 1 b, at deposited on substrates deielectric-coating, the material of deielectric-coating is preferably SiO2；
(4), join shown in Fig. 1 c, utilize corresponding micro projection exposure photoetching process, form nanometer resolution pattern on deielectric-coating surface；
(5), join shown in Fig. 1 d, with the deielectric-coating on mask etching hetero-epitaxy substrate prepared by miniature projection exposure；
(6), shown in ginseng Fig. 1 e, remove mask plate, acquisition has high-aspect ratio pattern hetero-epitaxy substrate, wherein obtained dielectric structure is one-dimensional grating structure, it is the strip groove structure of period profile, the depth-to-width ratio of each groove is more than 1, and the degree of depth of each groove is less than 2 μm, and the width of each groove is less than 1000nm.
(7) shown in ginseng Fig. 1 f, the big mismatched material of extension in above-mentioned large area medium nanostructured, it is derived from high-quality dissimilar materials.
It is with reticle pattern for unit that the method forms pattern, the repetition of large area unit is realized by programming step motion control, therefore, pattern concordance is good, one-tenth figure speed fast, can realize large area and pattern is controlled flexibly, mutually compatible with semiconductor technology production model, therefore, this underlay pattern technology contributes to pushing the hetero-epitaxy based on depth-to-width ratio dislocation capture technique to industrialized production.
Finally, it can further be stated that, term " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, so that include the process of a series of key element, method, article or equipment not only include those key elements, but also include other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.
Claims (8)
1. the manufacture method of a high-aspect-ratio medium nanostructured, it is characterized in that: adopt micro projection exposure to form nanometer resolution pattern on the deielectric-coating surface being positioned on substrate, then this pattern is transferred on deielectric-coating, forming the medium nanostructured with high-aspect-ratio, the depth-to-width ratio of described medium nanostructured is more than 1.
2. the manufacture method of high-aspect-ratio medium nanostructured according to claim 1, it is characterised in that: the degree of depth of described medium nanostructured is less than 2 μm, and the width of described medium nanostructured is less than 1000nm.
3. the manufacture method of high-aspect-ratio medium nanostructured according to claim 1, it is characterised in that: described medium nanostructured is one-dimensional grating structure or two-dimensional mesh grating texture.
4. the manufacture method of high-aspect-ratio medium nanostructured according to claim 1, it is characterised in that: the material of described substrate is Si or GaAs.
5. the manufacture method of high-aspect-ratio medium nanostructured according to claim 1, it is characterised in that: the material of described deielectric-coating is SiN, SiO2、Al2O3Or TiO2。
6. the manufacture method of a semi-conducting material, it is characterised in that include adopting the method described in claim 1 to make the medium nanostructured with high-aspect-ratio on substrate, grown epitaxial layer in described medium nanostructured.
7. the manufacture method of semi-conducting material according to claim 6, it is characterised in that: the material of described epitaxial layer adopts the III-V material with base material lattice mismatch.
8. the manufacture method of semi-conducting material according to claim 6, it is characterized in that: with reticle pattern for unit, over the substrate repeat make to obtain large-area medium nanostructured, and in this large area medium nanostructured extension lattice mismatching material.
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| CN201410734929.7A CN105717752A (en) | 2014-12-05 | 2014-12-05 | Manufacturing methods for high-aspect-ratio dielectric nanostructure and semiconductor material |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112960641A (en) * | 2020-10-12 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer member, method of manufacturing the same, and transfer head having the same |
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| CN101640175A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor structure |
| CN101996873A (en) * | 2009-08-21 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Oxide layer and method for manufacturing grid electrode of flash memory containing same |
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Patent Citations (2)
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| CN101640175A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor structure |
| CN101996873A (en) * | 2009-08-21 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Oxide layer and method for manufacturing grid electrode of flash memory containing same |
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| 李玉斌等: "具有深高宽比的SiO2/GaAs纳米图形衬底的制作工艺", 《中国科技论文在线》 * |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112960641A (en) * | 2020-10-12 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer member, method of manufacturing the same, and transfer head having the same |
| CN112960641B (en) * | 2020-10-12 | 2024-01-23 | 重庆康佳光电科技有限公司 | Transfer member, preparation method thereof and transfer head with transfer member |
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Application publication date: 20160629 |