CN105702581B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105702581B CN105702581B CN201410707060.7A CN201410707060A CN105702581B CN 105702581 B CN105702581 B CN 105702581B CN 201410707060 A CN201410707060 A CN 201410707060A CN 105702581 B CN105702581 B CN 105702581B
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Abstract
A kind of forming method of semiconductor structure, comprising: form gate stack structure on a semiconductor substrate；Stressor layers are formed on the semiconductor substrate covers the gate stack structure；Ozone plasma processing is carried out to the stress layer surface, to form thin oxide layer in the stress layer surface；After ozone plasma processing, interlayer dielectric layer is formed in the stressor layers.The method can eliminate the excessively high puzzlement of failure rate when wafer carries out fault detection.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of semiconductor structure.
Background technique
When manufacturing semiconductor devices, stressor layers can be used to cause stress in transistor channel, to adjust in channel
Carrier mobility.CMOS complementary metal-oxide-semiconductor (Complementary Metal-Oxide-Semiconductor,
CMOS) structure includes NMOS structure and PMOS structure, for CMOS structure, needs to deposit in NMOS structure to have to open and answer
The stressor layers of power (tensile stress), deposition the answering with compression (compressive stress) in PMOS structure
Power layer, stressor layers generally use silicon nitride production.
With the reduction of semiconductor structure geometric dimension, high-aspect-ratio technique (High Aspect Ratio Process,
HARP it is used to form interlayer dielectric layer) to improve the gap of interlayer dielectric layer (inter-layer dielectric, ILD)
Fill (gap-fill) performance.For high density plasma CVD method (HDP-CVD), high-aspect-ratio work
Skill has better clearance filling capability, and the film layer formed does not have plasma damage.
However, after forming interlayer dielectric layer in above-mentioned stressor layers using high-aspect-ratio technique, either in the production line
Or under line, when wafer carries out fault detection (trouble shooting), the excessively high puzzlement of failure rate, this puzzlement
It shows to be particularly acute when carrying out particle problems detection.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, to be formed in stressor layers
After interlayer dielectric layer, when carrying out the fault detection of wafer, failure rate excessively high puzzlement when eliminating fault detection.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising:
Gate stack structure is formed on a semiconductor substrate；
Stressor layers are formed on the semiconductor substrate covers the gate stack structure；
Ozone plasma processing is carried out to the stress layer surface, to form thin oxide layer in the stress layer surface；
After ozone plasma processing, interlayer dielectric layer is formed in the stressor layers.
Optionally, in ozone plasma processing, the ozone range of flow that uses for 17000sccm~
18000sccm。
Optionally, in the ozone plasma processing, the processing time range used is 35s~45s.
Optionally, in the ozone plasma processing, the temperature range used is 370 DEG C~430 DEG C.
Optionally, in the ozone plasma processing, the pressure range used is 4Tott~10Tott.
Optionally, the material of the stressor layers is silicon nitride.
Optionally, the thickness range of the thin oxide layer is
Optionally, the interlayer dielectric layer is formed using high-aspect-ratio technique.
Optionally, the interlayer dielectric layer is formed using ethyl orthosilicate.
Optionally, the stressor layers have tensile stress or compression stress.
Compared with prior art, technical solution of the present invention has the advantage that
In technical solution of the present invention, gate stack structure is formed on a semiconductor substrate, and in the semiconductor substrate
Upper formation stressor layers cover the gate stack structure, later, ozone plasma processing are carried out to the stressor layers, in institute
It states stress layer surface and forms thin oxide layer, then form inter-level dielectric in the stressor layers with the thin oxide layer again
Layer.Due to the presence of the thin oxide layer, the interlayer dielectric layer, which is equivalent to, to be formed directly into above the thin oxide layer, and layer
Between synthesis speed of the dielectric layer in the thin oxide layer it is very fast, form the liquid material of interlayer dielectric layer in vaporescence,
It also has not enough time to form bubble in film surface, just continues to cover, therefore the bubble that film surface is formed is few, it is finally formed
Interlayer dielectric layer surface roughness reduce, and interlayer dielectric layer surface roughness reduction can prevent it is subsequent wafer carry out failure
When detection, there is a situation where erroneous detections, to eliminate the excessively high puzzlement of failure rate when fault detection.
Further, the thickness range of the thin oxide layer isOn the one hand the thickness control of the thin oxide layer
?More than, to guarantee that subsequent interlayer dielectric layer is all formed directly into thin oxide layer, to guarantee interlayer dielectric layer
Synthesis speed is improved to necessary requirement.On the other hand, the thickness control of the thin oxide layer existsHereinafter, to be formed with preventing
Thin oxide layer impacts the stress inside stressor layers.In addition, the thickness increase of thin oxide layer can inevitably extend work
The skill time, process efficiency is caused to decline.
Detailed description of the invention
Fig. 1 to Fig. 3 is each step counter structure signal of forming method of semiconductor structure provided by the embodiment of the present invention
Figure.
Specific embodiment
As described in background, existing method is formed using high-aspect-ratio technique positioned at upper stressor layers inter-level dielectric
After layer, when carrying out fault detection, the excessively high puzzlement of failure rate, this puzzlement is showed when carrying out particle problems detection
It is particularly acute.
Reason is analyzed, the interlayer dielectric layer structure originally formed using high-aspect-ratio technique is softer, and surface roughness
It is larger, the case where causing when such as particle problems detect, by rough surface erroneous detection be particulate matter, when causing fault detection therefore
The excessively high puzzlement of barrier rate.
The further larger reason of analysis interlayer dielectric layer surface roughness, it is found that the forming material of interlayer dielectric layer is usual
For ethyl orthosilicate, high-aspect-ratio technique is directly when forming interlayer dielectric layer in stressor layers, since stressor layers are usually to nitrogenize
Silicon materials, deposition synthesis speed of the interlayer dielectric layer generated by ethyl orthosilicate in stressor layers is slow, at this time the positive silicon of liquid
Acetoacetic ester is incomplete in film surface vaporization, and film surface is caused to generate more bubble, therefore the inter-level dielectric layer surface formed
Roughness is big.
For this purpose, the present invention provides a kind of forming method of new semiconductor structure, the method after forming stressor layers,
Ozone plasma processing first is carried out to stressor layers, to form thin oxide layer in the stress layer surface, then again with institute
It states and forms interlayer dielectric layer in the stressor layers of thin oxide layer.Due to the presence of the thin oxide layer, the interlayer dielectric layer
It is equivalent to and is formed directly into above the thin oxide layer, and synthesis speed of the interlayer dielectric layer in the thin oxide layer is very fast,
Therefore the bubble that film surface is formed is few, so that interlayer dielectric layer surface roughness is improved, failure rate mistake when eliminating fault detection
High puzzlement.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of semiconductor structure, incorporated by reference to referring to figs. 1 to Fig. 3.
Referring to FIG. 1, forming gate stack structure on a semiconductor substrate 100.The gate stack structure includes that grid are situated between
Matter layer 120 and grid 130.
In the present embodiment, semiconductor substrate 100 is silicon substrate.In other embodiments of the invention, the semiconductor lining
Bottom 100 or germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or its laminated construction substrate, or insulation
Silicon substrate on body can also be that well known to a person skilled in the art other semiconductor substrates.
In the present embodiment, semiconductor substrate 100 includes n-type dopant, and the region of doping is formed on a semiconductor substrate 100
N well structure 110, N well structure 110 can be phosphorus (phosphorus) or arsenic to make PMOS transistor structure, n-type dopant
(arsenic)。
In other embodiments of the invention, semiconductor substrate 100 also may include p-type dopant or there are two types of containing simultaneously
Dopant, wherein p-type dopant can be boron (boron) or BF2, to constitute p-type well structure or Dual Well Structure.
In the present embodiment, it is formed with isolation area 101, on a semiconductor substrate 100 to completely cut off the various of semiconductor substrate 100
Region.For example, isolation area 101 can be used to completely cut off NMOS and PMOS transistor region.Isolation area 101 can use region silicon oxygen
Change (local oxidation of silicon, LOCOS) or shallow trench isolation (shallow trench isolation,
STI).The material in isolation area 101 may include silica, silicon nitride, silicon oxynitride or other suitable materials or previous materials
Combination.
In the present embodiment, gate dielectric layer 120 is formed directly into semiconductor substrate 100.The material of gate dielectric layer 120 can be with
For silica.Gate dielectric layer 120 can be formed using chemical vapour deposition technique.
In the present embodiment, the material of grid 130 can be polysilicon.The forming process of grid 130 and gate dielectric layer 120 can
Think, directly forms silicon oxide layer, the deposit polycrystalline silicon layer on silicon oxide layer, to the polysilicon on a semiconductor substrate 100
Layer and silicon oxide layer perform etching, until forming grid 130 and gate dielectric layer 120.
In the present embodiment, side wall 140 can also be formed in grid 130 and 120 two sides of gate dielectric layer, as shown in Figure 1.Specifically
The forming process of side wall 140 can be with are as follows: by chemical vapor deposition method 100 surface of semiconductor substrate, 130 surface of grid and
120 surface deposition of gate dielectric layer, one layer of spacer material layer (not shown), then etching removal be located at 100 surface of semiconductor substrate and
The spacer material layer of 130 upper surface of grid, the spacer material layer that residue is located at 120 side of grid 130 and gate dielectric layer are left
Side wall 140.
It further include that source region (is not marked in the semiconductor substrate 100 of the gate stack structure down either side in the present embodiment
Note) and drain region (not marking).Specifically, the source region and the forming process in drain region can be with are as follows: with the gate stack structure and
Side wall is blocking mask, carries out active area injection technology to semiconductor substrate 100.Since PMOS structure uses hole to carry as majority
Stream, so the source electrode and drain electrode of PMOS transistor structure is p-type, the ion of injection is boron or indium etc..
In other embodiments of the invention, when forming NMOS transistor structure, using electronics as majority carrier,
Corresponding source electrode and drain electrode is N-type, and the ion of injection is phosphorus or arsenic.
Although not shown in the drawing can also include other doped regions, such as the source/drain region being lightly doped in semiconductor substrate 100
(LDD), and implementable annealing process is to activate LDD region, and annealing process may include flash annealing (RTA) or laser annealing work
Skill.
Although not shown in the drawing but the present embodiment further includes implementing silicide process (silicide process).Specifically,
Can be in any metals such as the source region, drain region and 130 surface of grid deposition nickel (Ni), titanium (Ti) or cobalts (Co), and make this
A little metals can form silicide layer with pasc reaction.
With continued reference to FIG. 1, forming stressor layers 150 on a semiconductor substrate 100 covers the gate stack structure.
In the present embodiment, the material of stressor layers 150 can be silicon nitride.Stressor layers 150 can use chemical vapor deposition
Method is formed.The thickness of stressor layers 150 can be
In the present embodiment, stressor layers 150 have the stressor layers 150 of tensile stress (tensile stress), stressor layers 150
One of effect be widen the porosity of PMOS transistor, thus improve carry electric current flowing velocity, raising transistor
Performance.
In other embodiments of the invention, when forming NMOS transistor structure, it can equally be formed to have to stretch and answered
The stressor layers of power, one of effect is equally the porosity for widening NMOS, to improve the flowing velocity for carrying electric current, is improved
Transistor performance.
It should be noted that stressor layers 150 play the role of etching stop layer, i.e. stressor layers 150 simultaneously in the present embodiment
It is used as etching stop layer simultaneously.The effect of etching stop layer are as follows: after forming interlayer dielectric layer, be situated between using etching technics in interlayer
During forming groove or through-hole in matter layer, corresponding etching technics can timely and accurately stop at etching stop layer
Surface so that the depth of groove or through-hole be made to be consistent, and guarantees that corresponding etching process does not cause brokenly other structures
It is bad.
Referring to FIG. 2, carrying out ozone plasma (O to 150 surface of stressor layers3Plasma it) handles, described
150 surface of stressor layers forms thin oxide layer 151.
The present embodiment is further aoxidized to the stressor layers 150 of silicon nitride material, it is therefore desirable to higher oxygen ability
Plasma-treating technology.Therefore, common oxygen gas plasma processing, effect is still undesirable, is finally subsequently formed
Interlayer dielectric layer surface roughness is still unable to reach necessary requirement.And ozone plasma oxidability with higher, it can
The stressor layers 150 of silicon nitride material are further aoxidized, to form the thin oxide layer 151 of silica ingredient.And it is subsequent
Interlayer dielectric layer can be deposited rapidly in thin oxide layer 151, to prevent from being formed by interlayer dielectric layer surface roughness
It is higher.
In the present embodiment, the ozone flow that ozone plasma processing uses may range from 17000sccm~
18000sccm.When ozone flow is maintained at 17000sccm~18000sccm, it can guarantee entire plasma treatment procedure
In, enough ozone plasmas are generated so that stressor layers 150 are carried out with stable oxidation, and reaction pressure is also at one
A stable range.If the flow of ozone is less than 17000sccm, the ozone plasma of generation is in shortage, may cause shape
At thin oxide layer 151 it is second-rate, influence the formation of subsequent interlayer dielectric layer.And if the flow of ozone is greater than
18000sccm, it will cause unnecessary wastes, and it is unstable to may cause reaction pressure.
In the present embodiment, the pressure range that the ozone plasma processing uses can be 4Tott~10Tott.According to
It is noted earlier it is found that ozone plasma processing need carried out under stable reaction pressure, when pressure range control and stablize
In 4Tott~10Tott, corresponding oxidation processes can stablize progress, and reaction rate is suitable.If pressure is less than
4Tott, corresponding oxidation reaction are too slow.And if pressure is greater than 10Tott, it is unstable to may cause reaction.
In the present embodiment, the temperature range that the ozone plasma processing uses is 370 DEG C~430 DEG C.The ozone
Corona treatment is needing to guarantee temperature higher than 370 DEG C, to guarantee that ozone can constantly generate corresponding ozone-plasma
Body.Meanwhile it needing to control temperature at 430 DEG C hereinafter, causing the structure that front process has made to prevent temperature excessively high
Adverse effect.
In the present embodiment, the processing time range that the ozone plasma processing uses can be 35s~45s.It is described
Ozone plasma processing, which must assure that, forms the thin oxide layer 151 of adequate thickness on 150 surface of stressor layers, after can improving
The synthesis speed of continuous interlayer dielectric layer.It controls when the processing time that ozone plasma processing uses in 35s~45s,
151 thickness of thin oxide layer of formation is met the requirements.If handling the time is less than 35s, 151 thickness of thin oxide layer of formation is too small,
Cause entire technique to fail, is unable to reach corresponding effect.If handling the time is greater than 45s, the process time can be extended, cause to give birth to
Produce efficiency decline.
By the setting of above-mentioned process conditions, the present embodiment can form thickness range on 150 surface of stressor layers and beThin oxide layer 151.In this thickness range, subsequent interlayer dielectric layer can be formed with faster synthesis speed
In stressor layers 150.That is, on the one hand the thickness control of the thin oxide layer 151 existsMore than, to guarantee that subsequent interlayer is situated between
Matter layer is all formed directly into thin oxide layer 151, to guarantee that the synthesis speed of interlayer dielectric layer is improved to necessary requirement.Separately
On the one hand, the thickness control of the thin oxide layer 151 existsHereinafter, to prevent formed thin oxide layer 151 to stressor layers
Stress inside 150 impacts.In addition, the thickness increase of thin oxide layer 151 can inevitably extend the process time, cause
Process efficiency decline.Furthermore it is possible to by measurement thin oxide layer 151 thickness (Left and right) come judge ozone etc. from
Whether daughter processing reacts completion.
Referring to FIG. 3, forming interlayer dielectric layer in the stressor layers 150 after ozone plasma processing
160。
In the present embodiment, interlayer dielectric layer 160 is formed using high-aspect-ratio technique.High-aspect-ratio technique guarantor with higher
Shape deposits (conformal deposition) characteristic, and can also prevent plasma attack during forming film layer
Substrate.
In the present embodiment, interlayer dielectric layer 160 is formed using ethyl orthosilicate.Ethyl orthosilicate is liquid at normal temperature,
It needs to gasify by introduction valve, the major parameter for influencing liquid gasification is introduction valve temperature and carrier gas (helium or helium and nitrogen
The mixed gas of gas) flow and flow rate.It is using ozone and the positive silicon of liquid that i.e. high-aspect-ratio technique, which forms interlayer dielectric layer 160,
The sub-atmospheric pressure chemical vapor deposition method of acetoacetic ester, and formed in conjunction with annealing process.Wherein, pass through control ozone and positive silicic acid second
The ratio of ester and the condition of annealing process can obtain the interlayer dielectric layer 160 of no silicon loss.Specifically, reaction gas with
After carrier gas enters reaction chamber, heat is issued in high temperature (about 430 DEG C) and is decomposed, then decompose the oxygen radical generated certain with ozone
It is reacted under pressure, generates interlayer dielectric layer 160.
The roughness on 160 surface of interlayer dielectric layer is that ethyl orthosilicate vaporizes incomplete state in fact.When raising interlayer
Synthesis speed (the synthesis speed that is, deposition rate) raising of dielectric layer 160 can be improved ethyl orthosilicate and form interlayer in deposition
The vapor state of dielectric layer 160, so that 160 surface roughness of finally formed interlayer dielectric layer can improve.
In fact, the material of interlayer dielectric layer is silica, when wanting the synthesis speed on silicon face to be with interlayer dielectric layer
When reference rate, if being handled without above-mentioned ozone plasma and directly forming interlayer dielectric layer in stressor layers, layer
Between the synthesis speed of dielectric layer be only the 63.6% of reference rate, it is seen then that the synthesis speed of interlayer dielectric layer is slower at this time, positive silicon
The film surface that acetoacetic ester is easy to be formed in front in vaporescence forms bubble, leads to finally formed interlayer dielectric layer table
Surface roughness is higher.
And the present embodiment uses and forms interlayer dielectric layer 160 in stressor layers 150 again after ozone plasma processing, it is smelly
Oxygen plasma treatment can form the thin oxide layer 151 of one layer of oxidation silicon material on 150 surface of stressor layers, be equivalent to interlayer Jie
Matter layer 160 is formed directly into thin oxide layer 151.And synthesis speed of the interlayer dielectric layer 160 in thin oxide layer 151 is substantially
Equal to reference rate (i.e. synthesis speed of the interlayer dielectric layer in thin oxide layer 151 is essentially the 100% of reference rate), it is seen that
After ozone plasma processing, synthesis speed of the interlayer dielectric layer 160 in stressor layers 150 is greatly improved, therefore, can be effective
Ground prevents ethyl orthosilicate from forming bubble in film surface, so that 160 surface roughness of finally formed interlayer dielectric layer
It reduces.
In the forming method of semiconductor structure provided by the present embodiment, ozone plasma first is carried out to stressor layers 150
Processing, to form thin oxide layer 151 on 150 surface of stressor layers, the then shape in the stressor layers 150 with thin oxide layer 151 again
At interlayer dielectric layer 160.Due to the presence of thin oxide layer 151, interlayer dielectric layer 160, which is equivalent to, is formed directly into thin oxide layer
151 tops, and synthesis speed of the interlayer dielectric layer 160 in thin oxide layer 151 is very fast, forms the liquid of interlayer dielectric layer 160
Material also has not enough time to form bubble in film surface, just continues to cover in vaporescence, therefore film surface formation
Bubble is few, and finally formed 160 surface roughness of interlayer dielectric layer reduces, and 160 surface roughness of interlayer dielectric layer reduces energy
Enough preventing consequent malfunction, there is a situation where erroneous detections when detecting, to eliminate the excessively high puzzlement of failure rate when fault detection.
The experimental results showed that when directly forming inter-level dielectric in stressor layers without the processing of above-mentioned ozone plasma
When layer, the surface roughness variance of interlayer dielectric layer is 3.5nm or more.At this time either in the production line or in production line
Under, when carrying out fault detection, there is the excessively high detection puzzlement of failure rate.
And after using the processing of above-mentioned ozone plasma, then when forming interlayer dielectric layer 160 in stressor layers 150, layer
Between the surface roughness variance of dielectric layer 160 be reduced to 3.1nm or less.At this time either in the production line or in production line
Under, when carrying out fault detection, the excessively high detection puzzlement of failure rate is eliminated.
Although not shown in the drawing but the present embodiment is subsequent that contact hole can also be formed in interlayer dielectric layer 160, and contacting
Metal plug is formed in hole, details are not described herein.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of forming method of semiconductor structure characterized by comprising
Gate stack structure is formed on a semiconductor substrate；
Stressor layers are formed on the semiconductor substrate covers the gate stack structure；
Ozone plasma processing is carried out to the stress layer surface, it is described to form thin oxide layer in the stress layer surface
The thickness range of thin oxide layer is
After ozone plasma processing, interlayer dielectric layer is formed in the stressor layers；
The interlayer dielectric layer is formed using high-aspect-ratio technique, the interlayer dielectric layer is formed using ethyl orthosilicate.
2. forming method as described in claim 1, which is characterized in that in the ozone plasma processing, the ozone of use
Range of flow is 17000sccm~18000sccm.
3. forming method as described in claim 1, which is characterized in that in the ozone plasma processing, the processing of use
Time range is 35s~45s.
4. forming method as described in claim 1, which is characterized in that in the ozone plasma processing, the temperature of use
Range is 370 DEG C~430 DEG C.
5. forming method as described in claim 1, which is characterized in that in the ozone plasma processing, the pressure of use
Range is 4Tott~10Tott.
6. forming method as described in claim 1, which is characterized in that the material of the stressor layers is silicon nitride.
7. forming method as described in claim 1, which is characterized in that there is the stressor layers tensile stress or compression to answer
Power.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080081480A1 (en) * | 2006-09-29 | 2008-04-03 | Kai Frohberg | Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device |
| US20080280391A1 (en) * | 2007-05-10 | 2008-11-13 | Samsung Electronics Co., Ltd. | Methods of manufacturing mos transistors with strained channel regions |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080081480A1 (en) * | 2006-09-29 | 2008-04-03 | Kai Frohberg | Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device |
| US20080280391A1 (en) * | 2007-05-10 | 2008-11-13 | Samsung Electronics Co., Ltd. | Methods of manufacturing mos transistors with strained channel regions |
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