CN105701291B

CN105701291B - Finite element fraction analysis apparatus and information acquisition method, sytem matrix parallel generation method

Info

Publication number: CN105701291B
Application number: CN201610020547.7A
Authority: CN
Inventors: 王希; 蔡显新; 刘建新
Original assignee: China Aircraft Power Machinery Institute
Current assignee: Hunan Aviation Powerplant Research Institute AECC
Priority date: 2016-01-13
Filing date: 2016-01-13
Publication date: 2019-04-23
Anticipated expiration: 2036-01-13
Also published as: CN105701291A

Abstract

This disclosure relates to a kind of finite element fraction analysis apparatus and information acquisition method, sytem matrix parallel generation method.Method includes: S11. using the 1st node in finite element grid as currently processed node；S12. the unit number that currently processed node connection is arranged is 0；S13. the 1st using in finite element grid unit is as current processing unit；S14. judge in current processing unit with the presence or absence of currently processed node；And if so, go to step S15, if there is no then going to step S14；S15. the element number that currently processed node connects is added 1；S16. judge whether current processing unit is the last one unit, if it is goes to step S17；If otherwise using the next unit of current processing unit as current processing unit, and going to step S14；S17. the element number of currently processed node connection is obtained；S18. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12.

Description

Finite element fraction analysis apparatus and information acquisition method, sytem matrix parallel generation method

Technical field

This disclosure relates to finite element analysis technology field, in particular to a kind of finite element fraction analysis apparatus interior joint phase It closes information acquisition method, be related to sytem matrix parallel generation method and a kind of finite element analysis in a kind of finite element fraction analysis apparatus Device.

Background technique

Finite element fraction analysis apparatus is that (FEA, Finite Element Analysis) utilizes the method for mathematical approach to true Physical system (geometry and load working condition) is simulated, also using simple and interaction element, i.e. unit, by limited The unknown quantity of quantity goes to approach the real system of unlimited unknown quantity.

An important step is that element stiffness matrix is assembled into system global matrix (often to claim global stiffness square in finite element analysis Battle array or gross mass matrix etc.), in traditional technology, the mode for mostly using unit to recycle calculates separately each unit square in order Battle array, is then assembled into system global matrix.

There are a large amount of neutral elements in the system global matrix that computer is generated by conventional method, thus are referred to as " dilute Dredge matrix ".The memory space that this matrix occupies is very big, and the very long calculating time need to be expended by handling this matrix；Moreover, with External memory exchange is difficult, handles large-scale finite element analysis problem and has difficulties；Further, it is difficult to realize parallel computation.

It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.

Summary of the invention

For subproblem in the prior art or whole issue, the disclosure provides to be saved in a kind of finite element fraction analysis apparatus Point relevant information acquisition methods are related to sytem matrix parallel generation method and a kind of finite element in a kind of finite element fraction analysis apparatus Analytical equipment.

According to the first aspect of the embodiments of the present disclosure, a kind of finite element fraction analysis apparatus interior joint correlation unit information is provided to obtain Take method, comprising:

S11. using the 1st node in finite element grid as currently processed node；

S12. the unit number that the currently processed node connection is arranged is 0；

S13. using the 1st unit in finite element grid as current processing unit；

S14. judge in the node of the current processing unit with the presence or absence of the currently processed node；If it is present Step S15 is gone to, if it does not exist, then going to step S14；

S15. the element number currently processed node connected increases by 1；

S16. judge whether current processing unit is the last one unit, if it is, going to step S17；If it is not, then Using the next unit of current processing unit as current processing unit, and go to step S14；

S17. the element number of currently processed node connection is obtained；

S18. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with current The next node of node is handled as currently processed node, and goes to step S12.

In a kind of exemplary embodiment of the disclosure, wherein in the step S18, judging that currently processed node is When the last one node, step S21 is gone to；The acquisition methods further include:

S21. using the 1st node in finite element grid as currently processed node；

S22. using the 1st unit in finite element grid as current processing unit；

S23. judge in the node of the current processing unit with the presence or absence of the currently processed node；If it is present Step S24 is gone to, if it does not exist, then going to step S25；

S24. the current processing unit is then denoted as the unit connecting with the currently processed node；

S25. judge whether current processing unit is the last one unit, if it is, going to step S26；If it is not, then Using the next unit of current processing unit as current processing unit, and go to step S23；

S26. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with current The next node of node is handled as currently processed node, and goes to step S22.

S21. using the 1st node in finite element grid as currently processed node, and n is set equal to 0；

S22. using the 1st unit in finite element grid as current processing unit；

S24. then by the unit connecting with the currently processed node that is denoted as of the current processing unit, and n increases by 1；

S25. judge whether n is less than the element number of the currently processed node connection: if it is less, going to step S26, if it is not, then going to step S27；

S26. judge whether current processing unit is the last one unit, if it is, going to step S27；If it is not, then Using the next unit of current processing unit as current processing unit, and go to step S23；

S27. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with current The next node of node is handled as currently processed node, and goes to step S22.

According to the second aspect of an embodiment of the present disclosure, sytem matrix parallel generation side in a kind of finite element fraction analysis apparatus is provided Method, comprising:

S31. obtain the node total number nNode in computer core number and finite element grid, and using the 1st core as Currently processed core；

S32., the initial row and termination row of currently processed core sytem matrix to be processed are set；

S33. thread is created in currently processed core, executes step S34 to step S38；

S34. using in finite element grid node corresponding with the initial row as currently processed node；

S35. the element number and unit number of the unit of currently processed node connection are obtained, and with currently processed node company The 1st unit in the unit connect is current processing unit；

S36. using the current processing unit computing system matrix sub block and it is assembled into the currently processed node In corresponding sytem matrix row；

S37. judge whether current processing unit is the last one unit in the unit of currently processed node connection, if It is then to go to step S38；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S36；

S38. judge whether the currently processed node is the corresponding node of the termination row, if it is, going to step S39；If it is not, then using the next node of currently processed node as currently processed node, and go to step S35；

S39. using next core of currently processed core as currently processed core, and step S32 is gone to, until last A core processing finishes.

According to the third aspect of an embodiment of the present disclosure, a kind of finite element fraction analysis apparatus is provided characterized by comprising

Processor；And

Memory, for storing the executable instruction of the processor；

Wherein the processor is configured to execute following operation via the executable instruction is executed:

S11. using the 1st node in finite element grid as currently processed node；

S13. using the 1st unit in finite element grid as current processing unit；

S15. the element number currently processed node connected increases by 1；

S17. the element number of currently processed node connection is obtained；

Technical solution in the exemplary embodiment of the disclosure can have it is following the utility model has the advantages that

1) " sytem matrix parallel generation method " can shorten the system matrix computation time.

2) " node correlation unit information acquisition method " can be used for piecemeal and assemble and store external memory, saves memory, is conducive to Handle extensive problem.

3) " node correlation unit information acquisition method " can be used for without generating the line iteration of total system matrix, can be Ultra-large problem is handled in common computer.

4) " node correlation unit information acquisition method " can be used for generating " dense " matrix, compared to " sparse " of conventional method Matrix amount of storage reduces by 1 to 2 orders of magnitude, while calculating speed improves even tens times of several times, ten several times.

It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not The disclosure can be limited.

Detailed description of the invention

The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure Some embodiments for those of ordinary skill in the art without creative efforts, can also basis These attached drawings obtain other attached drawings.

Fig. 1 schematically shows a kind of finite element matrix.

Fig. 2 schematically shows a kind of finite element grid.

Fig. 3 schematically shows a kind of finite element fraction analysis apparatus interior joint correlation unit information in disclosure exemplary embodiment The flow diagram of acquisition methods.

Fig. 4 schematically shows a kind of finite element fraction analysis apparatus interior joint correlation unit information in disclosure exemplary embodiment The structural block diagram of acquisition device.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and So that all aspects of this disclosure thicken.

In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure Note indicates same or similar part, thus will omit repetition thereof.Some block diagrams shown in the drawings are function Energy entity, not necessarily must be corresponding with physically or logically independent entity.These function can be realized using software form Energy entity, or these functional entitys are realized in one or more hardware modules or integrated circuit, or at heterogeneous networks and/or place These functional entitys are realized in reason device device and/or microcontroller device.

Technical solution in this example embodiment can quickly calculate what each node in finite element grid was attached thereto Unit sum and all element numbers for being attached thereto unit.These information being calculated can be used for fast parallel generation " dense " system global matrix may be simultaneously used for solving using the line iteration for not forming system global matrix ultra-large Finite element analysis problem.In this example embodiment, " dense " the system global matrix eliminates all neutral elements, advises matrix Mould greatly reduces, and so as to effectively improve computer calculating speed, realizes block storage system global matrix and then solves especially big The finite element analysis problem of scale.

Finite element matrix is arranged with the sequence of node number.As shown in Figure 1, assuming for ease of understanding The freedom degree of each node is 1 (when being greater than 1, matrix element can be regarded as submatrix), at this time node number and sytem matrix line number Equal, line number is identical with node number meaning, under do not repeat.

Iterative solution sytem matrix is since the first row, and iteration to the last a line, completes an iteration line by line.And such as Edge generating system matrix side is iterated there is no need to store total system matrix fruit line by line, thus can be asked on a common computer Solve ultra-large problem.

In direct solution, a kind of parallel generation sytem matrix method is to give each thread distribution of substantially equal line number of number Sytem matrix, and independently carry out parallel computation by these threads.Such as there are two core, sytem matrixes 100 for certain computer Sytem matrix is divided into two pieces by rank (n=100), and first piece of 1-50 behavior, second piece of 51-100 behavior, distribution first is assessed The calculating of the first block system matrix is calculated, another core is responsible for the 2nd piece of system matrix computation, and thus the two cores can concurrently solely It is vertical to calculate the matrix-block being each responsible for.

As shown in Fig. 2, finite element grid includes unit 20,21,22 and 23；The number of node on each unit is nothing Rule, as the node number on No. 20 units is respectively as follows: 14,15,16,17,18,23,24,25.It can be seen that these numbers are Random, it is not in order.

Therefore system stiffness matrix must could be generated line by line in the way of " node scan ".However it must first calculate Cell matrix could obtain sytem matrix；To calculate corresponding (the i-th row) stiffness matrix of i-th of node, it is necessary to calculate and save with i The connected all cell matrixs sub-block relevant to i-node of point, the information of this unit for just needing to be connected with each node, i.e., " node correlation unit information ".

In this example embodiment, " the node correlation unit information " includes being connected in finite element grid with each node Unit number and unit number number.In 2 dimension grid as shown in Figure 2, the unit being connected with node " 2 " only has 1, list Member number is 21；The unit being connected with node 15 has 2, and unit number is respectively 20,21；The unit being connected with node 16 has 3, list Member number is respectively 20,21,22, and the node being connected with node 25 has 3, and unit number is respectively 20,22,23.

In this example embodiment, the finite element fraction analysis apparatus interior joint correlation unit information acquisition method provided can be with Include:

S11. using the 1st node in finite element grid as currently processed node；

S13. using the 1st unit in finite element grid as current processing unit；

S15. the element number currently processed node connected increases by 1；

S17. the element number of currently processed node connection is obtained；

Further, in the step S18 of the finite element fraction analysis apparatus interior joint correlation unit information acquisition method, sentencing When the currently processed node that breaks is the last one node, step S21 can be gone to；The acquisition methods further include:

S21. using the 1st node in finite element grid as currently processed node；

S22. using the 1st unit in finite element grid as current processing unit；

To reduce calculation amount, it is also possible to the step of the finite element fraction analysis apparatus interior joint correlation unit information acquisition method In rapid S18, when judging currently processed node for the last one node, step S21 can be gone to；The acquisition methods also wrap It includes:

S22. using the 1st unit in finite element grid as current processing unit；

In the following, above-mentioned steps S11 to step S27 is illustrated:

In this example embodiment, the total node number of finite element grid is nNode, and provides that minimum node number is 1, maximum Node number is nNode, and node is from 1 to nNode serial number；Total unit number of finite element grid is nElment, and is provided most Junior unit number is 1, and largest unit number is nElment, and unit is from 1 to nElment serial number.

In this example embodiment, data structure setting can be configured first, main includes setting nodal information Data structure Node and setting unit information data structure Element.

For example, nodal information data structure Node (with C++ sign flag) is arranged may include:

Be arranged the number of degrees of freedom, of each node, degree of freedom on a node basis array pointer, the number of unit being coupled and its Unit number array pointer, coupled interstitial content and coupled node number array pointer of connection etc..

For example, setting unit information data structure Element (with C++ sign flag) may include:

That is setting unit style number, unit group number, material number, the number of nodes of unit, node number array pointer of unit etc. Deng.

Wherein the corresponding cell type of unit class model can be as shown in Table 1 below:

1 cell type of table

In this example embodiment, the calculating of node correlation unit information may include:

1) the first one-dimension array ND is set, and the element in array is above-mentioned nodal information data structure；Such as:

ND=new Node [nNode]；

First one-dimension array length is nNode；ND [i] -> nEl in array (i=0 ... nNode-1) each node of storage Contiguous location number.

Can also include being initialized to the first one-dimension array ND in this example embodiment:

ND [i] -> nEl=0 (i=1 ... nNode)；

ND [i] -> ei [j] (j=1 ... ND [i] -> nEl) the connected unit number of storage node.

2) the second one-dimension array EL is set, and the element in array is above-mentioned unit information data structure；Such as:

EL=new Element [nElment]；

3) input unit information:

EL [i], i=1 ..nElment；

Include:

Unit class model EL [i] -> mat；

Unit material item number EL [i] -> type；

According to unit class model, referring to 1 setting unit number of nodes of table: EL [i] -> num；

Cell node number is stored in array EL [i] -> ie [j] (j=1 ..., EL [i] -> num).

4) node circulation is carried out

For (iNode=1；INode≤nNode；iNode++)

{

5) unit circulation is carried out:

For (iElem=1；IElem≤nElment；iElem++)

{

6) cell node circulation is carried out for each unit iElem:

For (j=1；J≤EL [i] -> num；j++)

{

If 7):

I=EL [i] -> ie [j], then

ND [i] -> nEl increases by 1, i.e. ND [i] -> nEl=ND [i] -> nEl+1；It goes to step 5) and carries out next unit It calculates.

8) j increases by 1, returns 6), when j is equal to EL [i] -> num, loop termination turns lower step.

}

9) iElem increases by 1, returns 5), when iElem is equal to nElment, loop termination turns lower step.

}

10) space of ND [iNode] -> nEl integer is distributed for array ND [iNode] -> ei

ND [iNode] -> ei=new int [ND [iNode] -> nEl]；

11) iNode increases by 1, returns 4), when iNode is equal to nNode, loop termination turns lower step.

}

12) node circulation is carried out

For (iNode=1；INode≤nNode；iNode++)

{

If n is equal to 0:n=0；

13) unit circulation is carried out:

For (iElem=1；IElem≤nElment；iElem++)

{

If n is greater than or equal to ND [i] -> nEl:if (n >=ND [i] -> nEl), goes to step 12) and carry out next node It calculates.

14) cell node circulation is carried out for each unit iElem:

For (j=1；J≤EL [i] -> num；j++)

{

If EL [i] -> ie [j] is equal to iNode:if (EL [i] -> ie [j] -1==iNode), then:

ND [iNode] -> ei [n]=iElem；(showing what node i Node and unit iElem were connected to)

N increases 1:n=n+1；

It goes to step 13) and carries out next unit calculating

15) j increases by 1, returns 14), when j is equal to EL [i] -> num, loop termination turns lower step.

16) iElem increases by 1, returns 13), when iElem is equal to nElment, loop termination turns lower step.

}

17) iNode increases by 1, returns 12), when iNode is equal to nNode, loop termination turns lower step.

}

Terminate.

Further, sytem matrix parallel generation in a kind of finite element fraction analysis apparatus is additionally provided in this example embodiment Method, comprising:

S35. the element number and unit number of the unit of currently processed node connection are obtained, and with currently processed node company The 1st unit in the unit connect is current processing unit；Wherein, it is obtained by acquisition methods above-mentioned in this example embodiment The element number and unit number of the unit of currently processed node connection；

In the following, above-mentioned steps S31 to step S39 is illustrated:

1) computer core number nCpu, node total number: nNode are obtained.

2) the starting behavior the first row of first core sytem matrix to be processed is set:

NLine1=1；

3) computer core number circulation is carried out

For (iCpu=1；ICpu≤nCpu；iCpu++)

{

Calculate the termination row nLine2 of i-th Cpu core sytem matrix to be processed:

NLine2=nLine1+nNode/nCpu；

4) the i-th Cpu thread is created

5) in the i-th Cpu thread internal segment dot cycle

For (iNode=nLine1；INode≤nLine2；iNode++)

{

6) iNode node correlation unit recycles

For (j=1；J≤ND [iNode] -> nEl；j++)

{

Correlation unit iElement assignment:

IElement=ND [i] -> ei [j]；

7) cell matrix sub-block relevant to iNode node is calculated to iElement unit

8) 7) the cell matrix sub-block calculated is assembled into the i-th Node row of sytem matrix

9) j increases by 1:

J=j+1；

It is back to step 6), as j=ND [iNode] -> nEl, turns lower step.

10) iNode increases by 1:

INode=1+iNode；

It is back to step 5), as iNode=nLine2, turns lower step.

11) after iCpu thread, iCpu increases by 1:

ICpu=1+iCpu；

It is back to step 3), as iCpu=nCpu, turns lower step.

12) terminate.

Method in this example embodiment has at least the following advantages, and the following of the disclosure have obtained many experiments Verifying.

It should be noted that although describing each step of method in the disclosure in the accompanying drawings with particular order, This does not require that or implies must execute these steps in this particular order, or have to carry out step shown in whole Just it is able to achieve desired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and held by certain steps Row, and/or a step is decomposed into execution of multiple steps etc..

Fig. 4 shows the schematic diagram according to finite element fraction analysis apparatus 400 a kind of in disclosure example embodiment.For example, dress Setting 400 may be provided as a server.Referring to Fig. 4, device 400 includes processing component 422, further comprises one or more A processor, and the memory resource as representated by memory 432, can be by the finger of the execution of processing component 422 for storing It enables, such as application program.The application program stored in memory 432 may include it is one or more each correspond to The module of one group of instruction.In addition, processing component 422 is configured as executing instruction, to execute the above method.

Device 400 can also include the power management that a power supply module 426 is configured as executive device 400, and one has Line or radio network interface 450 are configured as device 400 being connected to network and input and output (I/O) interface 458.Dress Setting 400 can operate based on the operating system for being stored in memory 432, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM or similar.

Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by following Claim is pointed out.

It should be understood that the present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and And various modifications and changes may be made without departing from the scope thereof.The scope of the present disclosure is only limited by the accompanying claims.

Claims

1. a kind of finite element fraction analysis apparatus interior joint correlation unit information acquisition method characterized by comprising

S11. using the 1st node in finite element grid as currently processed node；

S13. using the 1st unit in finite element grid as current processing unit；

S14. judge in the node of the current processing unit with the presence or absence of the currently processed node；If it is present going to Step S15, if it does not exist, then going to step S14；

S15. the element number currently processed node connected increases by 1；

S16. judge whether current processing unit is the last one unit, if it is, going to step S17；If it is not, then to work as The next unit of pretreatment unit goes to step S14 as current processing unit；

S17. the element number of currently processed node connection is obtained；

S18. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with currently processed The next node of node goes to step S12 as currently processed node.

2. finite element fraction analysis apparatus interior joint correlation unit information acquisition method according to claim 1, which is characterized in that Wherein, in the step S18, when judging currently processed node for the last one node, step S21 is gone to；The acquisition side Method further include:

S21. using the 1st node in finite element grid as currently processed node；

S22. using the 1st unit in finite element grid as current processing unit；

S23. judge in the node of the current processing unit with the presence or absence of the currently processed node；If it is present going to Step S24, if it does not exist, then going to step S25；

S25. judge whether current processing unit is the last one unit, if it is, going to step S26；If it is not, then to work as The next unit of pretreatment unit goes to step S23 as current processing unit；

S26. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with currently processed The next node of node goes to step S22 as currently processed node.

3. finite element fraction analysis apparatus interior joint correlation unit information acquisition method according to claim 1, which is characterized in that Wherein, in the step S18, when judging currently processed node for the last one node, step S21 is gone to；The acquisition side Method further include:

S21. using the 1st node in finite element grid as currently processed node, and Integer n is set equal to 0；

S22. using the 1st unit in finite element grid as current processing unit；

S25. judge whether n is less than the element number of the currently processed node connection: if it is less, going to step S26, such as Fruit is not less than, then goes to step S27；

S26. judge whether current processing unit is the last one unit, if it is, going to step S27；If it is not, then to work as The next unit of pretreatment unit goes to step S23 as current processing unit；

S27. judge whether currently processed node is the last one node, if it is, terminating；If it is not, then with currently processed The next node of node goes to step S22 as currently processed node.

4. sytem matrix parallel generation method in a kind of finite element fraction analysis apparatus characterized by comprising

S31. the node total number nNode in computer core number and finite element grid is obtained, and using the 1st core as currently Processing core；

S35. the element number and unit number of the unit of currently processed node connection are obtained, and with the connection of currently processed node The 1st unit in unit is current processing unit；Wherein, worked as by the acquisition of method described in claims 1 to 3 any one The element number and unit number of the unit of pre-treatment node connection；

S36. using the current processing unit computing system matrix sub block and to be assembled into the currently processed node corresponding Sytem matrix row in；

S37. judge whether current processing unit is the last one unit in the unit of currently processed node connection, if so, Then go to step S38；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S36；

S38. judge whether the currently processed node is the corresponding node of the termination row, if it is, going to step S39； If it is not, then using the next node of currently processed node as currently processed node, and go to step S35；

S39. using next core of currently processed core as currently processed core, and step S32 is gone to, until the last one institute Core processing is stated to finish.

5. a kind of finite element fraction analysis apparatus characterized by comprising

Processor；And

Memory, for storing the executable instruction of the processor；

S11. using the 1st node in finite element grid as currently processed node；

S13. using the 1st unit in finite element grid as current processing unit；

S15. the element number currently processed node connected increases by 1；

S17. the element number of currently processed node connection is obtained；