CN105700612A - Voltage regulator - Google Patents

Voltage regulator Download PDF

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Publication number
CN105700612A
CN105700612A CN201610059049.3A CN201610059049A CN105700612A CN 105700612 A CN105700612 A CN 105700612A CN 201610059049 A CN201610059049 A CN 201610059049A CN 105700612 A CN105700612 A CN 105700612A
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China
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pmos
voltage regulator
couples
couple
grid
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CN201610059049.3A
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CN105700612B (en
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徐光磊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

A voltage regulator comprises an error amplifier, a second discharge channel and a regulating pipe. The error amplifier comprises a first discharge channel and a bias power source, wherein the first discharge channel is coupled between the control end of the regulating pipe and a ground wire, and the discharge current of the first discharge channel is not larger than the maximum output current of the bias power source. The input end of the regulating pipe is coupled with a preset voltage source, the output end of the regulating pipe is coupled with the output end of the voltage regulator, the control end of the regulating pipe is coupled with the input end of the first discharge channel and the input end of the second discharge channel, and the potential of the control end and the voltage of the output end of the voltage regulator change in the same direction. The second discharge channel is coupled between the control end of the regulating pipe and the ground wire. The sum of the discharge current of the first discharge channel and the discharge current of the second discharge channel and the potential of the control end of the regulating pipe change in opposite directions. The voltage regulator has high response speed.

Description

Voltage regulator
Technical field
The present invention relates to electronic applications, particularly relate to a kind of voltage regulator。
Background technology
Along with the development of electronic technology, the application of voltage regulator is more and more extensive。Such as, a lot of analog circuits, radio circuit, memory circuitry and SOC(system on a chip) (SystemOnaChip, SoC) etc.。
In actual applications, when load current changes, it usually needs voltage regulator can provide response speed faster。In traditional voltage regulator, when load current changes suddenly, the discharge and recharge of electric capacity is responded by voltage regulator usually by bias current, and response time depends on the bias current charge/discharge rates to electric capacity。
There is the problem that response speed is slower in traditional voltage regulator。
Summary of the invention
Present invention solves the technical problem that the response speed being how to improve voltage regulator。
For solving above-mentioned technical problem, the embodiment of the present invention provides a kind of voltage regulator, including: error amplifier, the second discharge path and adjustment pipe, wherein:
Described error amplifier includes the first discharge path, and described first discharge path is coupled between control end and the ground wire of described adjustment pipe, and including bias current sources, and the discharge current of described first discharge path is not more than the maximum output current of described bias current sources；
The described pipe that adjusts, input and predeterminated voltage source couple；The outfan of outfan and described voltage regulator couples；The input controlling end and the input of the first discharge path, described second discharge path couples, and the current potential of described control end changes in the same direction with the output end voltage of described voltage regulator；
Described second discharge path, is coupled between control end and the ground wire of described adjustment pipe；The discharge current sum of the discharge current of described first discharge path and described second discharge path is with the current potential inverse change controlling end of described adjustment pipe。
Optionally, described adjustment pipe is the first PMOS, and the source electrode of described first PMOS is the input of described adjustment pipe, and grid is the control end of described adjustment pipe, and drain the outfan into described adjustment pipe。
Optionally, described second discharge path includes: the second PMOS, the first NMOS tube and the second NMOS tube, wherein: the source electrode of described second PMOS and described predeterminated voltage source couple, the grid of grid and described first PMOS couples, and the drain electrode of drain electrode and described first NMOS tube couples；The grid of described first NMOS tube and drain electrode couple, and source electrode and ground wire couple；The grid of the grid of described second NMOS tube and described first NMOS tube couples, and the input of drain electrode and described bias current sources couples, and outfan and the ground wire of source electrode and described bias current sources couple。
Optionally, described voltage regulator also includes: zero compensation circuit, is coupled between the outfan of described error amplifier and described voltage regulator, and the stability being suitable to the loop to described voltage regulator compensates。
Optionally, described zero compensation circuit includes: impedance unit and the first electric capacity, and wherein: described first electric capacity, the grid of the first end and described second PMOS couples, and the first end of the second end and described impedance unit couples；The outfan of described impedance unit, the second end and described voltage regulator couples。
Optionally, described impedance unit includes: the 3rd PMOS, the 4th PMOS and the 3rd NMOS tube, and wherein: described first electric capacity is miller capacitance, the grid of the first end and described second PMOS couples, and the source electrode of the second end and described 3rd PMOS couples；Grid and the drain electrode of described 3rd PMOS, grid and described 4th PMOS couple, and the source electrode of drain electrode and described 4th PMOS couples；Described 4th PMOS, the source electrode of drain electrode and described 3rd NMOS tube couples；The drain electrode of described 3rd NMOS tube, grid and described first NMOS tube couples, and source electrode and ground wire couple。
Optionally, described error amplifier and sampling resistor couple, and the output end voltage of described voltage regulator being suitable to collect described sampling resistor compares with reference voltage。
Optionally, described sampling resistor includes the first resistance and the second resistance, and wherein: the first end of described first resistance and the outfan of described voltage regulator couple, the second end and described error amplifier couple；First end of the first end of described second resistance and described first resistance couples, the second end with couple。
Optionally, described error amplifier includes: the 5th PMOS, the 6th PMOS, the 4th NMOS tube, the 5th NMOS tube and bias current sources, wherein: the source electrode of described 5th PMOS and described predeterminated voltage source couple, grid and the drain electrode of grid and described 6th PMOS couple, and the grid of drain electrode and described second PMOS couples；The source electrode of described 6th PMOS and described predeterminated voltage source couple, and the drain electrode of drain electrode and described 5th NMOS tube couples；The input of described 4th NMOS tube, source electrode and described bias current sources couples, grid input reference voltage value, and the drain electrode of drain electrode and described 5th PMOS couples；Described 5th NMOS tube, source electrode couples with the input of described bias current sources and the drain electrode of described second NMOS tube, and the second end of grid and described second resistance couples。
Optionally, described voltage regulator also includes: load capacitance, and the outfan of the first end and described voltage regulator couples, the second end with couple。
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that
First discharge path and the second discharge path are respectively positioned between control end and the ground wire of described adjustment pipe, when the output end voltage of voltage regulator changes, the current potential controlling end adjusting pipe occurs to change in the same direction therewith, now, first discharge path generates the first discharge current, second discharge path generates the second discharge current, and the first discharge current and the second discharge current sum inverse change therewith。When the output end voltage of voltage regulator declines suddenly, the current potential controlling end adjusting pipe decreases, and the first discharge current and the second discharge current sum increase therewith。The control end that the first discharge path and the second discharge path exchange homogeneous tube is adopted to carry out discharge operation, using the first discharge current and the second discharge current sum as bias current, voltage regulator the velocity of discharge controlling end adjusting pipe can be improved, so that can quickly respond output end voltage change。
Further, dynamic impedance unit and miller capacitance is adopted to form zero compensation circuit, it is possible to dynamically the loop of voltage regulator to be compensated, dynamically adjust the stability of the loop of voltage regulator。
Accompanying drawing explanation
Fig. 1 is the structural representation of existing a kind of voltage regulator；
Fig. 2 is the structural representation of the another kind of voltage regulator in the embodiment of the present invention。
Detailed description of the invention
With reference to Fig. 1, give the structural representation of existing a kind of voltage regulator。
Error amplifier is by PMOS MP5, PMOS MP6, NMOS tube MN4, NMOS tube MN5And bias current sources ISConstitute。MP5Source electrode and voltage source VDDCouple, grid and MP6Grid couple, drain electrode and MN4Drain electrode and adjust pipe MP1Grid couple；MP6Source electrode and voltage source VDDCoupling, grid and drain electrode couple, and drain and MN5Drain electrode couple；MN4Grid meet reference voltage VREF, source electrode and bias current sources ISInput couple；MN5Grid and the first sampling resistor R1The second end and the second sampling resistor R2The first end couple, source electrode and bias current sources ISInput couple。Bias current sources ISOutfan and ground wire couple。
Adjust pipe MP1For PMOS, the outfan being suitable for voltage regulator provides driving electric current。MP1Source electrode and voltage source VDDCouple, grid and MN4Drain electrode couple, drain electrode and the outfan of voltage regulator couple。
Outfan V at error amplifier Yu voltage regulatorOUTBetween be coupled with zero compensation circuit。Zero compensation circuit is by resistance R3And electric capacity C1Composition。Resistance R3With electric capacity C1Series connection, and resistance R3The first end and MP1Grid couple, the second end and electric capacity C1The first end couple；Electric capacity C1The outfan of the second end and voltage regulator couple。
First sampling resistor R1And the second sampling resistor R2Be suitable to gather the magnitude of voltage V of the outfan of voltage regulatorOUT, and the magnitude of voltage V that will collectOUTInput to MN5Grid so that error amplifier is by VREFWith VOUTCompare。First sampling resistor R1The second end and the second sampling resistor R2The first end couple；Second sampling resistor R2The second end and ground wire couple。At the outfan of voltage regulator, there is also load resistance C2, load resistance C2The outfan of the first end and voltage regulator couple, the second end and ground wire couple。
With reference to Fig. 1, in existing voltage regulator, when the electric current of the load that the outfan of voltage regulator accesses increases suddenly, the magnitude of voltage V of the outfan of voltage regulatorOUTSuddenly reduce, now, MP1The current potential V of grid (the A point in Fig. 1)ANeed to be reduced to target potential, so that MP1Drain current increase, thus drawing high VOUT。
At VOUTWhen remaining unchanged, MP1Can be regarded as a charge and discharge capacitance。Work as VOUTWhen reducing suddenly, the parasitic capacitance of MP1 carries out discharge operation, via MN4And bias current sources ISThe discharge path of composition discharges。Maximum discharge current value on this discharge path is less than bias current sources ISMaximum output current。Thus have a problem that, work as VOUTSuddenly, when the amplitude of reduction is bigger, owing to discharge current exists the upper limit, the guiding discharge time is longer, therefore have impact on the response speed of voltage regulator。
In embodiments of the present invention, when the output end voltage of voltage regulator changes, the current potential controlling end adjusting pipe occurs to change in the same direction therewith, now, first discharge path generates the first discharge current, second discharge path generates the second discharge current, and the first discharge current and the second discharge current sum inverse change therewith。When the output end voltage of voltage regulator declines suddenly, the current potential controlling end adjusting pipe decreases, and the first discharge current and the second discharge current sum increase therewith。The control end that the first discharge path and the second discharge path exchange homogeneous tube is adopted to carry out discharge operation, using the first discharge current and the second discharge current sum as bias current, voltage regulator the velocity of discharge controlling end adjusting pipe can be improved, so that can quickly respond output end voltage change。
Understandable for enabling the above-mentioned purpose of the present invention, feature and beneficial effect to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail。
With reference to Fig. 2, embodiments provide a kind of voltage regulator, including: error amplifier 201, adjustment pipe 202 and the second discharge path 203。
In being embodied as, error amplifier 201 can include the first discharge path, and the first discharge path includes bias current sources。Described first discharge path is coupled between control end and the ground wire adjusting pipe 202。
In being embodied as, adjust pipe 202 and there is input, outfan and control three ports of end。The outfan of the input and the voltage source preset, outfan and voltage regulator that adjust pipe 202 couples, and controls end and the input of the first discharge path and the input of the second discharge path 203 couples。The outfan adjusting pipe 202 is suitable for the outfan load offer driving electric current of voltage regulator。
When the output end voltage of voltage regulator remains unchanged, adjust pipe 202 and play the effect of discharge and recharge。Adjust and there is bigger parasitic capacitance between control end and the outfan of voltage regulator of pipe 202。When the output end voltage of voltage regulator changes suddenly, the current potential controlling end adjusting pipe 202 also changes therewith in the same direction。Change refers in the same direction: the variation tendency of the current potential controlling end adjusting pipe 202 is identical with the variation tendency of the output end voltage of voltage regulator。That is:, when the output end voltage of voltage regulator increases, the current potential controlling end adjusting pipe 202 increases；When the output end voltage of voltage regulator reduces, the current potential controlling end adjusting pipe 202 reduces。
In being embodied as, the second discharge path 203 can be coupled between control end and the ground wire adjusting pipe 202。When the current potential controlling end adjusting pipe 202 changes, the second discharge path 203 there is also discharge current。When the current potential controlling end adjusting pipe 202 changes, first discharge path and the second discharge path 203 all exist the discharge current of correspondence, discharge current on first discharge path and the discharge current sum on the second discharge path 203 are as total discharge current, and namely total discharge current is adjust discharge current corresponding when the current potential controlling end of pipe 202 changes。
The size of total discharge current and the current potential inverse change controlling end adjusting pipe 202。When adjusting the current potential decline that pipe 202 controls end, total discharge current increases；When adjusting the current potential rising that pipe 202 controls end, total discharge current reduces。
It is to say, in embodiments of the present invention, when the output end voltage of voltage regulator changes, the current potential controlling end adjusting pipe 202 occurs to change in the same direction therewith。When control end current potential change time, the first discharge path and the second discharge path 203 exists correspondence discharge current。When the output end voltage of voltage regulator reduces suddenly, the current potential controlling end adjusting pipe 202 needs to be reduced to target potential, now, is discharged by the first discharge path and the second discharge path 203。Owing to there is bias current sources in the first discharge path, the therefore maximum maximum output current less than bias current sources of the discharge current on the first discharge path, the restriction of the then not biased current source of the discharge current on the second discharge path 203。In discharge process, total discharge current is the discharge current on the first discharge path and the discharge current sum on the second discharge path 203, total discharge current is no longer biased the restriction of the maximum output current of current source, therefore can accelerate to adjust the velocity of discharge controlling end of pipe 202, thus improving the response speed of voltage regulator。
In being embodied as, for the stability of bucking voltage actuator loop, it is possible to arrange zero compensation circuit 204 between error amplifier 201 and the outfan of voltage regulator, by zero compensation circuit 204, the stability of the loop of voltage regulator is compensated。
Structure below in conjunction with the Fig. 2 voltage regulator to providing in the above embodiment of the present invention is described in detail。
With reference to Fig. 2, adjusting pipe 202 is the first PMOS MP1。First PMOS MP1Source electrode be adjust pipe 202 input, grid be adjust pipe 202 control end, drain into adjust pipe 202 outfan。First PMOS MP1Source electrode and predeterminated voltage source VDDCouple, grid and the second PMOS MP2Grid and the 4th NMOS tube MN4Drain electrode couple, drain electrode and the outfan of voltage regulator couple。First PMOS MP1The outfan being suitable for voltage regulator provides driving electric current。
Error amplifier 201 includes the 5th PMOS MP5, the 6th PMOS MP6, the 4th NMOS tube MN4, the 5th NMOS tube MN5And bias current sources IS, wherein:
5th PMOS MP5Source electrode with preset voltage source VDDCouple, grid and MP6Grid couple, drain electrode and MN4Drain electrode and MP1Grid couple；6th PMOS MP6Source electrode with preset voltage source VDDCoupling, grid and drain electrode couple, and drain and MN5Drain electrode couple；4th NMOS tube MN4Grid meet reference voltage VREF, source electrode and bias current sources ISInput couple；5th NMOS tube MN5Grid and the first sampling resistor R1The second end and the second sampling resistor R2The first end couple, source electrode and bias current sources ISInput couple；Bias current sources ISOutfan and ground wire couple。
In error amplifier 201, the 4th NMOS tube MN4And bias current sources ISConstitute the first discharge path。As the first PMOS MP1The current potential of grid when changing, the 4th NMOS tube MN4And bias current sources ISConstitute and the first discharge path exists discharge current。
Second discharge path 203 includes the second PMOS MP2, the first NMOS tube MN1And the second NMOS tube MN2, wherein:
Second PMOS MP2Source electrode with preset voltage source VDDCouple, grid and the first PMOS MP1Grid couple, drain electrode with the first NMOS tube MN1Drain electrode couple；First NMOS tube MN1Source electrode and ground wire couple, drain electrode and self grid couple, grid and the second NMOS tube MN2Grid couple；Second NMOS tube MN2Source electrode and bias current sources ISOutfan and ground wire couple, drain electrode with bias current sources ISInput couple。
As the first PMOS MP1The current potential of grid when changing, the second PMOS MP2, the first NMOS tube MN1And the second NMOS tube MN2There is discharge current in the second discharge path 203 of composition。
For the stability of bucking voltage actuator loop, between error amplifier 201 and the outfan of voltage regulator, it is provided with zero compensation circuit 204。Zero compensation circuit 204 includes impedance unit and the first electric capacity, wherein: the first end of the first electric capacity and the second PMOS MP2Grid couple, the first end of the second end and impedance unit couples；Second end of impedance unit and the outfan of voltage regulator couple。
In actual applications, impedance unit can be resistance, with reference to Fig. 1, constitutes zero compensation circuit by a resistance and the first electric capacity。Impedance unit can also be other kinds of impedance unit。
In embodiments of the present invention, with reference to Fig. 2, impedance unit is by the 3rd PMOS MP3, the 4th PMOS MP4And the 3rd NMOS tube MN3Composition, wherein:
3rd PMOS MP3Grid and described 4th PMOS MP4Grid and drain electrode couple, drain electrode with described 4th PMOS MP4Source electrode couple；4th PMOS MP4Drain electrode and described 3rd NMOS tube MN3Drain electrode couple；3rd NMOS tube MN3Grid and described first NMOS tube MN1Drain electrode couple, source electrode and ground wire couple。
3rd PMOS MP3Impedance the 3rd NMOS tube MN3On electric current be correlated with, as the 3rd NMOS tube MN3On electric current increase time, the 3rd PMOS MP3Impedance reduce；When current reduction on the 3rd NMOS, the 3rd NMOS tube MN3Impedance increase。3rd NMOS tube MN3It is the 3rd PMOS MP3Bias current, the 4th PMOS MP are provided4It is the 3rd PMOS MP3Bias voltage is provided。
First end of the first electric capacity and the second PMOS MP2Grid couple, the second end and the 3rd PMOS MP3Source electrode couple。In an embodiment of the present invention, the first electric capacity is miller capacitance。3rd PMOS MP3Drain electrode couple with the outfan of voltage regulator simultaneously。
From the foregoing it can be that the 3rd PMOS MP3, the 4th PMOS MP4And the 3rd NMOS tube MN3The resistance value of the impedance unit of composition is dynamic。So, the loop of voltage regulator just can be carried out stabiloity compensation by the zero compensation circuit 204 of impedance unit and the first electric capacity composition dynamically。
Voltage regulator also includes the first sampling resistor R1And the second sampling resistor R2, the first sampling resistor R1And the second sampling resistor R2Be suitable to gather the magnitude of voltage V of the outfan of voltage regulatorOUT, and the magnitude of voltage collected is inputted to the 5th NMOS tube MN5Grid so that error amplifier 201 is by reference voltage VREFOutput end voltage V with voltage regulatorOUTCompare。First sampling resistor R1The second end and the second sampling resistor R2The first end couple；Second sampling resistor R2The second end and ground wire couple。
At the outfan of voltage regulator, there is also load resistance C2, load resistance C2The outfan of the first end and voltage regulator couple, the second end and ground wire couple。
Below the operation principle of the voltage regulator provided in Fig. 2 is illustrated。
Output end voltage V at voltage regulatorOUTTime constant, the first PMOS MP1Can be regarded as the electric capacity of a discharge and recharge。When the load current of the outfan of voltage regulator increases suddenly, the output end voltage V of voltage regulatorOUTDragged down by moment, now, the first PMOS MP1The current potential V of grid A pointAMoment reduces。The reduction of A point current potential realizes mainly through discharging。
When the current potential of A point reduces time namely the first PMOS MP1Grid voltage reduce time, the second PMOS MP2Grid voltage reduce so that the second PMOS MP2Drain current increase。Now, the first NMOS tube MN1Drain current increase, correspondingly, the first NMOS tube MN1Grid and the second NMOS tube MN2Grid voltage increase so that the second NMOS tube MN2Source current increase。Now, there is discharge current in the second discharge path 203。
While the current potential of A point reduces, the 4th NMOS tube MN4And bias current sources ISThere is discharge current in the first discharge path of composition。
When the current potential of A point reduces, the first PMOS MP1Drain current increase so that the output end voltage V of voltage regulatorOUTStarting to increase, correspondingly, the current potential of A point is drawn high gradually。When the current potential of A point is driven high, the second PMOS MP2Grid voltage increase。Now, the second PMOS MP2Drain current reduce, the second NMOS tube MN2Grid voltage reduce, the second NMOS tube MN2Source current reduce, namely the discharge current on the second discharge path 203 reduce。
It is to say, in the embodiment of the present invention, when the current potential of A point reduces, discharged by the first discharge path and the second discharge path 203, as early as possible the current potential of A point is pulled down to target potential。Compared with voltage regulator existing with Fig. 1, the discharge current that discharge current is the first discharge path of voltage regulator provided in the embodiment of the present invention and the discharge current sum of the second discharge path 203。
Voltage regulator in Fig. 1, its discharge path is by MN4And bias current sources ISComposition, discharge current is maximum less than bias current sources ISMaximum output current。And in embodiments of the present invention, discharge current is the discharge current sum of the discharge current of the first discharge path and the second discharge path 203, and therefore discharge current can exceed bias current sources ISMaximum output current。It is to say, the voltage regulator provided in the embodiment of the present invention is capable of the velocity of discharge faster, namely response speed is faster。
Although present disclosure is as above, but the present invention is not limited to this。Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range。

Claims (10)

1. a voltage regulator, it is characterised in that including: error amplifier, the second discharge path and adjustment pipe, wherein:
Described error amplifier includes the first discharge path, and described first discharge path is coupled between control end and the ground wire of described adjustment pipe, and including bias current sources, and the discharge current of described first discharge path is not more than the maximum output current of described bias current sources；
The described pipe that adjusts, input and predeterminated voltage source couple；The outfan of outfan and described voltage regulator couples；The input controlling end and the input of the first discharge path, described second discharge path couples, and the current potential of described control end changes in the same direction with the output end voltage of described voltage regulator；
Described second discharge path, is coupled between control end and the ground wire of described adjustment pipe；
The discharge current sum of the discharge current of described first discharge path and described second discharge path is with the current potential inverse change controlling end of described adjustment pipe。
2. voltage regulator as claimed in claim 1, it is characterised in that described adjustment pipe is the first PMOS, and the source electrode of described first PMOS is the input of described adjustment pipe, and grid is the control end of described adjustment pipe, and drain the outfan into described adjustment pipe。
3. voltage regulator as claimed in claim 2, it is characterised in that described second discharge path includes: the second PMOS, the first NMOS tube and the second NMOS tube, wherein:
The source electrode of described second PMOS and described predeterminated voltage source couple, and the grid of grid and described first PMOS couples, and the drain electrode of drain electrode and described first NMOS tube couples；
The grid of described first NMOS tube and drain electrode couple, and source electrode and ground wire couple；
The grid of the grid of described second NMOS tube and described first NMOS tube couples, and the input of drain electrode and described bias current sources couples, and outfan and the ground wire of source electrode and described bias current sources couple。
4. voltage regulator as claimed in claim 3, it is characterised in that also including: zero compensation circuit, be coupled between the outfan of described error amplifier and described voltage regulator, the stability being suitable to the loop to described voltage regulator compensates。
5. voltage regulator as claimed in claim 4, it is characterised in that described zero compensation circuit includes: impedance unit and the first electric capacity, wherein:
The grid of described first electric capacity, the first end and described second PMOS couples, and the first end of the second end and described impedance unit couples；
The outfan of described impedance unit, the second end and described voltage regulator couples。
6. voltage regulator as claimed in claim 5, it is characterised in that described impedance unit includes: the 3rd PMOS, the 4th PMOS and the 3rd NMOS tube, wherein:
Described first electric capacity is miller capacitance, and the grid of the first end and described second PMOS couples, and the source electrode of the second end and described 3rd PMOS couples；
Grid and the drain electrode of described 3rd PMOS, grid and described 4th PMOS couple, and the source electrode of drain electrode and described 4th PMOS couples；
Described 4th PMOS, the source electrode of drain electrode and described 3rd NMOS tube couples；
The drain electrode of described 3rd NMOS tube, grid and described first NMOS tube couples, and source electrode and ground wire couple。
7. voltage regulator as claimed in claim 3, it is characterised in that described error amplifier and sampling resistor couple, the output end voltage of described voltage regulator being suitable to collect described sampling resistor compares with reference voltage。
8. voltage regulator as claimed in claim 7, it is characterised in that described sampling resistor includes the first resistance and the second resistance, wherein:
First end of described first resistance and the outfan of described voltage regulator couple, and the second end and described error amplifier couple；
First end of the first end of described second resistance and described first resistance couples, the second end with couple。
9. voltage regulator as claimed in claim 8, it is characterised in that described error amplifier includes: the 5th PMOS, the 6th PMOS, the 4th NMOS tube, the 5th NMOS tube and bias current sources, wherein:
The source electrode of described 5th PMOS and described predeterminated voltage source couple, and grid and the drain electrode of grid and described 6th PMOS couple, and the grid of drain electrode and described second PMOS couples；
The source electrode of described 6th PMOS and described predeterminated voltage source couple, and the drain electrode of drain electrode and described 5th NMOS tube couples；
The input of described 4th NMOS tube, source electrode and described bias current sources couples, grid input reference voltage value, and the drain electrode of drain electrode and described 5th PMOS couples；
Described 5th NMOS tube, source electrode couples with the input of described bias current sources and the drain electrode of described second NMOS tube, and the second end of grid and described second resistance couples。
10. voltage regulator as claimed in claim 1, it is characterised in that also include: load capacitance, the outfan of the first end and described voltage regulator couples, the second end with couple。
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US10719097B1 (en) 2019-06-13 2020-07-21 Vanguard International Semiconductor Corporation Voltage regulation circuit suitable to provide output voltage to core circuit

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CN103105883A (en) * 2011-11-11 2013-05-15 中国科学院微电子研究所 Linear voltage regulator with load detection circuit and dynamic zero compensation circuit
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI684089B (en) * 2019-04-29 2020-02-01 世界先進積體電路股份有限公司 Voltage regulation circuit
US10719097B1 (en) 2019-06-13 2020-07-21 Vanguard International Semiconductor Corporation Voltage regulation circuit suitable to provide output voltage to core circuit

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