CN105681904A - Method for improving response speed of television - Google Patents
Method for improving response speed of television Download PDFInfo
- Publication number
- CN105681904A CN105681904A CN201610032330.8A CN201610032330A CN105681904A CN 105681904 A CN105681904 A CN 105681904A CN 201610032330 A CN201610032330 A CN 201610032330A CN 105681904 A CN105681904 A CN 105681904A
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- China
- Prior art keywords
- ddr
- response speed
- mode
- write
- read
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
The invention discloses a method for improving a response speed of a television; the method comprises the steps of changing a DDR data read-write manner and changing the DDR data read-write manner from an 8X mode into a 4X mode. According to the method disclosed by the invention, by changing the DDR data read-write manner from the 8X mode into the 4X mode, the DDR core frequency is improved and the DDR read-write climbing time is reduced; and thus, the access efficiency of a DDR is improved, the run time of a rectification system is accelerated, and the response speed and the operation experience of the television are improved.
Description
Technical field
The present invention relates to TV technology, be specifically related to a kind of method improving TV response speed.
Background technology
Along with development in science and technology, shooting ahead of electronic information industry, the performance of tv product is increasingly stronger, and function gets more and more, and consumer is also at increasingly " fastidious ". People start more to pay attention to the experience sense of product, and at this time a operation tv product smooth, fast response time will obtain the favor of consumer.
Current tv product DDR generally adopts the read-write mode of 8XMode, and the response speed of a tv product depends on its hardware configuration. A tv product how in hardware configuration it has been determined that, promote its response speed and operation smoothness sense, become a difficult problem.
Summary of the invention
Instant invention overcomes the deficiencies in the prior art, it is provided that a kind of method improving TV response speed.
For solving above-mentioned technical problem, the present invention by the following technical solutions:
A kind of method improving TV response speed, described method includes changing DDR and reads and writes the mode of data, DDR the mode 8XMode reading and writing data is changed into 4XMode.
Further technical scheme is 8XMode is the DDR data once reading 8Chanel; Described 4XMode is the DDR data once reading 4Chanel.
Compared with prior art, the invention has the beneficial effects as follows: DDR is read and write the mode of data and become 4XMode from 8XMode by the present invention, improve DDR core frequency, reduce the climbing time of DDR read-write thus promoting the access efficiency of DDR, accelerate the operation time of rectification system, promote response speed and the operating experience of television set.
Accompanying drawing explanation
Fig. 1 is the system logic schematic diagram that mode is 8XMode that in one embodiment of the invention, DDR reads and writes data.
Fig. 2 is the system logic schematic diagram that mode is 4XMode that in one embodiment of the invention, DDR reads and writes data.
Fig. 3 is DDR read-write sequence schematic diagram in one embodiment of the invention.
Fig. 4 is CPUFlow schematic diagram in one embodiment of the invention.
Detailed description of the invention
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
This specification (include any accessory claim, summary and accompanying drawing) disclosed in any feature, unless specifically stated otherwise, all can by other equivalences or there is the alternative features of similar purpose replaced. That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in detail.
As shown in Figures 1 to 4, according to one embodiment of present invention, the present embodiment discloses a kind of method improving TV response speed, the method is to change DDR to read and write the mode of data, the mode 8XMode being read and write data by DDR being changed into 4XMode, improves DDR core frequency, reducing the climbing time of DDR read-write thus promoting the access efficiency of DDR, accelerate the operation time of rectification system, promote response speed and the operating experience of television set.
Concrete, as depicted in figs. 1 and 2, the situation of DDR31866MHz32bit:
8XMode:IP, Controller, PHY once read 256bit, frequency 233MHz;
4XMode:IP, Controller, PHY once read 128bit, frequency 466MHz.
Although it is 2 times of 4XMode that 8XMode reads data every time, but the reading frequency of 4XMode is 2 times of 8XMode, so both patterns reading per second bit number is constant.
As shown in Figure 3, DDR utilizes the rising edge of clock and trailing edge to transmit data, the core frequency of 4XMode is the twice of 8XMode, the raising of frequency can make the climbing time of rising edge and trailing edge shorten, shortened, thus adding CPU to do the time of other work the CPU time reading and writing DRAM.
As shown in Figure 4, can be seen that CPU first reads and writes data from DDR from CPUFlow, then process, then read and write again, so circulate.
Improve DDR core frequency, it is possible to shortened, thus shortening the time of read-write the climbing time of rising edge and trailing edge. The time shortening CPURead and CPUWrite can accelerate again the operation time of whole CPU.
The method of the present invention, not only to the DDR31866MHz32bit in above-described embodiment by adopting 4XMode to shorten the operation time of CPU, improves the response speed of system, fluency and experience sense. The tv product of other frequency DDR by adopting 4XMode raising DDR core frequency to shorten the climbing time of DDR read-write, can also be improved read-write efficiency, thus arriving the lifting response speed of whole system, fluency and experience sense.
" embodiment ", " another embodiment ", " embodiment " spoken of in this manual etc., refer to the specific features, structure or the feature that describe in conjunction with this embodiment and include at least one embodiment that the application generality describes. Multiple local appearance statement of the same race is not necessarily refer to same embodiment in the description. Furthermore, it is understood that when describing a specific features, structure or feature in conjunction with any one embodiment, what advocate is also fall within the scope of the present invention to realize this feature, structure or feature in conjunction with other embodiments.
Although reference be made herein to invention has been described for the multiple explanatory embodiment invented, but, it should be understood that those skilled in the art can be designed that a lot of other amendments and embodiment, these amendments and embodiment will drop within spirit disclosed in the present application and spirit. More specifically, in disclosure scope of the claims, it is possible to building block and/or layout to theme composite configuration carry out multiple modification and improvement. Except the modification that building block and/or layout are carried out and improvement, to those skilled in the art, other purposes also will be apparent from.
Claims (2)
1. the method improving TV response speed, it is characterised in that described method includes changing DDR and reads and writes the mode of data, DDR the mode 8XMode reading and writing data is changed into 4XMode.
2. the method for raising TV response speed according to claim 1, it is characterised in that described 8XMode is the DDR data once reading 8Chanel; Described 4XMode is the DDR data once reading 4Chanel.
Priority Applications (1)
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CN201610032330.8A CN105681904A (en) | 2016-01-18 | 2016-01-18 | Method for improving response speed of television |
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CN201610032330.8A CN105681904A (en) | 2016-01-18 | 2016-01-18 | Method for improving response speed of television |
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CN105681904A true CN105681904A (en) | 2016-06-15 |
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CN201610032330.8A Pending CN105681904A (en) | 2016-01-18 | 2016-01-18 | Method for improving response speed of television |
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CN101833424A (en) * | 2010-03-26 | 2010-09-15 | 中国科学院光电技术研究所 | High-speed storage and transmission device based on FPGA |
US20120204079A1 (en) * | 2011-02-08 | 2012-08-09 | Diablo Technologies Inc. | System and method of interfacing co-processors and input/output devices via a main memory system |
US20130194499A1 (en) * | 2012-01-30 | 2013-08-01 | Mstar Semiconductor, Inc. | Television system and method for managing applications therein |
US20140068168A1 (en) * | 2012-08-30 | 2014-03-06 | Imagination Technologies Limited | Tile based interleaving and de-interleaving for digital signal processing |
CN103780506A (en) * | 2012-10-26 | 2014-05-07 | 中兴通讯股份有限公司 | Data caching system and data caching method |
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2016
- 2016-01-18 CN CN201610032330.8A patent/CN105681904A/en active Pending
Patent Citations (7)
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US20040264464A1 (en) * | 2003-06-27 | 2004-12-30 | Broadcom Corporation | Datagram replication in internet protocol multicast switching in a network device |
CN1825479A (en) * | 2005-01-18 | 2006-08-30 | 因芬尼昂技术股份公司 | Improved DDR II dram data path |
CN101833424A (en) * | 2010-03-26 | 2010-09-15 | 中国科学院光电技术研究所 | High-speed storage and transmission device based on FPGA |
US20120204079A1 (en) * | 2011-02-08 | 2012-08-09 | Diablo Technologies Inc. | System and method of interfacing co-processors and input/output devices via a main memory system |
US20130194499A1 (en) * | 2012-01-30 | 2013-08-01 | Mstar Semiconductor, Inc. | Television system and method for managing applications therein |
US20140068168A1 (en) * | 2012-08-30 | 2014-03-06 | Imagination Technologies Limited | Tile based interleaving and de-interleaving for digital signal processing |
CN103780506A (en) * | 2012-10-26 | 2014-05-07 | 中兴通讯股份有限公司 | Data caching system and data caching method |
Non-Patent Citations (1)
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Application publication date: 20160615 |