CN105681716B - A kind of communication channel physical layer circuit of MHL equipment - Google Patents
A kind of communication channel physical layer circuit of MHL equipment Download PDFInfo
- Publication number
- CN105681716B CN105681716B CN201511017355.2A CN201511017355A CN105681716B CN 105681716 B CN105681716 B CN 105681716B CN 201511017355 A CN201511017355 A CN 201511017355A CN 105681716 B CN105681716 B CN 105681716B
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- resistance
- switching tube
- communication channel
- switch pipe
- physical layer
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
Abstract
The application provides a kind of communication channel physical layer circuit of MHL equipment, by the specific type of attachment of first switch pipe, second switch pipe, third switching tube, the 4th switching tube, the 5th switching tube, first resistor, second resistance, 3rd resistor and conduction threshold adjustment module, the connection between FPGA platform and communication channel chip is realized；And then the signal of FPGA platform and communication channel chip can be received by above-mentioned each component, make to realize communication and verification between the two, while avoiding and being attached caused resources of chip waste using other chips.
Description
Technical field
The present invention relates to MHL equipment technical fields more particularly to a kind of communication channel physical layer circuits of MHL equipment.
Background technology
MHL (Mobile High-Definition Link, mobile terminal high-definition audio and video standard interface) is a kind of high speed number
Word signal transmission standard is mainly used for transmitting audio-video signal；It is generally answered on high definition television, mobile phone or player at present
With.And MHL equipment generally refers to the mobile phone with MHL functions or tablet computer etc..
Generally use FPGA (Field-Programmable Gate Array, field-programmable gate array in the prior art
Row) platform carries out digital code verification for the communication channel chip of MHL equipment, and it is that communication channel chip finds it before manufacture
The defect of Digital Design.
But lack special communication channel physical chip or circuit in the prior art to realize FPGA platform and communication
Connection between channel chip, and realize that above-mentioned connection would generally cause the wasting of resources of connection chip using other chips.
Invention content
In view of this, the present invention provides a kind of communication channel physical layer circuit of MHL equipment, with realize FPGA platform with
Connection between communication channel chip.
To achieve the goals above, technical solution provided in an embodiment of the present invention is as follows：
A kind of communication channel physical layer circuit of MHL equipment is connected to on-site programmable gate array FPGA platform and communication
Between channel chip；The communication channel physical layer circuit of the mobile terminal high-definition audio and video standard interface MHL equipment includes：
First switch pipe, second switch pipe, third switching tube, the 4th switching tube, the 5th switching tube, first resistor, second
Resistance, 3rd resistor and conduction threshold adjustment module；Wherein：
The first end of the first switch pipe is connected with the first power supply；
The second end of the first switch pipe and third end, the first end of the second switch pipe, the third switching tube
Control terminal, one end of the second resistance and CBUS pin of the one end with the communication channel chip of the 3rd resistor
It is connected；
The second end of the second switch pipe and third end, the second end of the third switching tube, the 4th switching tube
Second end and the second end and third end of third end and the 5th switching tube be grounded；
The other end of the second resistance is connected with the first end of the 4th switching tube；
The other end of the 3rd resistor is connected with the first end of the 5th switching tube；
The control terminal of the first switch pipe, the control terminal of the second switch pipe, the first end of the third switching tube,
The control terminal of 4th switching tube and the control terminal of the 5th switching tube are connected with the FPGA platform respectively；
The first resistor is connected between the first end and second source of the third switching tube；
The conduction threshold adjustment module respectively with the third end of the third switching tube, first power supply and ground phase
Even.
Preferably, the conduction threshold adjustment module includes：4th resistance, the 5th resistance, the 6th resistance and the 7th resistance；
Wherein：
One end of 4th resistance is connected with first power supply；
The other end of 4th resistance, one end of the 5th resistance, the 6th resistance one end and the described 7th
One end of resistance is connected with the third end of the third switching tube；
The other end, the other end of the 6th resistance and the other end of the 7th resistance of 5th resistance connect
Ground.
Preferably, the resistance value of the first resistor and the second resistance is 1K Ω, and the resistance value of the 3rd resistor is
100KΩ。
Preferably, the resistance value of the 4th resistance is 1K Ω, and the resistance value of the 6th resistance and the 7th resistance is 2K
The resistance value of Ω, the 5th resistance are 470 Ω.
Preferably, the first switch pipe, the second switch pipe, the third switching tube, the 4th switching tube and
5th switching tube is NMOS transistor.
Preferably, the model BSS83 of the NMOS transistor.
Preferably, the output voltage of first power supply is 1.8V.
Preferably, the output voltage of the second source is 3.3V.
The application provides a kind of communication channel physical layer circuit of MHL equipment, by first switch pipe, second switch pipe,
Third switching tube, the 4th switching tube, the 5th switching tube, first resistor, second resistance, 3rd resistor and conduction threshold adjustment module
Specific type of attachment, realize the connection between FPGA platform and communication channel chip；And then above-mentioned each member can be passed through
Device receives the signal of FPGA platform and communication channel chip, makes to realize communication and verification between the two, avoid simultaneously
Caused resources of chip waste is attached using other chips.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of the communication channel physical layer circuit of MHL equipment provided by the embodiments of the present application；
Fig. 2 is the structural representation of the communication channel physical layer circuit for another MHL equipment that another embodiment of the application provides
Figure.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of communication channel physical layer circuits of MHL equipment, to realize FPGA platform and communication channel
Connection between chip.
Specifically, the communication channel physical layer circuit of the MHL equipment, as shown in Figure 1, being connected to FPGA platform and communication
Between channel chip；The communication channel physical layer circuit of the MHL equipment includes：
First switch pipe Q1, second switch pipe Q2, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5, first
Resistance R1, second resistance R2,3rd resistor R3 and conduction threshold adjustment module 101；Wherein：
The first end of first switch pipe Q1 is connected with the first power supply VCC1；
The control of the second end of first switch pipe Q1 and third end, the first end of second switch pipe Q2, third switching tube Q3
The one end at end, one end of second resistance R2 and 3rd resistor R3 is connected with the CBUS pins of the communication channel chip；
The second end of second switch pipe Q2 and third end, the second end of third switching tube Q3, the 4th switching tube Q4 second
The second end and third end of end and third end and the 5th switching tube Q5 are grounded；
The other end of second resistance R2 is connected with the first end of the 4th switching tube Q4；
The other end of 3rd resistor R3 is connected with the first end of the 5th switching tube Q5；
The control terminal of first switch pipe Q1, the control terminal of second switch pipe Q2, the first end of third switching tube Q3, the 4th open
The control terminal of the control terminal and the 5th switching tube Q5 of closing pipe Q4 is connected with the FPGA platform respectively；
First resistor R1 is connected between the first end and second source VCC2 of third switching tube Q3；
Conduction threshold adjustment module 101 is connected with the third end of third switching tube Q3, the first power supply VCC1 and ground respectively.
Specifically operation principle is：
Equipment identification process：Described in the control terminal of first switch pipe Q1, second switch pipe Q2 and the 5th switching tube Q5 receive
The input signal of FPGA platform, first switch pipe Q1, second switch pipe Q2 and the 5th switching tube Q5 shutdowns, and it is logical to the communication
The signal high resistant of the CBUS pins of road chip；The control terminal of 4th switching tube Q4 receives the input signal of the FPGA platform, the
Four switching tube Q4 are closed, and the signal of the CBUS pins of the communication channel chip is pulled down to by the resistance value over the ground for second resistance R2
GND meets the criterion of identification of the MHL equipment, completes the equipment identification process of the MHL equipment.
Prepare communication process：After the completion of the equipment identification process, the MHL equipment is considered as it and has been coupled to separately
An outer MHL equipment, begins through the identification pulse that CBUS pins send specific length, and third switching tube Q3 receives this pulse simultaneously
It is sent to the FPGA platform by its first end；According to MHL agreements, the FPGA platform can control the 4th switching tube Q4 at this time
Shutdown, and control the 5th switching tube Q5 and be closed, the signal of the CBUS pins of the communication channel chip is by being 3rd resistor over the ground
The resistance value of R3 pulls down to GND.The MHL equipment detects that the variation of the signal of CBUS pins, the inside of the MHL equipment also can
Corresponding adjustment is done, so far, prepares communication process and completes.
Communication process：The MHL equipment converts signals into the FPGA platform by third switching tube Q3 and can be compatible with
Level value, complete communication of the MHL equipment to the FPGA platform；The FPGA platform is by being input to first switch pipe
The signal value of the control terminal of Q1 and second switch pipe Q2 controls the break-make of first switch pipe Q1 and second switch pipe Q2, and then comes
It realizes and the signal of CBUS pins is inputted, complete communication of the FPGA platform to the MHL equipment.
It is worth noting that once after the completion of the equipment identification process, the communication channel physical layer electricity of the MHL equipment
Road will be always maintained at communication state, until the MHL equipment disconnects the connection with the MHL equipment, then communication needs to connect again
It connects and identifies.
The communication channel physical layer circuit of the MHL equipment provided in this embodiment, specific by above-mentioned component connect
Form is connect, the connection between FPGA platform and communication channel chip is realized；And FPGA platform is received by above-mentioned each process
With the signal of communication channel chip, make to realize communication and verification between the two, while avoiding and being carried out using other chips
Resources of chip waste caused by connection.
In addition, the communication channel physical layer circuit of the MHL equipment, is all built using above-mentioned resolution element, it is at low cost
And easily obtain, logic is simple, suitable for the fireballing chip field that currently updates.
Preferably, as shown in Fig. 2, conduction threshold adjustment module 101 includes：4th resistance R4, the 5th resistance R5, the 6th electricity
Hinder R6 and the 7th resistance R7；Wherein：
One end of 4th resistance R4 is connected with the first power supply VCC1；
The other end of 4th resistance R4, one end of the 5th resistance R5, one end of the 6th resistance R6 and the 7th resistance R7 one
End is connected with the third end of third switching tube Q3；
The other end, the other end of the 6th resistance R6 and the other end of the 7th resistance R7 of 5th resistance R5 is grounded.
Preferably, it is 100K Ω that the resistance value of first resistor R1 and second resistance R2, which are the resistance value of 1K Ω, 3rd resistor R3,.
Preferably, it is 2K Ω that the resistance value of the 4th resistance R4, which is the resistance value of 1K Ω, the 6th resistance R6 and the 7th resistance R7, the 5th
The resistance value of resistance R5 is 470 Ω.
Preferably, first switch pipe Q1, second switch pipe Q2, third switching tube Q3, the switches of the 4th switching tube Q4 and the 5th
Pipe Q5 is NMOS transistor.
Correspondingly, the first end of the corresponding each switching tube of the drain electrode of the NMOS transistor, source electrode correspond to each switch
The second end of pipe, grid correspond to the control terminal of each switching tube, and substrate corresponds to the third end of each switching tube.
Preferably, the model BSS83 of the NMOS transistor.
BSS83 is a kind of 4 foot metal-oxide-semiconductors, and speed is higher, and capacitance is small, can meet the CBUS communication needs of 1M speed；And
And the threshold value of each switching tube conducting can be controlled by the way that the voltage value of its substrate is arranged, this so that third switching tube Q3 can be with
Receive the signal of the 1.8V level of the CBUS pins output.
Preferably, the output voltage of the first power supply VCC1 is 1.8V.
Preferably, the output voltage of second source VCC2 is 3.3V.
The identification pulse for the specific length that the MHL equipment is sent by CBUS pins is 1.8V level, and the FPGA
Platform can be compatible with 3.3V level values.
In the equipment identification process, the control of first switch pipe Q1, second switch pipe Q2 and the 5th switching tube Q5 terminate
The input signal for the FPGA platform received is low level, and first switch pipe Q1, second switch pipe Q2 and the 5th switching tube Q5 are closed
It is disconnected；The input signal that the control terminal of 4th switching tube Q4 receives the FPGA platform is high level, and the 4th switching tube Q4 is closed.
In the preparation communication process, the identification pulse for the specific length that the MHL equipment is sent by CBUS pins is
1.8V level, third switching tube Q3 receive this pulse and are sent to the FPGA platform by its first end；According to MHL agreements,
The FPGA platform exports low level to the control terminal of the 4th switching tube Q4 at this time, and exports high level to the 5th switching tube Q5's
Control terminal.
In the communication process, the MHL equipment converts signals into the FPGA platform energy by third switching tube Q3
Enough compatible 3.3V level values, complete communication of the MHL equipment to the FPGA platform；The FPGA platform is by being input to
The signal value of the control terminal of first switch pipe Q1 and second switch pipe Q2, control first switch pipe Q1's and second switch pipe Q2 is logical
It is disconnected, and then realize the signal input to CBUS pins, complete communication of the FPGA platform to the MHL equipment.
Each embodiment is described by the way of progressive in the present invention, the highlights of each of the examples are with other realities
Apply the difference of example, just to refer each other for identical similar portion between each embodiment.For device disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related place is referring to method part illustration
?.
It the above is only the preferred embodiment of the present invention, make skilled artisans appreciate that or realizing of the invention.It is right
A variety of modifications of these embodiments will be apparent to one skilled in the art, general original as defined herein
Reason can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, the present invention will not
Be intended to be limited to the embodiments shown herein, and be to fit to it is consistent with the principles and novel features disclosed in this article most
Wide range.
Claims (8)
1. a kind of communication channel physical layer circuit of MHL equipment, which is characterized in that it is flat to be connected to on-site programmable gate array FPGA
Between platform and communication channel chip；The communication channel physical layer circuit of mobile terminal high-definition audio and video standard interface MHL equipment includes：
First switch pipe, second switch pipe, third switching tube, the 4th switching tube, the 5th switching tube, first resistor, second resistance,
3rd resistor and conduction threshold adjustment module；Wherein：
The first end of the first switch pipe is connected with the first power supply；
The second end of the first switch pipe and third end, the second switch pipe first end, the third switching tube control
The one end at end processed, one end of the second resistance and the 3rd resistor with the CBUS pin phases of the communication channel chip
Even；
The second end of the second switch pipe and third end, the second end of the third switching tube, the 4th switching tube
The second end and third end of two ends and third end and the 5th switching tube are grounded；
The other end of the second resistance is connected with the first end of the 4th switching tube；
The other end of the 3rd resistor is connected with the first end of the 5th switching tube；
It is the control terminal of the first switch pipe, the control terminal of the second switch pipe, the first end of the third switching tube, described
The control terminal of 4th switching tube and the control terminal of the 5th switching tube are connected with the FPGA platform respectively；
The first resistor is connected between the first end and second source of the third switching tube；
The conduction threshold adjustment module is connected with the third end of the third switching tube, first power supply and ground respectively.
2. the communication channel physical layer circuit of MHL equipment according to claim 1, which is characterized in that the conduction threshold
Adjustment module includes：4th resistance, the 5th resistance, the 6th resistance and the 7th resistance；Wherein：
One end of 4th resistance is connected with first power supply；
The other end, one end of the 5th resistance, one end of the 6th resistance and the 7th resistance of 4th resistance
One end be connected with the third end of the third switching tube；
The other end, the other end of the 6th resistance and the other end of the 7th resistance of 5th resistance are grounded.
3. the communication channel physical layer circuit of MHL equipment according to claim 1, which is characterized in that the first resistor
Resistance value with the second resistance is 1K Ω, and the resistance value of the 3rd resistor is 100K Ω.
4. the communication channel physical layer circuit of MHL equipment according to claim 2, which is characterized in that the 4th resistance
Resistance value be 1K Ω, the resistance value of the 6th resistance and the 7th resistance is 2K Ω, and the resistance value of the 5th resistance is 470
Ω。
5. the communication channel physical layer circuit of MHL equipment according to claim 1, which is characterized in that the first switch
Pipe, the second switch pipe, the third switching tube, the 4th switching tube and the 5th switching tube are NMOS crystal
Pipe.
6. the communication channel physical layer circuit of MHL equipment according to claim 5, which is characterized in that the NMOS crystal
The model BSS83 of pipe.
7. the communication channel physical layer circuit of MHL equipment according to claim 1, which is characterized in that first power supply
Output voltage be 1.8V.
8. the communication channel physical layer circuit of MHL equipment according to claim 1, which is characterized in that the second source
Output voltage be 3.3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511017355.2A CN105681716B (en) | 2015-12-29 | 2015-12-29 | A kind of communication channel physical layer circuit of MHL equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511017355.2A CN105681716B (en) | 2015-12-29 | 2015-12-29 | A kind of communication channel physical layer circuit of MHL equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105681716A CN105681716A (en) | 2016-06-15 |
| CN105681716B true CN105681716B (en) | 2018-11-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511017355.2A Active CN105681716B (en) | 2015-12-29 | 2015-12-29 | A kind of communication channel physical layer circuit of MHL equipment |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204906555U (en) * | 2015-04-28 | 2015-12-23 | 惠州市康冠科技有限公司 | Reduced form MHL control circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014101088A1 (en) * | 2012-12-28 | 2014-07-03 | Silicon Image, Inc. | Compensation scheme for mhl common mode clock swing |
-
2015
- 2015-12-29 CN CN201511017355.2A patent/CN105681716B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204906555U (en) * | 2015-04-28 | 2015-12-23 | 惠州市康冠科技有限公司 | Reduced form MHL control circuit |
Non-Patent Citations (2)
| Title |
|---|
| MHL在电视机上的电路实现方法;敬奕艳等;《电视技术》;20141031;第38卷(第20期);第48-50页 * |
| Optimal Common-mode Choke Selection for the High Definition Video Interface for the Mobile Application;Junwoo Lee等;《Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd》;20130531;第2058-2062页 * |
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| Publication number | Publication date |
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| CN105681716A (en) | 2016-06-15 |
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